A Novel DPS Integrator for Fast CMOS Imagers

Transcription

1 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 1/17 A Novel DPS Integrator for Fast CMOS Imagers J. M. Margarit, J. Sabadell, L. Terés and F. Serra-Graells System Integration Department Institut de Microelectrònica de Barcelona Centro Nacional de Microelectrónica - CSIC Spain May 2008

2 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 2/17 1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions

3 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 3/17 1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions

4 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 4/17 In-pixel ADC FPA Architecture? X Direct (flash) Pulse density modulator Digital filter X Algorithmic (success. approx.) I sens + q adc Predictive (Σ ) - DAC Feedback = relaxed analog specs Pulse modulator + digital filter I sens V int + PWM time-to-first spike PDM spike counting 0 V th - q adc No external clocks 0 Switching power signal X Signal loss due to reset times b init

5 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 5/17 1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions

6 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 6/17 PDM for Fast Imaging Classic topology: b init + C int CTIA to cancel input parasitics I sens C CDS V int Correlated double sampling (CDS) for noise cancellation C par b init + V ref Vref + Vth Ideally: q adc = n adcideal n adcideal = T frame T pulseideal = T frame C intv th I sens

7 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 7/17 Real Scenario Loss due to reset time: T frame n adcreal = T pulseideal + T res n adcreal = n adcideal Non-linearity error: 1 + Tres T frame n adcideal b init V int V int T frame T pulseideal T pulsereal Vref + Vth V ref Vref + Vth n error = n adcreal n adcideal V ref Maximum at full-scale: q max(n error) = q fullscale fullscale < 0.5LSB = 1 1+ Tres q 2 T fullscale frame T res < T frame for q fullscale 1 2q 2 fullscale e.g. q fullscale = 1023(10bit) T frame = 10ms T res < 5ns T res Not compatible with low-power nor low-voltage!

8 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 8/17 1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions

9 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 9/17 Reset-Insensitive Topology Charge controlled reset of the PDM integrator b init C int Continuous-time integration (like APS!) I sens V int Built-in CDS mechanism C par C reset/cds Switch charge injection similar to classic topology V ref Vref + Vth

10 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 10/17 Real Scenario During reset, charge from I sens and C reset/cds is combined and integrated in C int. b init V int T frame Vref + Vth V ref Almost ideal, even for T pulsereal T res. V int T pulseideal T pulsereal Vref + Vth Minimum T res required for redistribution V ref... but T res value not relevant (technology independence). T res True low-power and low-voltage compatible!

11 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 11/17 1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions

12 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 12/17 CMOS Proposal 3-stage compact PDM circuit I sens b init I bias V int I bias I bias Single transistor CTIA stage M1 C par C int C reset/cds Vref M1 M2 M3 Local reference M2 Built-in threshold comparator M3 (all in weak inversion): V th = nu t ln (W /L)1 (W /L) 3 Technology mismatching C int C reset/cds, M1 M2 and M1 M3 are equivalent to V th V th reduction through DPS area increase

13 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 13/17 1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions

14 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 14/17 Quasi-Static (QS) Stimulus Classic PDM Proposed PDM Digital output [LSB] µm 1-poly 6-metal CMOS technology Design parameters: C int,reset/cds =100fF, V ref =1V, (W /L) 1=20(W /L) 3 so V th =0.1V and T frame =2ms

15 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 15/17 Non Quasi-Static (NQS) Stimulus 1000 Classic PDM Proposed PDM 800 Digital output [LSB] Non systematic loss even at low amplitudes for classic PDM 0 time T frame

16 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 16/17 1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions

17 ISCAS 08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 17/17 Conclusions Novel pulse density modulator (PDM) for high-speed DPS. Reset-insensitive analog integrator proposal. Low non-linearity for low-power and low-voltage operation. Compact CMOS circuit realization. Comparative study in 0.18µm 1-poly 6-metal technology. Robust simulation results for both QS and NQS signals.