ACTion: Combining Logic Synthesis and Technology Mapping for MUX based FPGAs

Transcription

1 IEEE EUROMICRO Conference (EUROMICRO 00) Maastricht, September 2000 ACTion: Combinin Loic Synthesis and Technoloy Mappin for MUX based FPGAs Wolfan Günther Rolf Drechsler Institute of Computer Science Chair of Computer Architecture (Prof. Dr. Bernd Becker) Albert-Ludwis-University Freibur im Breisau, Germany Abstract Technoloy mappin for Multiplexor (MUX) based Field Prorammable Gate Arrays (FPGAs) has widely been considered. Here, a new alorithm is proposed that applies techniques from loic synthesis durin mappin. By this, the taret technoloy is considered in the minimization process. Binary Decision Diarams (BDDs) are used as an underlyin data structure due to the close relation between BDDs and MUX netlists. The alorithm uses local don' t cares obtained by a reedy alorithm. The mappin is sped up by computin sinatures. A trade-off quality versus runtime can be specified by the user by settin different parameters. Experimental results comparin the approach to the best known results show improvements of more than 30% for area and 40% for delay for many instances. 1 Introduction Field Prorammable Gate Arrays (FPGAs) have been widely used in implementations of Application Specific Interated Circuits (ASICs) due to several reasons, like short turnaround time and time-to-market aspects. FPGAs are mainly based on a basic cell that consists e.. of a Look- Up Table (LUT) or a Multiplexor (MUX) structure. Several successful approaches to technoloy mappin have been proposed in the last few years [15, 13, 3, 19, 25]. Technoloy mappin is usually applied after a technoloy independent loic optimization phase. Durin technoloy mappin the optimized network is transformed to a functional equivalent network respectin the underlyin circuit architecture. But since this structure is not considered durin loic synthesis the resultin mapped circuits are often far from bein optimal. Several approaches to combine loic synthesis and technoloy mappin have been already proposed usin Pass Transistor Loic (PTL) as a taret technoloy. In [5] a decomposed BDD representation and variable reorderin is used. In [6], a BDD based synthesis flow for PTL is presented. Basic operations to cells are applied. Also local don' t cares are used to minimize the BDDs of cells. In this paper we present a new approach to combine technoloy mappin and loic synthesis. As a taret architecture we use FPGAs based on Actel-1 cells [1]. The alorithm starts with a pre-optimized netlist, obtained by a standard tool, like SIS [23]. However, instead of only mappin the circuit to the taret technoloy, also further lobal optimizations with respect to technoloy are performed. After each modification, the mapper is run aain and the mapped netlists are compared (instead of usin e.. the literal count as an estimation for the resultin circuit size). It has been observed in [7, 11] that this combination tends to be time consumin. However, in most cases only small parts of the netlist are affected by one modification and therefore the mapper only needs to be re-run on the modified parts of the netlist, allowin a fast evaluation. Furthermore, we use an efficient representation of the subcircuits, i.e. we use Binary Decision Diarams (BDDs) [4]: BDDs for cells of the netlist are mered and the resultin BDDs are mapped. To minimize the size of the BDDs, different variable orderin techniques are applied. We also use sophisticated techniques for local don' t care assinment. The alorithm has been implemented as the proram ACTion. We ive comparisons to many other approaches, includin ite map [13, 14, 19] which is interated in SIS. We show that sinificant improvements can be obtained usin ACTion. The paper is structured as follows: The detailed problem formulation is iven in Section 2. In Section 3 the new approach to combine technoloy mappin with loic synthesis is described. Experimental results are iven in Section 4. Finally, the results are summarized.

2 MUX1 MUX2 MUX3 1 0 OR map(mux netlist) set of ates to realize := set of output ates; while (set of ates to realize is not empty) := first element of set of ates to realize; do for (all fanin ates h) mere and h, if the resultin cell is realizable with one Actel-1 cell; while (improvement); insert Actel-1 cell to mapped netlist; insert fanin ates to set of ates to realize; Fiure 2. Sketch of mappin alorithm Fiure 1. Architecture of Actel-1 2 Problem Formulation Durin technoloy mappin a iven netlist is transformed to a functional equivalent representation with respect to a taret technoloy. One of the main problems results from the fact that this taret technoloy is usually not considered durin loic synthesis. The approach in this paper focuses on one specific cell type, i.e. the Actel-1 cell. The basic cell is iven in Fiure 1. Several technoloy mappers have been proposed in the past for this architecture (see e.. [13, 18]). Note that our approach can easily be extended to other cell types. However, a MUX based structure is advantaeous because of the similarity to BDDs. For the rest of the paper we mainly focus on area minimization, i.e. we try to find a representation that minimizes the number of cells needed to represent the circuit. Even thouh delay is not the main optimization objective, it turns out that the resultin circuits often have very ood delay. Choosin an other evaluation function, also other criteria can be incorporated, like power dissipation. 3 Combinin Loic Synthesis and Technoloy Mappin In this section the overall flow of the alorithm is described. To ive a better understandin of the interaction between loic synthesis and technoloy mappin, the main ideas of the mappin alorithm are outlined in Section 3.1. Then the tool implemented as the proram ACTion is described in Section Actel-1 Mapper A relatively simple reedy stratey is used to map MUX based netlists to Actel-1 cells: Startin from the primary outputs of the circuit, a ate is chosen and assined to a new Actel-1 cell. Then the fanin ates are added to the cell one after another until no further ate fits into the cell. Now all ates in the fanin which could not be added to the cell become output cells since they have to be represented by separate cells. A sketch of the mappin alorithm is iven in Fiure 2. To decide whether a ate can be added to an Actel-1 cell, in a preprocessin step the set of functions which can be realized with one cell is computed. Permutation invariant sinatures (see e.. [17]) are used to identify most of the computed results. We used the followin sinatures for a function f: The number of minterms of f. The Boolean values f (0; : : : ; 0) and f (1; : : : ; 1). The number of symmetry roups of f and their size. For each variable x i, the followin sinatures were used: The number of minterms of f xi=1. The number of minterms of 9x i f. The size of the symmetry roup of x i. If the sinatures do not allow to uniquely determine the variable correspondences, a complete enumeration of all variable correspondences has to be carried out. For Actel-1 cells, at most 8! = cases have to be considered. In the experiments, it turned out that only very few different correspondences had to be tested to decide whether a function is in the table of computed results. 3.2 Overall Alorithm Before the preprocessin and main optimization phase of the overall alorithm are discussed, the data structure used is briefly described Representation of the Netlist To represent a netlist, a data structure is used that can represent cells with arbitrary functionality. The function of

3 x 1 x 1 x 2 x 1... x n x 2 x 2 x 3 x x x 3 EXOR ates for transformation Transformed function f τ( ) x 1... x n (a) (b) (c) Fiure 3. Linear transformations for BDD minimization each cell is described by a BDD. Additionally, each cell is marked by a label which denotes either a basic function ( MUX, OR ) or a complex function (in this case, the label is simply BDD ). By this it is possible to decompose the function into blocks which can be represented by Actel-1 cells. Also merin of cells is possible. Note that this representation combines both structural and functional properties Preprocessin Library-invariant optimization tools are used to find a ood startin point. For this, three different startin points are created and then the best one is selected: 1. The first startin point is obtained usin SIS script rued. For the cells of the resultin netlist, local BDDs are constructed. These BDDs are then mapped to a MUX network by substitutin each BDD node by a MUX cell. 2. The MUX network is used to construct a lobal BDD (if possible within iven memory bounds; otherwise the MUX network is the only startin point). To minimize the BDD size, different variable reorderin techniques are applied: for small functions (14 variables or less), an exact alorithm is used [8]. For larer functions, the followin reorderin techniques are applied (in that order): converin roup siftin [21], converin siftin [22], a simple enetic alorithm [24], and finally converin roup siftin aain. Then the BDD is mapped to a MUX network. 3. If the lobal BDD could be constructed in the previous step, a window optimization alorithm usin linear transformations [16, 10] is applied. Linear transformations replace input variables of the BDD by the EXOR of several variables, i.e. instead of assinin variables to each node of the BDD, the parity of a set of variables is assined to each node. Fiure 3 (b) shows an example of a linearly transformed BDD for the function iven by its BDD in Fiure 3 (a). To heuristically find a ood linear transformation, the window optimization alorithm computes the optimal linear transformation for small windows of size 3. This results in a circuit like the one shown in Fiure 3 (c). The circuit is mapped to MUX cells by replacin each EXOR ate by two MUX cells. The startin point used for the followin steps is the one that results in the least number of Actel-1 cells (usin the mapper of Section 3.1). Compared to the followin step, the preprocessin consumes only a small fraction of the runtime Local Optimization Startin from a netlist obtained in the preprocessin step, local synthesis operations are applied. These modifications may result in cells consistin of BDDs with many nodes. The operations we used are the followin: 1. Chane polarity of one cell [20]. 2. Mere one cell with all its fanin cells. In a first step, each cell is mered with its fanin cells one after another. To avoid local minima, in a second step also larer reions of fanin cells are mered, unless the BDDs for the cells become too lare. 3. Mere one cell with all its fanout cells. 4. Mere two cells with similar inputs. As the resultin cell has two outputs, the shared BDD representation for the cell is mapped to MUX cells. By this, many small cells are created, which enables further merin steps. After each modification the resultin number of Actel-1 cells is computed usin the mapper of the previous section. (If the netlist contains BDD cells consistin of more than one MUX, these BDDs are replaced by a MUX netlist before mappin.) If the resultin number of Actel-1 cells is larer than the size before, then the last modification is undone and the previous netlist is restored. Therefore, the optimization is no loner technoloy independent. The opti-

4 ACTion (netlist) f /* preprocessin */ use SIS script rued to et a first startin point net; build BDD for netlist; if (successful) f net2 := BDD mapped to MUX netlist; replace net by net2 if better (in terms of Actel-1 cells); build linearly transformed BDD; net3 := transformed BDD mapped to MUX netlist; replace net by net3 if it is better (in terms of Actel-1 cells); /* local optimization phase */ repeat 3 times f repeat f foreach operation o of (chane polarity, mere one fanin, mere set of fanins, mere fanout, mere similar) f for (all ates of net) f net' := perform local synthesis operation of type o; if (net' is better in terms of Actel-1 cells) f net := net'; until (no improvement or time exceeded) net := net mapped to a MUX netlist; Fiure 4. Sketch of alorithm mization steps are iterated until no further improvement can be obtained (or a user defined time limit is reached). Then, the netlist is mapped to a multiplexor netlist, leadin to tiny cells consistin of only one MUX ate. This is also done in each mappin step, but in this case the small cells are part of the new netlist, whereas the netlist remains unchaned for the mappin step. If the size of the intermediate BDDs rows too much, the merin process can be stopped, as it is very unlikely (yet desirable) that the size can be reduced by further merin steps. The local optimization cycle is carried out three times. A sketch of the overall alorithm is iven in Fiure 4. All in all, the flow of the alorithm is very simple and the ood quality (see below) mainly results from the technoloy dependent optimizations durin local optimization and the ood BDD minimization techniques, which will be described in more detail in the followin. 3.3 Merin Cells Fiure 5. Merin two cells Merin two cells is the main operation of local optimization. Basically, this is done by buildin the BDD for the mered cell, i.e. a variable is substituted by another BDD (see Fiure 5). As the size of the resultin BDD directly influences the mappin result, a minimal representation is very desirable. Therefore, we apply different methods for variable reorderin. If the number of variables is small enouh, an exact

5 4 Experimental Results fanin cone OBDD cell fanout cone Fiure 6. Reion surroundin a cell to compute local don't cares alorithm [8] is used. Otherwise, converin siftin [21] is called. By this procedure, in most cases a ood variable orderin is found. To further minimize the BDD sizes, we make use of local don' t cares. The don' t care set could be determined by constructin the characteristic function of the whole netlist. However, its BDD size is often too lare to fit into the main memory. Therefore, the don' t care set is computed only for a local reion surroundin the cell (see Fiure 6). The reion is chosen in a way that the BDD sizes remain acceptable: It consists of a fanin cone of the cell of maximum depth 4 and a fanout cone of the cell of maximum depth 4 (unless the ate is primary output). The BDD is constructed for the reion unless its size exceeds a iven limit, i.e. four times the size of the netlist. (These numbers can be chaned by the user accordin to the trade-off quality versus runtime.) More formally, iven the characteristic functions for the fanin cone, fanout cone and the whole reion, a characteristic function cell for the cell is constructed. This function contains the care information of the cell. Next, the characteristic function has to be converted into a don' t care function. But as the cell is sinle-output, this can be done usin universal quantification over the output variable: Let x 2 B n denote some assinment to the primary inputs. Then dc(x) = 1, cell (x; 0) = 1 ^ cell (x; 1) = 1, 8o 2 B : cell (x; o) = 1; i.e. dc = 8o: cell. With the don' t care information iven as a Boolean function, standard minimization alorithms known from formal verification can be applied. We used a safe minimization alorithm [12] which uarantees that the size of the BDD does not increase by the minimization process. Note that it does not prevent the final result from becomin worse, due to the mappin step. However, in most cases some improvements can be obtained. Usin these sophisticated minimization techniques, the BDD sizes can often be reduced sinificantly. In this section we describe our experimental results. All experiments are carried out on a SUN Ultra 1 workstation. The CUDD packae [24] is used as underlyin BDD packae. A memory limit of 100 MB and a runtime limit of 15,000 CPU seconds is set in all experiments. The hih runtime limit is used because the quality of the results was our main interest. In a first series of experiments the ACTion alorithm is compared to several previously presented approaches. Results are iven in Table 1. The name of the benchmark is iven in the first column. The followin columns report the number of Actel-1 cells needed for each circuit for the approaches misii [23], Amap [13], Prosperine [9], mis-pa (old, without last asp, with last asp) [18], respectively 1. In the last column we ive the results of the alorithm AC- Tion. The best result in each row is iven in bold. As can be seen ACTion clearly outperforms all other approaches. Compared to the other mappers improvements of more than 50% can be observed (see alu2). The averae improvement to mis-pa with last asp is 20%. In a second series of experiments we compare ACTion to the ite map alorithm interated in SIS (see Table 2). For ite map, we first run script rued and then apply ite map (with two iterations). Both area and delay (usin the unit delay model) values are iven. The startin point of ACTion is iven in column start (see Section 3.2.2): SIS means that the initial netlist was obtained by SIS, while for BDD it was obtained by buildin the lobal BDD. LT refers to linearly transformed BDDs. The runtime of ACTion in CPU seconds is iven in the last column. Aain, the best results are iven in bold. An improvement in size can be observed for most examples. It is important to notice that in both cases where ite map outperforms ACTion the results differ by less than 10%. But in some cases the improvement of ACTion over ite map is much larer (see e.. t481), i.e. more than a factor of 30. This clearly demonstrates the robustness of our alorithm resultin from the different startin points. Furthermore, usin ACTion also the delay of the circuits is on averae 26% smaller than usin ite map. In most cases where the area is smaller, the delay is also much smaller (see e. alu4 or f51m). For larer instances, the alorithm tends to need much runtime. Therefore, we use an upper limit of 15,000 CPU seconds for the runtime. If the limit is exceeded, the best result found so far is reported. By this approach the user can trade off the runtime to spend and the quality of the result. Fiure 7 shows an analysis of this trade-off for c3540. Startin with 534 cells, the area is much larer than the result of ite map (462 cells). After less than 500 seconds, AC- Tion has also reached that value, but then further reduces 1 The numbers are taken from [18].

6 Table 1. Comparison to previously presented alorithms circuit misii Amap Proserpine mis-pa ACTion old new-nlg new-lg 5xp sym n/a alu n/a apex b n/a bw clip e n/a f51m misex rd sao n/a v z4ml n/a total sub-total the function to 414 cells. Also other parameters of the alorithm can be modified in order to trade off area versus runtime. Such parameters are e.. the limitation of maximal intermediate BDD sizes or the size of the reion the local don' t care set is computed from. In a third series of experiments, we compare our results to the results of the Actel Desiner usin ACTmap VHDL Synthesis [2]. Results are iven in Table 3. It can be seen that ACTion always produces results which have smaller or equal size. In some cases, the reduction is even more than a factor of two (see e.. cordic or term1). Finally, we compare the best ever values that we found in literature to the results obtained by ACTion usin a fixed parameter set and a runtime limit of 15,000 CPU seconds and to the best ever values we obtained for ACTion by varyin the parameters. The numbers are iven in Table 4. As can be seen, in many cases even ACTion with fixed parameters can further improve the best known values. For some benchmarks, like alu2 or rd84, even lare reductions can be observed. Usin different parameter settins, these results can be further improved in many cases. However, these improvements are rather small and therefore underline the robustness of our approach. 5 Conclusions We presented a new approach to combine technoloy mappin and loic synthesis. The networks are optimized such that they fit well on multiplexor based FPGAs. To minimize the underlyin BDD data structure, we use variable reorderin techniques and local don' t care minimiza- Actel-1 cells Time [s] Fiure 7. Trade-off time versus quality for c3540 tion. The user can specify parameters like a runtime limit or the maximal size of intermediate BDDs in order to trade off quality of the results versus runtime. The alorithm has been implemented as the proram ACTion. A comparison to previously published approaches clearly demonstrates the efficiency of the approach. References [1] Actel. ACT TM 1 series FPGAs. Also available at s01d07.pdf, 1997.

7 Table 2. Comparison to ite map circuit in out ite map ACTion ain area delay start area delay CPU time area delay 5xp LT % % 9sym LT % % alu BDD % % alu LT % % apex SIS % 38.5 % apex BDD % % apex SIS % % b SIS % % bw SIS % % c SIS % 0.0 % c SIS % 0.0 % c SIS % 36.4 % c SIS % -4.0 % c SIS % % c SIS % % c SIS % % c SIS % 4.5 % clip LT % % cordic BDD % % dalu LT % % des LT % % duke BDD % % e SIS % 23.1 % ex LT % 0.0 % f51m LT % % k SIS % 37.5 % misex SIS % % rd LT % % rot SIS % 0.0 % sao LT % % spla SIS % 33.3 % t LT % % v SIS % % z4ml BDD % % total [2] Actel. Actel DeskTOP CD. See com/products/systems/desktop.html, [3] S.D. Brown, R.J. Francis, J. Rose, and Z.G. Vranesic. Field-Prorammable Gate Arrays. Kluwer Academic Publisher, [4] R.E. Bryant. Graph - based alorithms for Boolean function manipulation. IEEE Trans. on Comp., 35(8): , [5] P. Buch, A. Narayan, A.R. Newton, and A.L. Saniovanni-Vincentelli. Loic synthesis for lare pass transistor circuits. In Int' l Conf. on CAD, paes , [6] R. Chaudhry, T.-H. Liu, A. Aziz, and J.L. Burns. Areaoriented synthesis for pass-transistor loic. In Int' l Conf. on Comp. Desin, paes , [7] G. De Micheli. Synthesis and Optimization of Diital Circuits. McGraw-Hill, Inc., [8] R. Drechsler, N. Drechsler, and W. Günther. Fast exact minimization of BDDs. IEEE Trans. on CAD, 19(3): , [9] S. Ercolani and G.D. Micheli. Technoloy mappin for electrically prorammable ate arrays. In Desin Automation Conf., paes , 1991.

8 Table 3. Comparison to Actel Desiner circuit in out Desiner ACTion ain alu % apex % c % cc % cm150a % cm151a % cm162a % cm85a % cordic % cu % f51m % i % rot % term % too lare % x % x % z4ml % Table 4. ACTion vs. best ever results circuit literature ACTion ACTion best ever fixed param best ever 5xp sym alu apex b bw c clip cordic e f51m misex rd sao t v z4ml total [10] W. Günther and R. Drechsler. BDD minimization by linear transformations. In Advanced Computer Systems, paes , [11] G. Hachtel and F. Somenzi. Loic Synthesis and Verification Alorithms. Kluwer Academic Publisher, [12] Y. Hon, P.A. Beerel, J.R. Burch, and K.L. McMillan. Safe BDD minimization usin don' t cares. In Desin Automation Conf., paes , [13] K. Karplus. Amap: a technoloy mapper for selectorbased field-prorammable ate arrays. In Desin Automation Conf., paes , [14] K. Karplus. ITEM: an if-then-else minimizer for loic synthesis. Technical report, University of California, Santa Cruz, [15] K. Keutzer. Daon: Technoloy bindin and local optimization by da matchin. In Desin Automation Conf., paes , [16] C. Meinel, F. Somenzi, and T. Theobald. Linear siftin of decision diarams. In Desin Automation Conf., paes , [17] J. Mohnke, P. Molitor, and S. Malik. Limits of usin sinatures for permutation independent Boolean comparison. In ASP Desin Automation Conf., paes , [18] R. Murai, R.K. Brayton, and A.L. Saniovanni- Vincentelli. An improved synthesis alorithm for multiplexor-based PGA' s. In Desin Automation Conf., paes , [19] R. Murai, R.K. Brayton, and A.L. Saniovanni- Vincentelli. Loic Synthesis for Field-Prorammable Gate Arrays. Kluwer Academic Publisher, [20] R. Murai, Y. Nishizaki, N. Shenoy, R.K. Brayton, and A. Saniovanni-Vincentelli. Loic synthesis for prorammable ate arrays. In Desin Automation Conf., paes , [21] S. Panda and F. Somenzi. Who are the variables in your neihborhood. In Int'l Conf. on CAD, paes 74 77, [22] R. Rudell. Dynamic variable orderin for ordered binary decision diarams. In Int'l Conf. on CAD, paes 42 47, [23] E. Sentovich, K. Sinh, L. Lavano, Ch. Moon, R. Murai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton, and A. Saniovanni-Vincentelli. SIS: A system for sequential circuit synthesis. Technical report, University of Berkeley, [24] F. Somenzi. CUDD: CU Decision Diaram Packae Release University of Colorado at Boulder, [25] C. Yan, M. Ciesielski, and V. Sinhal. BDS: a BDDbased loic optimization system. In Desin Automation Conf., 2000.