Low cost concurrent error masking using approximate logic circuits

Transcription

1 1 Low cost concurrent error maskin usin approximate loic circuits Mihir R. Choudhury, Member, IEEE and Kartik Mohanram, Member, IEEE Abstract With technoloy scalin, loical errors arisin due to sinle-event upsets and timin errors arisin due to dynamic variability effects are increasin in loic circuits. Existin techniques for online resilience to loical and timin errors are limited to detection of errors, and often result in sinificant performance penalty and hih area/power overhead. This paper proposes approximate loic circuits as a loic desin approach for low cost concurrent error maskin. An approximate loic circuit can predict the value of the outputs of a iven loic circuit for a specified portion of the input space, and indicate uncertainty about the outputs over the rest of the input space. Usin portions of the input space that are most vulnerable to errors as the specified input space, we show that approximate loic circuits can be used to provide low overhead concurrent error maskin support for a iven loic circuit. We describe efficient alorithms for synthesizin approximate circuits for concurrent error maskin of loical and timin errors. Results indicate that concurrent error maskin based on approximate loic circuits can mask 88% of tareted loical errors for 34% (17%) area (power) overhead, 0% timin errors on all timin paths within % of the critical path delay for 23% (8%) area (power) overhead, and 0% timin errors on all timin paths within 20% of the critical path delay for 42% (26%) area (power) overhead. Index Terms Reliability, loic synthesis, concurrent error detection, concurrent error maskin. I. INTRODUCTION Variability in CMOS desins both static and dynamic has been steadily increasin with technoloy scalin. Static variability in a chip is independent of the application or workload, and thus does not chane durin normal operation in the lifetime of a chip. Process variations are a dominant source of static variability. With increasin process variations, post-manufacturin techniques like burn-in, which have been traditionally used to screen defective chips, are becomin less effective due to increased chance of thermal runaway [1]. Hence, latent defects that escape manufacturin test are increasin and may cause intermittent failures resultin in errors durin normal operation. Further, the early onset of dynamic ain and wearout related effects like neative-bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB) in sub-45nm technoloies also increases intermittent ate failures durin the lifetime of a chip, thus resultin in shrinkin of the reliability bath-tub curve [2], [3]. The first author is with the IBM T. J. Watson Research Center, Yorktown Heihts, NY, USA ( choudhury@us.ibm.com). The second author is with the Department of Electrical and Computer Enineerin at the University of Pittsburh, Pittsburh, PA, USA ( kmram@pitt.edu and kartik.mohanram@mail.com). This research was supported by rants CCF and CCF from the National Science Foundation. On the other hand, timin errors arisin due to dynamic variability effects, e.., supply voltae variations, temperature variations, and ain related effects, are projected to be a dominant source of timin errors in loic circuits. Althouh timin errors can also result from static variability effects, these can be mitiated usin techniques like speed-binnin, clock skew adjustment [4], soft-ede flip-flops [5], and latches [6]. However, timin errors resultin from dynamic variability effects such as temperature/voltae variations and ain-related slow down of speed-paths are typically addressed by addin worstcase timin marin durin desin. To summarize, increasin loical and timin error rates are a new challene in sub-45nm technoloy scalin, and there is sinificant interest in developin new desin techniques to cope with this challene [7]. To address these challenes, this paper proposes approximate loic circuits as a universal framework for low cost concurrent error maskin to taret errors arisin from a broad class of failure mechanisms. An of a iven loic circuit can predict the output(s) of the iven circuit for a specified portion of the input space and indicates uncertainty about the value of the output(s) for the rest of the input space. Thus, the structural description of an approximate loic circuit may be different from the iven circuit, but the functional description of these circuits are closely related. Approximate loic circuits can be classified into two cateories unidirectional and bidirectional based on the input space they predict. Unidirectional approximate circuits predict portions of either the on-set or the off-set, but not both. On the other hand, bidirectional s predict portions of both the on-set and the off-set. Given a loic circuit, loical and timin errors in this circuit can be masked by synthesizin an approximate loic circuit that predicts the outputs on portions of the input space that are most vulnerable to loical or timin errors. To the best of our knowlede, concurrent error maskin usin approximate circuits is the first approach that can leverae bias in the vulnerability of a circuit to errors on different inputs to achieve cost-effective reliability improvement. Concurrent error maskin based on approximate loic circuits, proposed in this work, offers several advantaes over existin error resilience approaches. Overhead versus error coverae tradeoffs: Unlike traditional fault-tolerant approaches such as triple modular redundancy and nand multiplexin, concurrent error maskin usin approximate loic circuits provides a costeffective solution for explorin fine-rained trade-offs between error coverae and area/power in improvin circuit reliability. Further, usin prior knowlede of the input

2 2 vector distribution, either acquired online or usin cycle accurate simulations, an can be tailored to provide better and tareted error maskin coverae for the same overhead. No rollback or instruction replay: Unlike error detection and correction approaches [], [12], [16] [21], [26] [30], approximate circuits can mask errors dynamically durin normal operation, and hence, no rollback or instruction replay is necessary to correct errors. Further, since no extra latches or flip-flops are added to the desin, it does not suffer from data-path metastability and increased clock enery issues that have to be addressed in resamplin-based timin error detection techniques [22], [23]. Non-intrusive: Unlike partial error maskin [13], loic rewirin [14], and resynthesis [15] techniques, concurrent error maskin usin approximate circuits is non-intrusive, i.e., it does not require any modification in the synthesis of the oriinal loic circuit. In addition to allowin approximate circuits to be synthesized independently, non-intrusiveness also has an advantae from a testability perspective. Techniques such as [14], [15] that use loical maskin to improve reliability of loic circuits can potentially hurt the testability by introducin hard-todetect faults. In contrast, non-intrusiveness allows atin of the approximate circuit durin test, thus preservin the testability of the iven loic circuit. Customizable: Unlike prior approaches, approximate circuits provide a common framework that can be customized to provide concurrent error maskin for a broad rane of failure mechanisms. For example, offline architectural techniques such as periodic testin [8] [], [31], lifetime-reliability trackin based on technoloy parameters [32], and error prediction techniques [20], [21], [24], [25] taret only timin errors resultin from radual slowdown of speed-paths, e.., due to ain mechanisms. On-chip temperature and voltae sensors to predict temperature sures and voltae droops [33] taret timin errors due to fast-chanin dynamic variability effects like supply voltae and temperature variations. However, timin error maskin based on approximate circuits can be used to mask timin errors arisin due to radual slowdown of speed-paths as well as due to fast-chanin dynamic variability effects. The number of approximate circuits for a iven loic circuit increases exponentially as the specified input space to predict reduces in size. Amon these approximate circuits, those with a small delay, power, and area footprint in comparison to the iven loic circuit are useful for providin low cost error resilience. In this paper, we describe efficient alorithms for synthesis of low overhead approximate loic circuits that can taret a specified input space for prediction. The synthesis alorithms is comprised of two core steps: (i) clusterin ates in the iven loic circuit into Boolean function of 15 inputs, commonly referred to as technoloy-independent nodes and (ii) simplification of the technoloy-independent nodes to reduce the delay, power, and area footprint based on the input space to approximate. Results indicate that when all inputs to a circuit are equally likely, concurrent error maskin based on approximate loic circuits can mask 88% of tareted loical errors for 34% (17%) area (power) overhead, 0% timin errors on timin paths within % of the critical path delay for 23% (8%) area (power) overhead, and 0% timin errors on timin paths within 20% of the critical path delay for 42% (26%) area (power) overhead. To the best of our knowlede, such a comprehensive study of approximate circuits and their applications has not been presented in the literature. This paper is oranized as follows. Section II presents a unified formal theory of unidirectional and bidirectional s, proposed separately in the conference papers [34] and [35], respectively. Section III describes synthesis alorithms for approximate loic circuits. Section IV describes concurrent error maskin of loical errors and timin errors based on approximate loic circuits. Section V presents results for concurrent error maskin of loical errors and timin errors. Section VI is the conclusion. II. CIRCUIT APPROXIMATION One of the first applications of simple approximate loic circuits can be traced back to pre-computation architecture [36], [37] which was proposed to reduce dynamic power dissipation in sequential circuits. The pre-computation architecture reduces dynamic power dissipation by reducin switchin activity of the inputs to a combinational loic block. This is done by disablin the inputs to the combinational block for a clock cycle if the outputs of the combinational block were computed correctly usin predictor circuits in the previous clock cycle. The techniques proposed in literature use simple implication-based s for predictin the outputs of a combinational block. Extensions of the pre-computation architecture to further reduce power dissipation [38] have also been proposed. Implication-based circuit s have also been used to reduce power dissipation in power-intensive loic blocks such as clock atin and branch-prediction loic. Application of circuit to performance optimization based on speculative computation [39] has also been proposed in literature. Performance optimization is achieved by reducin the delay of the circuit implementation by relaxin the Boolean specification of outputs to allow the simplified circuit to occasionally compute an incorrect value. When an incorrect value is computed, the error is corrected throuh roll-back or local instruction relay. Speculative techniques proposed in literature leverae desiner knowlede for simplifyin a loic circuit, and hence have only been applied to reular circuit structures such as adders [40], [41], rename and issue loic [40]. However, to the best of our knowlede, they have not been applied to multi-level random loic circuits. Performance optimization in sequential circuits based on common case computation usin frequently occurrin traces [42] and thread-level parallelism usin software-based pre-computation slices [43] have also been proposed. To summarize, circuit techniques have been explored in literature for improvin performance and reducin

3 3 power dissipation of loic circuits. However, the s used in these applications are either limited to simple implication-based s or can only be applied to reular loic structures such as adders. Further, the synthesis alorithms for s proposed in literature can only taret maximization of the coverae for the entire input space, i.e., they cannot be used to taret a specific portion of the input space. In this section, we propose a eneral definition of of a Boolean function and we show that simple implication-based s proposed in literature are special cases of this definition of. Further, usin this definition of, specific portions of the input space can be tareted for prediction, and hence, conventional s that taret the entire input space are shown to be special instances of the eneralizations described in the remainder of this section. A. Approximate loic functions A Boolean function with n inputs is a function of the form f : B n B, where B = {0, 1}. A Boolean specification with n inputs is a function : B n {0, 1, }, where stands for a don t care, i.e., the value of is not specified for input combinations mapped to. A specification is said to be complete if no input combination of is mapped to, and incomplete otherwise. Thus, a Boolean function is a completely specified Boolean specification. A Boolean specification can also be described as a partition of the input space B n = {0, 1} n into three sets: (i) the on-set: set of inputs in B n where is a 1, (ii) the off-set: set of inputs in B n where is a 0, and (iii) the don t care set: set of inputs in B n where is a. These three sets can be identified by three characteristic Boolean functions: (i) on-set characteristic function, on, is 1 for inputs in the on-set of and 0 otherwise, (ii) off-set characteristic function, off, is 1 for inputs in the offset of and 0 otherwise, and (iii) don t care set characteristic function, dc, is 1 for inputs in the don t care set of and 0 otherwise. Since the on-set, off-set, and don t care set are exhaustive and mutually exclusive sets in B n, the pair-wise products of on, off, and dc are 0, and on + off + dc is 1. An of a iven Boolean specification,, predicts the correct value of for a specified portion of the input space and indicates uncertainty about the value of for the rest of the input space. Note that indicatin uncertainty about the value of the specification is essential to ensure that the specification is not altered when an is used for concurrent error maskin. Thus, iven a characteristic Boolean function S : B n B that specifies the portion of the input space to predict for, we define an, ĝ, as a set of two Boolean functions ĝ ={, e}, where and e depend on the same inputs as. The Boolean functions and e are referred to as the predictor and indicator functions, respectively. The predictor function,, predicts the value of and the indicator function, e, indicates uncertainty about the value of. In our notation for indicatin uncertainty about the value of, when e is 1, is equal to and when e is 0, may or may not be equal to. Note that the inputs in the don t care set of an incomplete specification are don t cares for both and e. In Boolean alebra, the relation between the predictor and indicator functions of an can be expressed as: ( ĝ = {, e} s.t. ( off + on ) e ) = 1 (1) The on-set of the indicator function e, i.e., when e is 1, is the input sub-space on which the, ĝ, correctly predicts the iven specification. This input sub-space is denoted as Σ. Note that the specified input sub-space (S) is typically different from the input sub-space (Σ) for which the predicts the iven specification correctly. This is because when an for a specified input sub-space S is implemented as a loic circuit, by allowin Σ to be different from S, the hardware overhead (area, delay, and power) for the approximate loic circuit can be reduced. The quality of the ( percentae) is evaluated as the fraction of the specified input sub-space S that is correctly predicted by the approximate loic circuit and can be computed as S Σ / S. We classify s into two cateories unidirectional and bidirectional. Approximations are cateorized as unidirectional and bidirectional s because for concurrent error maskin, the two approaches offer a trade-off between maximum achievable error coverae and the types of errors that can be masked. The maximum achievable error coverae with a unidirectional is lower than a bidirectional since either 0 1 or 1 0 errors can be masked. However, a unidirectional can mask errors at the outputs arisin due to a sinle fault or defect in either the oriinal or the approximate circuit. In contrast, a bidirectional cannot mask errors arisin due to a fault or defect in the approximate circuit. Section IV describes concurrent error maskin based on approximate loic in further detail. In this section, we will formalize the definitions of unidirectional and bidirectional s. B. Unidirectional An is called unidirectional if the input subspace that is predicted correctly (Σ) is either a sub-set of the on-set or a sub-set of the off-set of. By definition, a unidirectional is an implication function. An implication function,, of satisfies. When is 1, is equal to, i.e., predicts the correct value of. When is 0, may or may not predict the correct value of, i.e., = 0 indicates uncertainty about the value of. Thus, the unidirectional ĝ = {, } satisfies the condition for an approximate loic function (Eqn. 1). The Boolean function is also called an under- or on-set unidirectional of. Similarly, an over or off-set unidirectional of satisfies. An off-set unidirectional for a Boolean function is illustrated usin Karnauh maps (Kmaps) in Fiure 1. The shaded cells of the K-map of indicate the specified input sub-space, S, of and the shaded cells of the K-map of indicate the input sub-space, Σ, that is

4 4 predicted correctly by. Since 6 out of the 7 minterms in S are predicted correctly by, the percentae is 85.7%. The number of unidirectional approximate loic functions rows exponentially as the size of the specified input subspace, S, decreases. If N is the on-set of and S N, then for an on-set unidirectional with an percentae of 0%, is 1 for all inputs in S. For the inputs outside of S, but in N, is a don t care, i.e., may or may not predict inputs in N \S correctly. Each don t care can be assined either a 0 or a 1 to et a different. Thus, there are 2 N S ways of assinin the don t cares, and hence there are 2 N S on-set unidirectional s of. Note that the size of N and S are already exponential in the number of inputs of. Fi. 1. ab S Unidirectional ˆ = {, } ab Implication-based unidirectional C. Bidirectional An is called bidirectional when the input sub-space that is predicted correctly, Σ, contains portions of both the on-set and the off-set of. Unlike a unidirectional, there are many possible ways of derivin a bidirectional of. We will describe two ways of derivin a bidirectional : (i) implicationbased bidirectional that uses two unidirectional s and (ii) predictor-indicator bidirectional that is the most eneral form of bidirectional. Implication-based bidirectional : A bidirectional of can be obtained usin an on-set unidirectional 1 and an off-set unidirectional 0 as follows. Since 1, 1 = 1 predicts the correct value for a portion of the on-set of. Similarly, since 0, 0 = 0 predicts the correct value for a portion of the off-set of. Note that 1 and 0 have the same value when 1 = 1 and when 0 = 0, i.e., both 1 and 0 predict the correct value of when 1 = 0. Hence, either 0 or 1 can be used as the predictor function and 0 1 is the indicator function e. Fiure 2 illustrates an implication-based bidirectional. Note that if either 1 is a constant 0 function or if 0 is a constant 1 function, the implicationbased bidirectional reduces to an implicationbased unidirectional. Predictor-indicator bidirectional : A predictor-indicator is defined directly by a predictor function and an indicator function e. In a predictor-indicator, the predictor function Fi. 2. ab S ab Implication-based bidirectional ab ˆ = { 1, } Implication-based bidirectional. and the indicator function e may not have implication relations with the iven specification. Instead, we will show that and e have inter-dependent don t cares for minterms in S, i.e., outside the specified input space S. To achieve a ab S ˆ = {, e} Inter-dependent don t care minterm ab X 1 0 X X 1 X 0 1 X 1 1 Predictor-indicator bidirectional ab 0 1 X X 1 X 1 1 Fi. 3. Implicit inter-dependent don t cares in a predictor-indicator bidirectional. 0% percentae usin a predictor-indicator, the predictor function must be equal to and the indicator function e must be 1 for the entire specified input space S. For the remainin portion of the input space S, the only condition that decides the values of and e is that the indicator function e must not incorrectly indicate that the predicts the correct value of. Thus, in S, if predicts correctly, e can be either a 0 or a 1, i.e., e is a don t care. On the other hand, if e is a 0, then can either be a 0 or a 1, i.e., is a don t care. Thus, in S, the predictor and indicator functions have implicit inter-dependent don t cares. The don t cares are implicit because these don t cares are not present in the iven specification, but arise implicitly from the definition of predictor-indicator bidirectional. The don t cares are inter-dependent because the don t cares in depend on the value of e and vice-versa. There are many combinations of implicit inter-dependent don t cares in and e. Fiure 3 shows one combination of implicit inter-dependent don t care in and e. Each of these don t cares in f and e can be assined to either a 0 or a 1 to obtain a predictor-indicator as shown in Fiure 4. Usin various combinations of implicit inter-dependent don t cares and the assinment of these don t cares to a 0 or a 1, every bidirectional can be expressed as a predictor-indicator and thus, a predictor-indicator is the most eneral form of 1 0 e

5 5 bidirectional. Fi. 4. ab S ˆ = {, e} ab Predictor-indicator bidirectional ab Predictor-indicator bidirectional. The number of predictor-indicator bidirectional s, ĝ = {, e}, of rows exponentially as the size of the input space to be predicted correctly by the decreases. In a predictor-indicator bidirectional, the value of the predictor function is fixed for the inputs in S, i.e., (S) = (S) and the indicator function, e, is 1 to indicate that predicts correctly. For inputs outside of S (in B n \S), and e have implicit inter-dependent don t cares as described in Section II-A, i.e., the indicator function is a don t care if predicts correctly, and 0 otherwise. Thus, if predicts correctly for s inputs in S, then there are s don t cares in the indicator function. There are 2 s ways of assinin these s don t cares. Hence, the total number of bidirectional approximate functions for is iven by s= S ( S ) s=0 s 2 s = 3 S. To summarize, the space of bidirectional s is rich and explorin this space durin synthesis of bidirectional s is challenin. In the next section, we will describe efficient alorithms for synthesizin approximate loic circuits. III. SYNTHESIS OF APPROXIMATE LOGIC CIRCUITS In the discussion so far, we have defined approximate loic functions and described two kinds of approximate loic functions: unidirectional and bidirectional. We have also shown that for a iven loic circuit and a specified portion of the input space to predict, there are an exponentially lare number of approximate loic functions. For loic desin applications, approximate loic functions are useful only when they can be synthesized into a loic circuit, referred to as approximate loic circuits, with a small delay, power, and area footprint. Existin loic synthesis techniques are not incremental, i.e., if the Boolean function to be synthesized is slihtly modified, the entire synthesis has to be repeated. Hence, synthesis of approximate loic circuits usin existin loic synthesis techniques must be a bottom-up approach that converts the iven Boolean function into an approximate loic function and then, synthesizes the approximate loic function into an approximate loic circuit. For simple implicationbased s, two level minimization tools such as ESPRESSO [44] followed by multi-level loic optimization or symbolic manipulation techniques such as binary decision diarams (BDDs) followed by BDD-based decomposition [45] e can be used to convert a iven loic function into an approximate loic function, followed by synthesis of the approximate loic function into an approximate loic circuit. However, these techniques cannot handle inter-dependent don t care spaces which arise in a predictor-indicator. Further, two-level minimization tools such as ESPRESSO [44] are not scalable to circuits with more than inputs and state-of-the-art BDD-based decomposition techniques cannot ensure a low overhead approximate loic circuit even if the BDD for the approximate function is smaller than the BDD for the iven loic function. To address these issues, this section describes synthesis of approximate loic circuits usin a clustered technoloyindependent network. A clustered technoloy-independent network is an intermediate representation of a circuit in which the internal nodes are Boolean functions with 15 inputs. Each node in the clustered technoloy-independent network is associated with two kinds of Boolean functions: (i) a local Boolean function with variables as the inputs to the clustered node and (ii) a lobal Boolean function with variables as the primary inputs to the circuit. We represent the local Boolean function of a node as a sum-of-product (SOP) expression. The SOP for the off-set is referred to as the 0-SOP and the SOP for the on-set is referred to as the 1-SOP. A 0-SOP can be converted to a 1-SOP and vice-versa usin DeMoran s law. Given loic circuit C with n inputs and m outputs and a specified input space S i for output i, a clustered technoloyindependent network, T, of C can be obtained by clusterin ates in C [44]. We have used the clusterin alorithms implemented in the renode command in ABC [46] the open source loic synthesis tool. The clusterin alorithm in ABC uses either SOPs or BDDs to store the Boolean function of the internal nodes. The clusterin decisions are made based on two input parameters: (i) maximum number of inputs and (ii) maximum size of the Boolean function of the clustered node. The size of the Boolean function is measured as the number of cubes in the SOP if the Boolean function is stored as an SOP and as the number of nodes in the BDD if the Boolean function is stored as a BDD. We have observed that usin a clusterin alorithm based on storin the Boolean functions as an SOP with 15 inputs and a maximum size of 0 cubes in the SOP yields approximate loic circuits with small area-power-delay footprint. A possible explanation for this behavior could be that SOPs provide a better correlation to the delay and area of a circuit than BDDs. The iven loic circuit, C, is then reduced to an approximate loic circuit with a small delay-power-area footprint by simplifyin the Boolean functions of the nodes in the clustered technoloy-independent network T. The simplification of the Boolean function is performed by selectin a sub-set of cubes from its 0-SOP, 1-SOP, or both based on the cube weihts. The cube weiht indicates the importance of each cube in predictin the output i correctly for inputs in the specified input space S i. A weiht is assined to each cube in the 0- SOP and 1-SOP of each node n j in the clustered technoloyindependent network usin S i of outputs i that contain node n j in their fanin cone.

6 6 Cube weiht computation: The cube weiht is computed as the projection of these S i s into the local Boolean input space of a clustered technoloy-independent node. In other words, the weiht of a cube represents the fraction of minterms in S i that will be predicted incorrectly if this cube is discarded durin simplification of the clustered technoloy-independent node. Note that two cubes in a SOP may represent the same minterms from S i. Thus, to avoid the same minterm from bein included in the weiht of more than one cube, the cubes are arraned in the increasin order of the size of their support sets, and the weiht of each cube is computed as the fraction of minterms in S i that are not included in the previous cubes. Such a cube orderin helps to reduce the area-powerdelay footprint of the approximate circuit because cubes with smaller support sizes tend to have hiher weihts, and hence are preferred over cubes with larer support sizes durin cube selection. The cube weihts are used to uide the to predict the output i of the circuit correctly for inputs in S i. In this section, we will show that to ensure correctness of unidirectional s, additional constraints have to be imposed durin simplification of clustered nodes. Further, to ensure correctness of bidirectional s, extra loic has to be added to the clustered technoloy-independent network. A. Unidirectional The alorithm for synthesis of unidirectional approximate loic functions is divided into 2 staes: (i) Type assinment: Assinin a type of (0/1/EX/DC) to each node in T and (ii) Cube selection: Reducin the nodes in T by selectin cubes from the 0-SOP, 1-SOP, or both. 1) Type assinment: The aim of type assinment is to determine the type of at each node in T based on the type of that is desired at the primary outputs of the circuit. Local observability values are used for type assinment. For each node n j in the multi-level network, the local observability of the fanin nodes of n j are computed with respect to the output of n j. The local 0(1)-observability of a fanin node is defined as the probability that a 0 (1) value at the fanin is observable at the output of n j. The reason behind assinin a type based on local observability values is that if the fanin 0(1)-observability of a fanin is dominant, then a 0(1)- of the fanin would ensure a better of node n j. Each node in T can be assined one of 4 types: 0, 1, EX, or DC. First, for a primary output i, the node drivin output i is assined the same type as primary output i. Then, the other nodes of T are assined a type in reverse topoloical order, i.e., a node is assined a type after all its fanout nodes have been assined a type. The fanin of each node is assined a type based on the local 0-observability and 1-observability of the fanin nodes. If both local 0-observability and 1-observability of a fanin node are small in comparison to the observabilities of other fanin nodes, a type DC is assined to the fanin node. If the local 0(1)-observability is reater than the local 1(0)- observability, then a type 0(1) is assined to the fanin node. If the local 0-observability and 1-observability are equal, then a type EX is assined to the fanin node. Note that a node with more than one fanout may be assined a different type by each fanout node. In that case, the type is assined to the node based on the preference order of type EX > type 0/1 > type DC. Further, if a node is assined a type 0 by one fanout and a type 1 by another fanout, then the node is assined a type EX. 2) Cube selection: The oal of cube selection is two fold: (i) to ensure correctness of at the primary outputs and (ii) to achieve a hih percentae for low overhead. Two alorithms with linear time complexity for cube selection exact cube selection and observability don tcare-based (ODC-based) cube selection are described. Exact cube selection approach uarantees correctness of the at the primary outputs, but may limit the percentae because strict constraints for selectin cubes are imposed to uarantee correctness. Observability don t care based cube selection relaxes the constraints for cube selection usin local ODCs. However, this may result in an incorrect at the primary outputs. Finally, we describe an iterative cube selection alorithm that uses exact cube selection and ODC-based cube selection to iteratively convere to a correct. Exact cube selection: This technique derives an approximate loic function by pickin a sub-set of cubes from the SOP expression of type 0 and type 1 nodes while type EX and type DC nodes are not reduced. First, the SOP expression used for cube selection must match the node type, i.e., if the node type is 0, then the cubes from the 0-SOP are selected. Cubes that conform to the fanin node types may be selected from the SOP expression. A cube is said to conform to a fanin node of type 0(1) if the literal in the cube correspondin to the fanin node is a 0 ( 1 ) or (don t care). A cube conforms to a fanin node of type DC if the correspondin literal in the cube is. Every cube conforms to a fanin node of type EX. A cube is selected only if it conforms to the type assinment of every fanin node. The followin theorem proves that selection of cubes based on this criteria always enerates a correct at the primary outputs. Theorem: Given Boolean functions X 1, X 2, = X 1 X 2, and on-set unidirectional approximate Boolean functions X 1 and X 2 for X 1 and X 2, then = X 1X 2 is a on-set unidirectional for. Proof: Since X 1 and X 2 are on-set unidirectional s for X 1 and X 2, X 1 X 1 and X 2 X 2. Thus, X 1 + X 1 = 1 and X 2 + X 2 = 1 (X 1 + X 1)(X 2 + X 2) = 1 X 1 X 2 + X 1 X 2 + X 2 X 1 + X 1 X 2 = 1 X 1 (X 2 + X 2) + X 2 (X 1 + X 1) + X 1 X 2 = 1 X 1 + X 2 + X 1X 2 = 1 X 1 X 2 + X 1X 2 = 1 X 1X 2 X 1 X 2

7 7 In other words, is an on-set unidirectional of. Similarly, we can prove that if = X 1 +X 2 then = X 1+ X 2 is an on-set unidirectional of. Note that both the above results also hold true for off-set unidirectional s, i.e., if X 1 and X 2 are off-set unidirectional s of X 1 and X 2 then (i) = X 1 X 2 is an off-set unidirectional of = X 1 X 2, and (ii) = X 1 + X 2 is an off-set unidirectional of = X 1 +X 2. The above theorems can be eneralized to n variables usin induction on n. Observability don t-care-based (ODC-based) cube selection: The constraint for selectin cubes in exact cube selection was based on conformity of the cubes to the fanin node types. Althouh this constraint uarantees correctness, it limits the quality of the that can be achieved. The constraint for cube selection can be relaxed by usin local ODCs to expand the space from which cubes can be selected. Local ODCs refer to the ODC space with respect to the output of the node, and not with respect to the primary output of the circuit. Equation 2 shows the computation of the Boolean space based on local ODCs from which cubes are selected. For simplicity, the Boolean space for a node n j with two fanin nodes f 1 of type 1 and f 2 type 0 is shown. (f 1 + o(f 1 ))(f 2 + o(f 2 )) if is of type 1 (f 1 + o(f 1 ))(f 2 + o(f 2 )) if is of type 0 Here, is the local Boolean function of the node n j and o(f 1 ) and o(f 2 ) represent the local observability of fanin nodes f 1 and f 2. The Boolean space (f 1 + o(f 1 )) represents the space that either conforms to the type 1 fanin node f 1 or a space in which f 1 is not observable. For a node of type DC, only the ODC term is used. Approximatin the nodes in T causes incorrect values of nodes for portions of the input space. As lon as only a sinle input of a node is incorrect, this ODC-based cube selection ensures correctness. However, when multiple inputs of a node are incorrect, the of the node may be incorrect because the ODC space for multiple inputs is computed as the Boolean AND of the ODC space for each input in Eqn. 2. Iterative cube selection alorithm: The exact cube selection alorithm uarantees correctness of the by imposin strict constraints for cube selection, thus affectin the quality of the. On the other hand, the ODCbased cube selection relaxes the constraints on cube selection but does not uarantee correctness of the. We now describe an iterative approach that combines these two techniques to achieve ood quality s while maintainin correctness. The SOP of every node is reduced by discardin cubes with least weihts. The 0(1)-SOP is used for type 0(1) nodes. For type EX and type DC nodes, either the 0-SOP or the 1-SOP can be used. The of the primary outputs of the circuit are then checked for correctness by verifyin, usin BDDs or SAT alorithms, that Equation 1 is satisfied. If all the outputs have been correctly approximated, the alorithm terminates. Otherwise, the outputs that have been incorrectly approximated are corrected as follows. First, a backward (2) T reduced to a unidirectional T - clustered technoloy-independent network i - Input space to approximate for output i Compute SOP cubes weihts of nodes in T usin i Assin a type 0/1/EX/DC to each node of T Reduce Boolean functions of nodes in T by discardin small weiht cubes Yes All outputs correctly approximated? No Back trace nodes from incorrect output to find source node for incorrect Try to correct node usin observability don t care based cube selection Correct node usin exact cube selection No Is node correct? Fi. 5. Alorithm for synthesis of a unidirectional [34]. traversal of the circuit is performed to identify a source node of incorrect. A node is a source of incorrect if the Boolean function of the node has been incorrectly approximated, but if all its fanin nodes have been correctly approximated. The of this node is corrected by usin ODC-based cube selection. If this fails to correct the at the node, the exact cube selection approach is used, which uarantees a correct. This procedure is repeated until the at the output is fixed. The iterative cube selection alorithm flow is shown in Fi. 5. Note that usin this iterative cube selection alorithm, it is possible for some internal nodes to be approximated incorrectly, but the primary outputs are always approximated correctly. Thus, the alorithm is implicitly able to explore the lobal ODC space of the internal nodes. The computational complexity of the iterative alorithm depends on the amount of backtrackin that needs to be performed in order to ensure correctness of. For most benchmark circuits considered, we found that no backtrackin was necessary to fix the at the outputs. B. Bidirectional A simple extension of the synthesis alorithm for unidirectional approximate loic circuits is to synthesize a bidirectional approximate loic circuit usin two unidirectional approximate loic circuits one for the off-set and the other for the on-set. Loic sharin between the two unidirectional approximate loic circuits can be used to reduce the overhead of the bidirectional approximate loic circuit. However, we found that this approach for synthesizin bidirectional approximate loic circuits results in hih overhead since it fails to explore the rich interdependent don t care space in bidirectional s as described in Sec. II-C. This section describes the synthesis alorithm for a predictorindicator bidirectional approximate loic circuit by simplifyin the clustered technoloy-independent network T. In addition to simplifyin the Boolean functions of the internal nodes in the clustered technoloy-independent network, the alorithm Yes

8 8 also adds extra loic ates to ensure a correct predictorindicator bidirectional. Let n j denote an internal node in the technoloy independent network T. First, the cube weihts for the 0-SOP and 1-SOP of n j are computed usin the sum of the speed-path characteristic functions (SPCFs) of all outputs in the fanout cone of n j. The Boolean expression of n j is then simplified by eliminatin zero weiht cubes from the 0-SOP and 1-SOP of n j to obtain the reduced on-set (n 0 j ) and the reduced off-set (n 1 j ). Usin n0 j and n1 j, the predictor output ñ j and indicator output e nj for node n j are obtained as follows. 1) The reduced Boolean expressions n 0 j or n1 j can be used as the predictor function for n j. The indicator function can be obtained by combinin n 0 j and n1 j usin an OR ate. Thus, ñ j = n 0 j or ñ j = n 1 j e nj = n 1 j + n 0 j (3) 2) The predictor and indicator functions for node n j can also be obtained by explorin the interdependent don t care space as follows. First, the predictor function is set to either n 0 j or n1 j and the indicator function is set to n1 j + n 0 j. Next, the predictor function, ñ j, can be optimized usin the Boolean space e j = 0 as the don t care space. Further, the indicator function e j can be optimized by usin the Boolean space ñ j = n j as the don t care space. This procedure is repeated to enerate unique pairs of predictor and indicator functions. Amon the various predictor-indicator functions, the pair with the least number of literals in the SOP expressions of the predictor and indicator is chosen. The output e nj is 1 when an input from the SPCF of any output in the fanout cone of n j is applied and output ñ j predicts the correct value of n j when e nj is 1. The indicator output e i for primary output i is 1 when all internal nodes in the fanin cone of primary output i predict their outputs correctly. Thus, e i can be enerated as a Boolean AND of the indicator outputs, e nj, of all internal nodes n j in the fanin cone of output i. The simplified technoloy-independent network T is then synthesized, optimized, and mapped to obtain a bidirectional for the output i. The pseudo code for synthesis of a bidirectional approximate circuit is presented in Alorithm 1. The synthesis techniques described in this section can be used to synthesize approximate loic circuits for predictin different portions of the input space. In Sec. IV, we describe two applications of approximate loic circuits to reliability enhancement based on concurrent error maskin. IV. APPROXIMATION-BASED CONCURRENT ERROR MASKING Error resilient systems rely on redundant computation to correct errors. Just as residue computation provides a low overhead customizable solution for improvin error resilience of arithmetic loic such as adders, concurrent error maskin usin approximate circuits can be applied to enhance error resilience of random combinational loic, only with better Alorithm 1: Bidirectional(T, Σ i ) input output : Clustered technoloy-independent network T and specified input space Σ i of output i : Reduced technoloy-independent network of the bidirectional Compute cube weihts for the 0-SOP and 1-SOP of all nodes in T foreach node n j in T do Remove zero weiht cubes from 0-SOP of n j to obtain n 0 j Remove zero weiht cubes from 1-SOP of n j to obtain n 1 j L = {} /* list of unique {n j, e nj } */ Assin ñ j = n 0 j and en j = n1 j + n0 j repeat Minimize SOP of ñ j usin e nj = as the don t care space if {ñ j, e nj } is unique then Add {ñ j, e nj } to L Minimize SOP of e nj usin ñ j = n j as the don t care space if {ñ j, e nj } is unique then Add {ñ j, e nj } to L until unique {ñ j, e nj } Assin ñ j = n 1 j and en j = n1 j + n0 j repeat Minimize SOP of ñ j usin e nj = as the don t care space if {ñ j, e nj } is unique then Add {ñ j, e nj } to L Minimize SOP of e nj usin ñ j = n j as the don t care space if {ñ j, e nj } is unique then Add {ñ j, e nj } to L until unique {ñ j, e nj } Pick {ñ j, e nj } from L with the minimum total literals in the two SOPs Output of T, reduced from the clustered technoloy-independent network T, is the predictor of the bidirectional AND of all e nj s in T is the indicator of the bidirectional customizability and overhead than traditional solutions such as parity prediction. This section describes the application of approximate loic circuits for concurrent maskin of errors arisin due to different failure mechanisms. A failure is defined as a physical anomaly in the desin. Failures can cause intermittent, transient, or permanent faulty behavior in a desin. A fault model is a behavioral abstraction of physical failure(s), i.e., it tries to capture the effect of failure(s) on the behavior of a desin and is useful for derivin test patterns or desinin robust systems. Traditionally, a atelevel stuck-at fault model has been widely used for derivin test patterns for post-manufacture testin. Technoloy scalin has introduced new failure mechanisms and increased power dissipation that has caused post-manufacture testin and burnin techniques to be inadequate. This paper considers transient failures arisin, for instance, due to sinle-event upsets, resultin in an incorrect value at the output of the circuit. Since these errors are not timin-related and cannot be avoided by reducin the clock frequency, they are referred to as loical errors. This paper also considers delay variations due to temperature and supply voltae variations and lon-term ain effects like NBTI and TDDB. An incorrect value latched at the output of a circuit due to delay variations is referred to as a timin error. Error maskin in a iven loic circuit is performed by synthesizin approximate loic circuits that predict the outputs of the iven circuit for portions of the input space that are most vulnerable to errors. Thus, application of approximate loic circuits to concurrent error maskin requires two steps:

9 9 Fi. 6. Inputs. x 1 x 2 y 1 x n. Oriinal loic circuit f(x 1, x 2,, x n ) Unidirectional approximate circuit y m y 2 y m y 1 y 2.. Outputs 0-approx 1-approx Concurrent error maskin based on approximate loic circuits. (i) identification of the input space that is most vulnerable to errors and (ii) synthesis of the approximate loic circuit that can predict the correct output for this input space. Based on this, the application of approximate loic circuits to maskin of errors arisin due to various static and dynamic variability effects are described in this section. A. Loical errors Loical errors at the output of a circuit, arisin due to latent defects or sinle-event upsets at internal ates, can be masked by combinin the output with its off-set (or on-set) unidirectional. For instance, 0 1 errors at an output y i in the oriinal circuit can be masked by combinin y i and an off-set unidirectional, ỹ i, of y i with an AND ate. Since ỹ i y i, when ỹ i is 0, y i is also 0, and an error at y i or ỹ i is masked by the AND ate. Note that errors are masked even when they occur at the outputs of the unidirectional approximate circuit. Similarly, 1 0 errors can be masked by combinin an output with its on-set unidirectional usin an OR ate. Concurrent error maskin of loical errors usin unidirectional approximate loic circuits is illustrated in Fi. 6. For each output in the oriinal loic circuit, the 1 0 and 0 1 error rates are computed usin either Monte Carlo simulations or reliability analysis tools, e.., [47], [48]. Then, for each output, a unidirectional approximate circuit is synthesized usin the alorithm described in Sec. III to mask the hiher of the two error rates, i.e., an off-set unidirectional is synthesized for an output if the 0 1 error rate is hiher for that output. The specified input space S i for the synthesis alorithm are the minterms in the on-set (off-set) for an on-set (off-set) unidirectional and the alorithm tries to reduce overhead of the approximate circuit while maximizin correct prediction of the output for inputs in S i. Errors are masked by combinin each output of the iven loic circuit with its off-set (on-set) unidirectional with an AND (OR) ate. Error maskin based on approximate circuit does not incur a performance penalty since the approximate circuit has a smaller delay. Further, approximate loic circuits allow flexible trade-offs between error maskin coverae and the power/area overhead incurred by the approximate loic circuit. Fi. 7. Inputs x 1 x n Oriinal loic circuity k-1 f(x 1,x 2,, x n ) y k 0 (Delay ) 1 Bidirectional approximate circuit (Delay < 0.8 ) x 1 x n Non-critical outputs k e k m e m y 1 y m Outputs Timin error maskin based on bidirectional approximate circuits. Note that a bidirectional, ŷ i = {ỹ i, e i }, of an output y i cannot be used to mask loical errors. This is because a 2-to-1 multiplexer is used to implement error maskin for a bidirectional, with y i, ỹ i, and e i as the 0-data, 1-data, and select inputs to the 2-to-1 multiplexer, respectively. When the indicator output, e i, is 0, ỹ i may not predict y i correctly, and hence errors at y i are not masked. When e i is 1, ỹ i predicts y i correctly, and thus, an error at ỹ i is masked by usin ỹ i instead of y i. However, if an error occurs at ỹ i when e i is 1, the 2-to-1 multiplexer output would be incorrect. Hence, a bidirectional cannot be used when the bidirectional approximate circuit is vulnerable to errors. B. Timin errors Approximate loic circuits can be used to mask timin errors resultin from both fast-chanin dynamic variability effects and radual slowdown of speed-paths. The first step in deployin approximate loic circuits for timin error maskin is to identify the input space of a loic circuit that is vulnerable to timin errors usin technoloy-dependent ate and interconnect delay models. This input space is the specified input space, S (also referred to as the speed-path characteristic function (SPCF)), for the. Hence, the computation of the SPCF is done after technoloy-mappin, and if possible after place-and-route of the desin. In this work, the computation of the SPCF tarets all timin paths in the desin within % and 20% of the critical path delay. Note that approximate loic circuits can mask timin errors arisin simultaneously from multiple critical paths. For an output y i and a iven taret delay, the SPCF for y i, S i, contains inputs that sensitize speed-paths in the fanin cone of output y i. Several alorithms have been proposed for the exact computation of the SPCF [49], [50]. These alorithms compute the exact set of minterms that sensitize paths with a delay reater than or equal to a desired value. These alorithms are path-based and require traversal of each critical path. Other alorithms that compute an of the SPCF have also been proposed [51], [52]. These alorithms compute an over- of the SPCF, i.e., minterms that do not sensitize critical paths may be included in the SPCF. The over alorithms are computationally more efficient than path-based alorithms because they are node-based and require computation only at nodes that lie on the critical path.