SH7147 APPLICATION NOTE. Resolver Built-in DC Brushless Motor Control. 1. Abstract. 2. Introduction. 2.1 Specification

Transcription

1 APPLICATION NOTE SH747. Abstract This application note is organized based on sample of resolver built-in DC brushless motor control, which uses SH747 embedded ADC_0, MTU2S_3,4, and CMT_0,, and is aimed to provide information users may need during software and hardware design. Although the operation of each program in this application note has been checked, make sure that you conduct your own operation checks before actually using. 2. Introduction 2. Specification () System Architecture Specification Figure describes system architecture of this control. SH747 is used as motor control MCU. M5934 is used as step-up predriver for inverter driver Six H7N0602LS (power MOS FET) is used as 3-phase inverter (2) Motor Control Specification Resolver built-in DC brushless motor is controlled in 20-degree energization drive system. Resolver output signal is converted to digital at ADC_0 and motor position is detected at every 30 degree. Motor drive wave most suitable to motor position will be outputted from MTU2S (level output on positive phase side, PWM output on antiphase side) Motor revolving direction reverses at every 4[sec]. REJ05B /Rev Page of 55

2 Motor control MCU SH747 MTU2S_3,4 TIOC3BS (U-phase) TIOC3DS (*U-phase) TIOC4AS (V-phase) TIOC4CS (*V-phase) TIOC4BS (W-phase) TIOC4DS (*W-phase) CMT_0, Predriver M5934 UT (U-phase) VT (V-phase) WT (W-phase) UB (*U-phase) VB (*V-phase) 3-Phase inverter H7N0602LS DC brushless motor WB (*W-phase) ADC_0 AN0 (resolver excitation) AN (resolver sin wave) AN2 (resolver cos wave) Resolver excitation signal generation circuit Resolver * Note: *U-phase, *V-phase, and *W-phase describes antiphase of each phase Figure Overview of System REJ05B /Rev Page 2 of 55

3 2.2 Functions Used Multi-function Timer pulse Unit 2S channel 3,4 (MTU2S_3,4) A/D converter 0 (ADC_0) Compare Match Timer channel 0, (CMT_0,) SH Applicable Conditions MCU : SH747(R5F7474AK64FPV) Operation Frequency : Internal Clock 64MHz : Bus Clock 32MHz : Peripheral Clock 32MHz : MTU2S Clock 64MHz : MTU2 Clock 32MHz C Compiler : Renesas Technology product SuperH RISC engine Family C/C++ compiler package Ver.9.00 Compile Option : Default setting by HEW 2.4 Related Application Note Power MOS FET Application Note REJ05B /Rev Page 3 of 55

4 3. Description of Control Sample This control sample determines motor position by A/D converting output signal of resolver, which is built in DC brushless motor. A motor drive wave, most suitable to the determined mortar position, will be output from MTU2S and controls DC brushless motor. 3. Overview of Entire Operation Following describes functions used by SH747 for controlling resolver built-in DC brushless motor (Figure 2.) SH747 Function Assignment CMT_0 Compare match interrupt function CMT_ Compare match interrupt function Motor position information ADC_0 A/D conversion end interrupt AN0 AN AN2 Resolver excitation wave Resolver output Sin wave Resolver output Cos wave Assigns motor revolving direction changing timing MTU2S_3,4 Assigns motor drive waveform switch timing CPU Assigns motor drive output wave TIOC3BS (U-phase) TIOC3DS (*U-phase) TIOC4AS (V-phase) TIOC4CS (*V-phase) TIOC4BS (W-phase) TIOC4DS (*W-phase) Complementary PWM output function Output motor drive wave (Connect to predriver M5934) Note: *U-phase, *V-phase, and *W-phase describes antiphase of each phase. Figure 2 SH747 Control Block Diagram Following describes each function. A/D Conversion End Interrupt: After conversing resolver input excitation signal, resolver output Sin wave signal, and resolver output Cos wave signal into digital, it requests CPU for interrupt. A/D conversion result is stored to RAM by interrupt procedure. Compare Match Interrupt Function (CMT_0): Request CPU for interrupt at every 50μ[sec]. Interrupt procedure determines motor position and outputs motor drive wave. Compare Match Interrupt Function (CMT_): Request CPU for interrupts at every 0.8[sec] Interrupt procedure counts number of interrupting times and reverses motor revolving direction at every 5 interrupts process. (reverse motor revolving direction at every 0.8[sec] x 5 = 4[sec]) Complementary PWM Output Function: Level output on positive phase side and chopping wave output on antiphase side. REJ05B /Rev Page 4 of 55

5 3.2 Description of Functions Used SH747 [] A/D Converter (a) Overview of A/D converter (ADC) operation Resolver input excitation signal, resolver output Sin wave signal, and resolver output Cos wave signal are input from analog input pin 0,,2 (AN0, AN, and AN2) respectively. Input voltage of AN0 to 2 are sampled at a same timing at sample & hold circuit (the step before analog multiplexer) and A/D converted sequentially. The operation mode is continuous scan mode. Figure 3 describes ADC_0 block diagram. AVcc AVss AVrefh AVrefl 2bit D/A approximation register Successive ADDR0 ADDR ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 Synchronous sampling AN0 (Resolver excitation signal) AN (Resolver output Sin wave) AN2 (Resolver output Cos wave) AN3 AN4 AN5 Sample & hold circuit Sample & hold circuit Sample & hold circuit Impedance conversion circuit Impedance conversion circuit Impedance conversion circuit Analog multiplexer Sample & hold circuit Converter + - Control circuit ADCR_0 ADANSR_0 ADSR_0 ADSTRGR_0 Data bus within Module Bus I/F AN6 AN7 Impedance conversion circuit Impedance conversion circuit ADDR0 to 7 : A/D Data Register 0 to 7 ADCR_0 : A/D Control Register_0 ADANSR_0 : A/D Analog Input Channel Select Register_0 ADSR_0 : A/D Status Register_0 ADSTRGR : A/D Start Trigger Select Register Offset cancel circuit A/D conversion end interrupt signal ADI_3 Trigger signal from MTU2 TRGAN TRGON TRG4AN TRG4BN Trigger signal from MTU2S TRGAN TRG4AN TRG4BN External trigger signal ADTRG Internal data bus Figure 3 ADC_0 Block Diagram REJ05B /Rev Page 5 of 55

6 (b) Overview of Resolver Following describes resolver in motor position detection sensor, implemented in this system (Figure 4.) A coil is fixed on the rotor, and two coils are fixed 90 degree of each other on the stator. When resolver input excitation signal (Vr) is inputted, resolver output Sin wave (V sin ) and resolver output Cos wave (V cos ), which has 90 degree phase difference, are outputted from two coils on the stator. Rotor Stator Input Signal Resolver excitation signal Vr = Vs Sin(ωt) Output Signal Resolver output Cos wave Vcos = Vs Sin(ωt) Vr Cosθ Stator Output Signal Resolver output Sin wave Vsin = Vs Sin(ωt) Vr Sinθ Vs = Input Voltage ω = Angular Speed of Excitation θ = Motor Rotation Angle Figure 4 Diagram of Resolver Principle REJ05B /Rev Page 6 of 55

7 (c) Resolver Input/Output Signal and Motor Rotation Position Figure 5 describes resolver input excitation signal, resolver output Sin wave, and resolver output Cos wave per revolution of the motor. One motor revolution is equivalent to one cycle of Sin waveform and Cos waveform obtained from resolver output Sin wave and resolver output Cos wave. Resolver Input Excitation Signal Resolver Output Sin Wave Sin Sin waveform Resolver Output Cos Wave Motor Rotation Position Cos Cos waveform Figure 5 Resolver Input/Output Signal and Sin wave/ Cos wave (per motor revolution) (d) Obtaining Sin waveform/ Cos waveform from each Resolver Output wave Resolver output Sin wave/ Cos wave can be described in following formula, as been shown in Figure 4 Diagram of Resolver Principle. Resolver Output Sin Wave Signal: V sin = VsSin(ωt)VrSinθ Resolver Output Cos Wave Signal: V cos = VsSin(ωt)VrCosθ If resolver input excitation signal (VsSin(ωt)) is regarded as constant, Resolver Output Sin Wave Signal: V sin = ASinθ Resolver Output Cos Wave Signal: V cos = ACosθ A : VsVrSin(ωt) REJ05B /Rev Page 7 of 55

8 Sin/Cos waveform can be obtained from above. Following describes how to obtain Sinθ and Cosθ from resolver output Sin wave signal and resolver output Cos wave signal with regarding resolver input excitation signal as constant. (i) In this control sample, voltage of resolver input excitation signal (VsSin(ωt)) is kept constant to have above A to be constant. A can be regarded as amplitude of resolver output signal. For this amplitude to have the maximum value, the voltage of resolver input signal for achieving the maximum amplitude of resolver output signal shall be obtained in beforehand by examining resolver input/output signal waveform and shall be defined as the reference value. (ii) Voltage of resolver input excitation signal, resolver output Sin wave signal, and resolver output Cos wave signal are sampled at a same time and are A/D converted in continuous conversion mode. (iii)when A/D conversion result of resolver input excitation signal and the reference voltage defined at (i) matches, in other words, when amplitude of resolver output signal becomes maximum, A/D conversion result of two output signals, ASinθ and ACosθ, are stored to RAM. To look f or the v oltage to achiev e maximum amplitude of the output signal, A/D conv ersion result of resolv er input excitation signal and ref erence v oltage shall are A/D compared at all time. Resolver Input Excitation Signal (Vr) (Vr) Resolver Output Sin Sin Wave (V (V sin ) sin ) Sin A/D conversion value of resolver output Sin wav e is stored into A/D RAM RAM. Resolver Output Cos Wave (V Cos (V cos ) cos ) A/D conversion value of resolver Cos output Cos wav e is stored into A/D RAM RAM. Figure 6 RAM Storage Timing of Resolver Output Signal REJ05B /Rev Page 8 of 55

9 In this control sample, resolver input excitation signal cycle is set 900μ[sec] and motor rotation speed is set 300[rpm] (200m[sec]/revolution). There are about 222 resolver input excitation signal cycles per motor revolution. As shown in Figure 6, Sinθ and Cosθ can be achieved once in one resolver input excitation signal cycle. Therefore, Sinθ and Cosθ can be achieved 222 times per one motor revolution and motor position can be detected per approximately.6 degree (360 degree/222) (A/D conversion error not regarded). As for this control sample requires motor position information per 30 degree,.6 degree motor positioning meets the requirement. (e) Motor Position Determination Following describes how to calculate an angle from Sin waveform/ Cos waveform achieved from resolver input/output signal. As for this sample controls motor in 20-degree energization method, it captures motor position information for each 30 degree. Figure 7 describes relation between motor position and Sin waveform/ Cos waveform. Voltage.700[V] Sin waveform Cos waveform.000 [V] Motor Position [V] Area () (2) (3) (4) (5) (6) (7) (8) (9) (0) () (2) Figure 7 Motor Position and Sin Waveform/ Cos Waveform Motor position can be determined from Sin waveform/cos waveform with defining following provision. Area (): Cosθ > Cos30 & Sinθ > 0 Area (7): Cosθ > Cos50 & Sinθ < 0 Area (2): Sin60 > Sinθ > Sin30 & Cosθ > 0 Area (8): Sin20 > Sinθ > Sin240 & Cosθ < 0 Area (3): Sinθ > Sin60 & Cosθ > 0 Area (9): Sinθ > Sin240 & Cosθ < 0 Area (4): Sinθ > Sin60 & Cosθ < 0 Area (0):Sinθ > Sin240 & Cosθ > 0 Area (5): Sin60 > Sinθ > Sin30 & Cosθ < 0 Area ():Sin20 > Sinθ > Sin240 & Cosθ > 0 Area (6): Cosθ > Cos50 & Sinθ > 0 Area (2):Cosθ > Cos330 & Sinθ < 0 REJ05B /Rev Page 9 of 55

10 Following describes data comparing Sin waveform/cos waveform. SH747 Analog input voltage of this control sample is maximum of.7[v], minimum of 0.3[V], and intermediate of.0[v]. Avref is set to 5.0[V]. As for motor is positioned by 30 degrees, voltage for comparing Sin/Cos waveform and constant to be compared is defined as Table. Table Voltage of Sin/Cos waveform and Comparison Value Sin270, Cos80 Sin240, Sin300, Cos50, Cos20 Sin20, Sin330, Cos20, Cos240 Voltage [V] Compared constant H'0F5 H'42 H'23 Sin60, Sin20, Cos30, Cos330 Sin30, Sin50, Cos60, Cos300 Sin0, Cos90, Sin80, Cos270 Voltage [V] Compared constant H'332 H'45 H'522 Sin90, Cos0 Voltage [V].7 Compared constant H'570 REJ05B /Rev Page 0 of 55

11 Flowchart for actually determining motor position by this controller is described in Figure 8. Start Sin wave > Sin60 Yes Cos wave > Sin330 Yes No Cos wave > Cos90 Yes No Sin wave > Sin0 Yes No No Motor position: [Area (4)] Motor position: [Area (3)] Motor position: [Area (2)] Motor position: 0-30 [Area ()] Sin wave > Sin240 Yes Sin wave > Sin0 Yes No Cos wave > Cos270 Yes No Cos wave > Cos90 Yes No No Motor position: [Area (9)] Motor position: [Area (0)] Motor position: [Area (5)] Motor position: [Area (2)] Cos wave > Cos50 Yes Cos wave > Cos270 Yes No Sin wave > Sin80 Yes No Motor position: [Area ()] No Motor position: [Area (7)] Motor position: [Area (6)] Motor position: [Area (8)] Figure 8 Motor Position Determining Flow REJ05B /Rev Page of 55

12 (f) Principle of A/D Converting Operation Figure 9 describes principle of A/D converting operation. Table 2 shows details of software and hardware processing. ADST bit is set to by software and executes A/D conversion in continuous scan mode. Following are processed by A/D conversion end interrupt. When A/D conversion result of resolver input excitation signal meets the condition described in Figure 6, A/D conversion result of resolver output Sin/Cos wave signal will be stored to RAM. When Figure 6 condition meets (when Sinθ and Cosθ are defined) for the first time, compare match interrupt by compare match timer_0 is enabled. (Compare match timer_0 (CMT_0) interrupt processing (output motor drive wave) is executed after motor position is defined.) ADST (A/D conversion start) Conversion AN0 wait (Resolver excitation signal) Conversion AN wait (Resolver output Sin wave) S S Synchronous sampling OFC A/D H conversion () OFC H H Conversion wait A/D conversion () Conversion wait S S Synchronous sampling OFC A/D H conversion (2) OFC H H Conversion wait A/D conversion (2) Conversion wait S S Synchronous sampling OFC A/D H conversion OFC H H Conversion AN2 wait (Resolver output Cos wave) S OFC H H A/D conversion () S OFC H H A/D conversion (2) OFC S H H ADDR ADDR ADDR A/D conversion result (AN0) () A/D conversion result (AN2) () A/D conversion result (AN0) (2) A/D conversion result (AN) A/D conversion result (AN) () (2) A/D conversion result (AN2) (2) ADF (A/D conversion end) Process () Process (2) Process (3) Process (4) Process (3) Process (4) Process (3) OFC : Offset Cancel Process S : Sampling H : Holding Figure 9 A/D Conversion Operation in Continuous Scan Mode REJ05B /Rev Page 2 of 55

13 Table 2 Details of Software/Hardware process for A/D Conversion Software Process Process () After releasing AD_0 module stop, followings are set Set continuous scan mode by setting ADCS bit to Select AN0 to 2 as input channel by setting ANS0-2 to Enable A/D conversion end interrupt (ADI_3) by setting ADIE bit to SH747 None Process (2) Set A/D conversion start by setting ADST bit to Start A/D conversion Hardware Process Process (3) None Sample AN0-2 synchronously and execute A/D Process (4) Transfer A/D conversion result of AN0 (resolver input excitation signal) to RAM If A/D conversion result of AN0 meets the condition (please refer figure 6), following are executed. () Store A/D conversion result of AN (resolver output Sin wave) and AN2 (resolver output Cos wave) to RAM. (2) When condition meets for the first time, CMT_0 compare match interrupt is enabled. Clear ADF to 0. conversion Store A/D conversion result sequentially to ADDR0-2 Set ADF to. A/D conversion end interrupt been generated (ADI_3). REJ05B /Rev Page 3 of 55

14 [2] MTU2S (g) Overview of MTU2S Operation Complementary PWM wave of three positive phase and three antiphase are outputted by using channel 3 and channel 4 of MTU2S. Operation mode is complementary PWM mode. Correlation between UF bit, VF bit, and WF bit of timer gate control register S (TGCRS) and output level is shown in Table 3. (active level is set Low in this sample) UF bit, VF bit, and WF bit are switched by software depending on motor revolving direction and motor position, and then motor drive wave is outputted (Figure 0). Table 3 TGCRS (UF, VF, WF bit) and Output Level Bit 2 Bit Bit 0 Function WF VF UF TIOC3BS TIOC4AS TIOC4BS TIOC3DS TIOC4CS TIOC4D U-phase V-phase W-phase *U-phase *V-phase *W-phase OFF OFF OFF OFF OFF OFF 0 0 ON OFF OFF OFF OFF ON 0 0 OFF ON OFF ON OFF OFF 0 OFF ON OFF OFF OFF ON 0 0 OFF OFF ON OFF ON OFF 0 ON OFF OFF OFF ON OFF 0 OFF OFF ON ON OFF OFF OFF OFF OFF OFF OFF OFF REJ05B /Rev Page 4 of 55

15 TGCRS UF bit VF bit WF bit Motor Drive Output Wave TIOC3BS (U-phase) TIOC3DS (*U-phase) TIOC4AS (V-phase) TIOC4CS (*V-phase) TIOC4BS (W-phase) TIOC4DS (*W-phase) Motor Position When clockwise of rotation axis (CW) When counterclockwise of rotation axis (CCW) * Active level of both positive phase and antiphase are Low Hardware Process Output motor drive wave from TIOC3BS, TIOC3DS, TIOC4AS, TIOC4CS, TIOC4BS, and TIOC4DS Software Process Switch TGCRS (UF/VF/WF bit) depending to motor position Figure 0 Motor Drive Wave by TGCRS (UF, VF, WF bit) Switch REJ05B /Rev Page 5 of 55

16 (h) Duty Setting Figure describes MTU2S (ch3, ch4) in complementary PWM mode and duty setting is explained after it. Timer Gate Control Register S (TGCRS) U-phase, *U-phase Duty setting Timer General Register D_3 (TGRD_3S) Temporary Register S (TempS) Timer General Register B_3S (TGRB_3S) V-phase, *V-phase Duty setting Timer General Register C_4S (TGRC_4S) Temporary Register 2S (Temp2S) TIOC3BS (U-phase) W-phase, *W-phase Duty setting Timer General Register D_4S (TGRD_4S) Timer Counter_3S (TCNT_3S) Timer Counter_4S (TCNT_4S) Timer General Register A_4S (TGRA_4S) Temporary Register 3S (Temp3S) Timer General Register B_4S (TGRB_4S) Comparator Compare match signal Output Controller TIOC3DS (*U-phase) TIOC4AS (V-phase) TIOC4CS (*V-phase) TIOC4BS (W-phase) Set dead time Timer Sub-Counter S (TCNTSS) Timer Dead Time Data Register S (TDDRS) TIOC4DS (*W-phase) Set PWM cycle Timer Cycle Buffer Register S (TCBRS) Timer Cycle Data Register (TCDRS) Set TCNT_3S upper limit Timer General Register C_3S (TGRC_3S) Timer General Register A_3S (TGRA_3S) Note: *U-phase, *V-phase, and *W-phase are antiphase of each phase. Figure Block Diagram when in Complementary PWM Mode (Channel 3/4) [Notes] CPU cannot directly access Temporary Register (TempS, 2S, 3S) Write into TGRB_3S, TGRA_4S, TGRB_4S, TGRA_3S, and TCDRS are prohibited during timer operation. When write into above listed register during timer operation is necessary, please write into their buffer register TGRD_3S, TGRC_4S, TGRD_4S, TGRC_3S, and TCBRS. REJ05B /Rev Page 6 of 55

17 Following describes duty setting. This control sample outputs PWM only for antiphase. Level output is made for positive phase. Duty is determined by setting values of TGRB_3S, TGRA_4S, and TGRB_4S. Motor drive current changes by changing duty setting, and it allows changing motor torque and speed. Figure 2 describes operation principle and Table 4 shows details of software/hardware process. PWM Cycle Process (3) TGRA_3S TCNTSS TCDRS Process (2) TGRB_3S = TGRA_4S = TGRB_4S TDDRS H'0000 TCNT_3S TCNT_4S Process (4) Process (6) Process () Process (5) Antiphase Output Non-active Period PWM Cycle Active Period Antiphase: Low Level Active Duty (%) = Active Level Period PWM Cycle x 00 Figure 2 Counter Operation and Duty/PWM Cycle REJ05B /Rev Page 7 of 55

18 Table 4 Details of Software/Hardware Processing for Duty Setting SH747 Software Process Process () Configure followings after releasing AD_0 module stop and setting PFC Timer count start Output L level from pin Hardware Process TCNT_3S and TCNT_4S start up-count Process (2) None Output H level from pin by compare match between TCNT_3S and TGRB_3S, TGRA_4S, and TGRB_4S Process (3) None TCNT_3S starts down-count by compare match between TCNT_3S and TGRA_3S TCNT_4S starts down-count by compare match between TCNT_4S and TCDRS Process (4) None Output L level from pin by compare match between TCNT_3S and TGRB_3S, TGRA_4S, and TGRB_4S Process (5) None TCNT_3S starts up-count by compare match between TCNT_3S and TGRA_3S TCNT_4S starts up-count by compare match between TCNT_4S and TCDRS Process (6) None Output L level from pin by compare match between TCNT_3S and TGRB_3S, TGRA_4S, and TGRB_4S REJ05B /Rev Page 8 of 55

19 [3]CMT (i) Overview of CMT Operation Interrupt process is executed at every 50μ [sec] by using compare match timer channel 0 (CMT_0). Interrupt process switches timer gate control register S (TGCRS) of MTU2S for outputting a PWM wave, which is most suitable to motor position. Also, interrupt process is executed at every 0.8 [sec] by using compare match timer channel (CMT_). This interrupt process counts number of interrupt process and reverses motor revolving direction (clockwise counterclockwise) at every 5 interrupt process (every 4 [sec]). Figure 3 describes CMT block diagram. Compare match timer start register (CMSTR) Control Circuit Peripheral Clock (Pφ) Clock Select 8 division 32 division 28 division 52 division Compare match timer control/status register_0 (CMCSR_0) Compare match counter_0 (CMCNT_0) CMI_0 interrupt Comparator Compare match constant register_0 (CMCOR_0) Control Circuit Peripheral Clock (Pφ) Clock Select 8 division 32 division 28 division 52 division Compare match timer control/status register_ (CMCSR_) Compare match counter_ (CMCNT_) CMI_ interrupt Comparator Compare match constant register_ (CMCOR_) Figure 3 CMT Block Diagram REJ05B /Rev Page 9 of 55

20 (j) Principle of CMT Operation Figure 4 and Figure 5 describes principles of CMT_0 and CMT_ operation. STR0 bit CMCOR_0 CMCNT_0 H'0000 CMF bit (Compare match flag) Hardware Process None Software Process Sets following after releasing CMT module stop Set CKS bit to 0 and select pφ/8 for count clock Set H 00FA to CMCOR_0 register and configure compare match at every 50μ[sec] Hardware Process Count start Software Process Set STR0 bit to and start count Hardware Process Set CMF bit to Generate compare match interrupt (However, only when compare match interrupt by A/D conversion end is enabled Clear CMCNT_0 Software Process Configure timer gate control register S (TGCRS) of MTU2S depending to motor position Clear CMF_0 bit to 0 Figure 4 Principle of CMT_0 Operation (Assign TGCRS setting timing) STR0 bit CMCOR_ CMCNT_ H'0000 CMF bit (Compare match flag) Hardware Process None Software Process Sets following after releasing CMT module stop Set CKS bit to 3 and select pφ/52 for count clock Set CMIE bit to and enable compare match interrupt Set H F424 to CMCOR_ register and configure compare Match at every 0.8 [sec] Hardware Process Count start Software Process Set STR bit to and start count Hardware Process Set CMF bit to Generate compare match interrupt Clear CMCNT_ Software Process Clear CMF_ bit to 0 Hardware Process Set CMF bit to Generate compare match interrupt Clear CMCNT_ Software Process Clear CMF_ bit to 0 Reverse motor revolving direction at every 5 compare match occurrences Figure 5 Principle of CMT_ Operation (Assign motor revolving direction reversing timing) REJ05B /Rev Page 20 of 55

21 3.3 Sample program Procedure Following describes each register setting. Table 5 ADC_0 Setting Register Name Bit Name Bit Function Set Value A/D Control Register ADST 7 0: A/D conversion start 0 (ADCR_0) : A/D conversion stop ADSC 6 0: cycle scan : Continuous scan ACE 5 0: Prohibit automatic clear, after ADDR read 0 : Enable automatic clear, after ADDR read ADIE 4 0: Prohibit A/D conversion end interrupt : Enable A/D conversion end interrupt Reserve TRGE 0: Prohibit A/D conversion triggered by exterior or MTU2/2S : Enable A/D conversion triggered by exterior or MTU2/2S 0 EXTRG 0 0: Select MTU2/MTU2S as A/D conversion start trigger 0 : Select external pin (ADTRG) as A/D conversion start trigger A/D Status Register_0 Reserve 7-0 (ADSR_0) ADF 0 A status flag indicating A/D conversion end Set: A/D conversion of all the selected channels have ended. 0 Note (Settable only by hardware process) 0 Clear: After read, write 0 Activate DTC by A/D conversion end interrupt and read ADDR A/D Analog Input Channel ANS7 7 0: Unselect AN7 as input channel 0 Select Register_0 (ADANSR_0) ANS6 6 : Select AN7 as input channel 0: Unselect AN6 as input channel 0 : Select AN6 as input channel ANS5 5 0: Unselect AN5 as input channel 0 : Select AN5 as input channel ANS4 4 0: Unselect AN4 as input channel 0 : Select AN4 as input channel ANS3 3 0: Unselect AN3 as input channel 0 : Select AN3 as input channel ANS2 2 0: Unselect AN2 as input channel : Select AN2 as input channel ANS 0: Unselect AN as input channel : Select AN as input channel ANS0 0 0: Unselect AN0 as input channel : Select AN0 as input channel A/D Data Register 0 (ADDR0) Reserve 5-2 R ADD[:0] -0 A/D conversion result of analog input pin 0(AN0) (2bit) A/D Data Register (ADDR) Reserve 5-2 R ADD[:0] -0 A/D conversion result of analog input pin (AN) (2bit) REJ05B /Rev Page 2 of 55

22 Register Name Bit Name Bit Function Set Value A/D Data Register 2 (ADDR2) Reserve 5-2 R ADD[:0] -0 A/D conversion result of analog input pin 2(AN2) (2bit) A/D Data Register 3 (ADDR3) Reserve 5-2 R ADD[:0] -0 A/D conversion result of analog input pin 3(AN3) (2bit) A/D Data Register 4 (ADDR4) Reserve 5-2 R ADD[:0] -0 A/D conversion result of analog input pin 4(AN4) (2bit) A/D Data Register 5 (ADDR5) Reserve 5-2 R ADD[:0] -0 A/D conversion result of analog input pin 5(AN5) (2bit) A/D Data Register 6 (ADDR6) Reserve 5-2 R ADD[:0] -0 A/D conversion result of analog input pin 6(AN6) (2bit) A/D Data Register 7 (ADDR7) Reserve 5-2 R ADD[:0] -0 A/D conversion result of analog input pin 7(AN7) (2bit) Note: : ADF is automatically set to R: Read-only bit REJ05B /Rev Page 22 of 55

23 Table 6 MTU2S Setting Register Name Bit Name Bit Function Set Value Timer Control Register_3S CCLR[2:0] 7-5 Select counter clear factor of timer counter_3s (TCNT_3S) H'000 (TCR_3S) 000: Prohibit clear 00: Clear by compare match/input capture of TGRA_3S 00: Clear by compare match/input capture of TGRB_3S 0: Clear by counter clear of other channel, which is cleared/operated synchronically 00: Prohibit clear 0: Clear by compare match/input capture of TGRC_3S 0: Clear by compare match/input capture of TGRD_3S : Clear by counter clear of other channel, which is cleared/operated synchronically CKEG[:0] 4-3 Select input clock edge Effective only when input clock is slower than MIΦ/4 When selected input clock is faster than MIΦ/4, it is counted at only rising edge. 00: Count at rising edge 0: Count at falling edge 0: Count at both rising/falling edge : Count at both rising/falling edge H'00 TPSC[2:0] 2-0 Select counter clock of timer counter_3s (TCNT_3S) H' : MIΦ/ 00: MIΦ/4 00: MIΦ/6 0: MIΦ/64 00: MIΦ/256 0: MIΦ/024 0: External clock (TCLKA) : External clock (TCKLB) Timer Control Register_4S (TCR_4S) CCLR[2:0] 7-5 Select counter clear factor of timer counter_4s (TCNT_4S) 000: Prohibit clear H'000 00: Clear by compare match/input capture of TGRA_4S 00: Clear by compare match/input capture of TGRB_4S 0: Clear by counter clear of other channel, which is cleared/operated synchronically 00: Prohibit clear 0: Clear by compare match/input capture of TGRC_4S 0: Clear by compare match/input capture of TGRD_4S : Clear by counter clear of other channel, which is cleared/operated synchronically CKEG[:0] 4-3 Select input clock edge Effective only when input clock is slower than MIΦ/4 When selected input clock is faster than MIΦ/4, it is counted at only rising edge. 00: Count at rising edge 0: Count at falling edge 0: Count at both rising/falling edge : Count at both rising/falling edge H'00 REJ05B /Rev Page 23 of 55

24 Register Name Bit Name Bit Function Set Value Timer Control Register_4S TPSC[2:0] 2-0 Select counter clock of timer counter_4s (TCNT_4S) H'000 (TCR_4S) 000: MIΦ/ 00: MIΦ/4 00: MIΦ/6 0: MIΦ/64 00: MIΦ/256 0: MIΦ/024 0: External clock (TCLKA) : External clock (TCKLB) Timer Mode Register_3S Reserve 7 0 (TMDR_3S) Reserve 6 0 BFB 5 0: TGRB_3S and TGRD_3S are in normal operation : TGRB_3S and TGRD_3S are in buffer operation BFA 4 0: TGRA_3S and TGRC_3S are in normal operation : TGRA_3S and TGRC_3S are in buffer operation MD[3:0] 0000: Normal operation 000: Setting prohibited 000: PWM mode 00: Setting prohibited 000: Setting prohibited 00: Setting prohibited 00: Setting prohibited 0: Setting prohibited 000: Reset-synchronized PWM mode 00: Setting prohibited 00: Setting prohibited 0: Setting prohibited 00: Setting prohibited 0: Complementary PWM mode (transfer at peaks) 0: Complementary PWM mode 2 (transfer at valleys) : Complementary PWM mode 3 (transfer at peaks and valleys) H'0 REJ05B /Rev Page 24 of 55

25 Register Name Bit Name Bit Function Set Value Timer Mode Register_4S Reserve 7 0 (TMDR_4S) Reserve 6 0 BFB 5 0: TGRB_4S and TGRD_4S are in normal operation : TGRB_4S and TGRD_4S are in buffer operation BFA 4 0: TGRA_4S and TGRC_4S are in normal operation : TGRA_4S and TGRC_4S are in buffer operation MD[3:0] : Normal operation 000: Setting prohibited H'0000 Note2 000: PWM mode 00: Setting prohibited 000: Setting prohibited 00: Setting prohibited 00: Setting prohibited 0: Setting prohibited 000: Setting prohibited 00: Setting prohibited 00: Setting prohibited 0: Setting prohibited 00: Setting prohibited 0: Setting prohibited 0: Setting prohibited : Setting prohibited Timer Output Master Enable Reserve Register S (TOERS) OE4D 5 0: Prohibit MTU2S output by TIOC4DS pin (Non-active level) Note2 : Enable MTU2S output by TIOC4DS pin (*W-phase) OE4C 4 0: Prohibit MTU2S output by TIOC4CS pin (Non-active level) Note2 : Enable MTU2S output by TIOC4CS pin OE3D 3 0: Prohibit MTU2S output by TIOC3DS pin (Non-active level) Note2 : Enable MTU2S output by TIOC3DS pin OE4B 2 0: Prohibit MTU2S output by TIOC4BS pin (Non-active level) Note2 : Enable MTU2S output by TIOC4BS pin OE4A 0: Prohibit MTU2S output by TIOC4AS pin (Non-active level) Note2 : Enable MTU2S output by TIOC4AS pin OE3B 0 0: Prohibit MTU2S output by TIOC3BS pin (Non-active level) Note2 : Enable MTU2S output by TIOC3BS pin REJ05B /Rev Page 25 of 55

26 Register Name Bit Name Bit Function Set Value Timer Gate Control Register S Reserve 7 (TGCRS) BDC 6 0: Disable TGCRS register (this register) setting : Enable TGCRS register (this register) setting N 5 Select output state of antiphase output pin (TIOC3DS (*U-phase), TIOC4CS (*V-phase), TIOC4DS (*W-phase)) Note3 0: Level output : Reset-synchronized PWM/ Complementary PWM P 4 Select output state of positive phase output pin 0 (TIOC3BS (U-phase), TIOC4AS (V-phase), TIOC4BS (W-phase)) Note3 0: Level output : Reset-synchronized PWM/ Complementary PWM FB 3 0: Switch output phase by external input : Switch output phase by software (setting of UF, VF, and WF bit of TGCRS) WF 2 Set output phase by switching WF, VF, and UF bit Please refer Table 7 H'000 Note4 Timer Output Control RegisterS Reserve 7 0 (TOCRS) PSYE 6 0: Prohibit toggle output synchronized to PWM cycle 0 : Enable toggle output synchronized to PWM cycle Reserve TOCL 3 0: Enable write to TOCS, OLSN, and OLSP bit : Prohibit write to TOCS, OLSN, and OLSP bit 0 TOCS 2 Set output level in complementary PWM mode/resetsynchronized PWM mode 0: TOCR setting effective : TOCR2 setting effective OLSN Select antiphase output level in complementary/ resetsynchronized PWM mode 0: Initial output H, Active level L, Compare match while up-count H, Compare match while down-count L : Initial output L, Active level H, Compare match while up-count L, Compare match while down-count H OLSP 0 Select positive phase output level in complementary/ reset-synchronized PWM mode 0: Initial output H, Active level L, Compare match while up-count L, Compare match while down-count H : Initial output L, Active level H, Compare match while up-count H, Compare match while down-count L REJ05B /Rev Page 26 of 55

27 Register Name Bit Name Bit Function Set Value Timer Counter_3S (TCNT_3S) 5-0 Counter of channel 3 H'0000 Note5 Timer Counter _4S (TCNT_4S) 5-0 Counter of channel 4 H'0000 Note5 Timer Cycle Data Register S 5-0 A register been used only in complementary PWM H'0640 (TCDRS) mode Set PWM carrier period to /2 Timer Dead Time Data 5-0 A register been used only in complementary PWM H'000 Register S (TDDRS) mode Set dead time Timer General Register A_3S 5-0 When complementary PWM mode is set; H'064 (TGRA_3S) Set (/2 of PWM carrier period + dead time) Timer General Register B_3S 5-0 When complementary PWM mode is set; H'00A0 (TGRB_3S) Compare register of TIOC3BS(U-phase)/TIOC3DS(*Uphase) pin output Timer General Register A_4S 5-0 When complementary PWM mode is set; H'00A0 (TGRA_4S) Compare register of TIOC3AS(V-phase)/TIOC4CS(*Vphase) pin output Timer General Register B_4S 5-0 When complementary PWM mode is set; H'00A0 (TGRB_4S) Compare register of TIOC4BS(W-phase)/ TIOC4DS(*W-phase) pin output Timer Cycle Buffer Register S (TCBRS) 5-0 A register been used only in complementary PWM mode Buffer register of TCDRS H'0640 Timer General Register C_3S (TGRC_3S) Timer General Register D_3S (TGRD_3S) Timer General Register C_4S (TGRC_4S) Timer General Register D_4S (TGRD_4S) Timer Dead Time Enable Register S (TDERS) 5-0 When complementary PWM mode is set; Buffer register of TGRA_3S TGRC_3S is set when changing TGRA_3S during timer operation 5-0 When complementary PWM mode is set; Buffer register of TGRB_3S TGRD_3S is set when changing TGRB_3S during timer operation 5-0 When complementary PWM mode is set; Buffer register of TGRA_4S TGRC_4S is set when changing TGRA_4S during timer operation 5-0 When complementary PWM mode is set; Buffer register of TGRB_4S TGRD_4S is set when changing TGRB_4S during timer operation Reserve 7- TDER 0 0: Do not generate dead time : Generate dead time H'064 H'00A0 H'00A0 H'00A0 REJ05B /Rev Page 27 of 55

28 Register Name Bit Name Bit Function Set Value Timer Start Register S CST4 7 0: Count stop of timer counter_4s (TCNT_4S) 0 (TSTRS) : Count start of timer counter_4s (TCNT_4S) CST3 6 0: Count stop of timer counter_3s (TCNT_3S) 0 : Count start of timer counter _3S (TCNT_3S) Reserve Reserve 2 0 Reserve 0 Reserve 0 0 Note2 Non-active level complies TOCRS/2S setting Note3 U-phase, V-phase, and W-phase are positive phase. *U-phase, *V-phase, and *W-phase are antiphase. Note4 Initial value. This control sample switches WF, VF, and UF bit depending on motor position. Note5 Initial value. Changes during timer operation. Table 7 Output Level Select Function Bit 2 Bit Bit 0 Function WF VF UF TIOC3BS TIOC4AS TIOC4BS TIOC3DS TIOC4CS TIOC4D U-phase V-phase W-phase *U-phase *V-phase *W-phase OFF OFF OFF OFF OFF OFF 0 0 ON OFF OFF OFF OFF ON 0 0 OFF ON OFF ON OFF OFF 0 OFF ON OFF OFF OFF ON 0 0 OFF OFF ON OFF ON OFF 0 ON OFF OFF OFF ON OFF 0 OFF OFF ON ON OFF OFF OFF OFF OFF OFF OFF OFF REJ05B /Rev Page 28 of 55

29 Table 8 CMT_0, Setting Register Name Bit Name Bit Function Set Value Compare Match Timer Start Reserve Register (CMSTR) STR 0: Count stop of compare match counter_ 0 : Count start of compare match counter_ STR0 0 0: Count stop of compare match counter_0 0 : Count start of compare match counter_0 Compare Match Timer Control Reserve Register_0 (CMCSR_0) CMF 7 A flag which indicates match of compare match constant register_0 (CMCOR_0) value and compare match timer counter_0 (CMCNT_0) value. 0 *Note6 Set: CMCOR_0 and CMCNT_0 matches (automatically set by hardware) 0 Clear: Write 0 When CMT register is accessed while DTC module is activated by CMI_0 interrupt and MRB/DISEL bit of DTC is 0 CMIE 6 0: Prohibit compare match interrupt (CMI_0) : Enable compare match interrupt (CMI_0) Reserve CKS[:0] -0 Select frequency for counting CMCNT_0 00: PΦ/8 0: PΦ/32 0: PΦ/28 : PΦ/52 H'00 Compare Match Counter_0 5-0 Counter for up-count H'0000 (CMCNT_0) Compare Match Constant 5-0 Set the duration until matching with CMCNT_0 H'00C8 Register_0 (CMCOR_0) Compare Match Timer Control Reserve Register_ (CMCSR_) CMF 7 A flag which indicates match of compare match constant register_ (CMCOR_) value and compare match timer counter_ (CMCNT_) value. 0 *Note6 Set: CMCOR_ and CMCNT_ matches (automatically set by hardware) 0 Clear: Write 0 When CMT register is accessed while DTC module is activated by CMI_ interrupt and MRB/DISEL bit of DTC is 0 CMIE 6 0: Prohibit compare match interrupt (CMI_) : Enable compare match interrupt (CMI_) Reserve CKS[:0] -0 Select frequency for counting CMCNT_ 00: PΦ/8 0: PΦ/32 0: PΦ/28 : PΦ/52 H' Compare MatchCounter_ 5-0 Counter for up-count H'0000 (CMCNT_) Compare Match Constant Register_ (CMCOR_) 5-0 Set the duration until matching with CMCNT_ H'C350 Note6: CMF is automatically set to REJ05B /Rev Page 29 of 55

30 Table 9 PFC Setting Register Name Bit Name Bit Function Set Value Port E IO Register H Reserve (PEIORH) PE2 5 0: PE2 pin (2pin) is input : PE2 pin (2pin) is output PE20 4 0: PE20 pin (4pin) is input : PE20 pin (4pin) is output PE9 3 0: PE9 pin (5pin) is input : PE9 pin (5pin) is output PE8 2 0: PE8 pin (6pin) is input : PE8 pin (6pin) is output PE7 0: PE7 pin (7pin) is input : PE7 pin (7pin) is output PE6 0 0: PE6 pin (8pin) is input : PE6 pin (8pin) is output Port E Control Register H2 Reserve (PECRH2) PE2MD 5 00: PE2 input/output (port) H'0 PE2MD0 4 0: TIOC4DS input/output (MTU2S) 0: WRL output (BSC) : Setting prohibited Reserve PE20MD 00: PE20 input/output (port) H'0 PE20MD0 0 0: TIOC4CS input/output (MTU2S) 0: Setting prohibited : Setting prohibited Port E Control Register H Reserve (PECRH) PE9MD PE9MD : PE9 input/output (port) 0: TIOC4BS input/output (MTU2S) H'0 0: RD output (BSC) : Setting prohibited Reserve -0 0 PE8MD PE8MD : PE8 input/output (port) 0: TIOC4AS input/output (MTU2S) H'0 0: CS output (BSC) : Setting prohibited Reserve PE7MD 5 00: PE7 input/output (port) H'0 PE7MD0 4 0: TIOC3DS input/output (MTU2S) 0: CS0 output (BSC) : Setting prohibited Reserve 3 0 PE6MD2 PE6MD PE6MD : PE6 input/output (port) 00: TIOC3BS input/output (MTU2S) 00: WAIT output (BSC) Other than above: Setting prohibited H'0 REJ05B /Rev Page 30 of 55

31 Table 0 STBYCR Setting Register Name Bit Name Bit Function Set Value Standby Control Register MSTP23 7 0: MTU2S is operating 0 (STBCR4) : Clock supply to MTU2S is halted (MTU2S is not operating) MSTP22 6 0: MTU2 is operating : Clock supply to MTU2 is halted (MTU2 is not operating) MSTP2 5 0: CMT is operating 0 : Clock supply to CMT is halted (CMT is not operating) MSTP20 4 0: A/D_ is operating : Clock supply to A/D_ is halted (A/D_ is not operating) MSTP9 3 0: A/D_0 is operating : Clock supply to A/D_0 is halted (A/D_0 is not operating) 0 Reserve 2-0 Table INTC Setting Register Name Bit Name Bit Function Set Value Interrupt Priority Register J (IPRJ) IPR[5:2] 5-2 Set the priority order of CMT_0 interrupt factor. Priority level is set between 0 to 5 H' : Priority level 0 (lowest) : Priority level 5 (highest) IPR[:8] -8 Set the priority order of CMT_ interrupt factor. H'00 Priority level is set between 0 to : Priority level 0 (lowest) : Priority level 5 (highest) Interrupt Priority Register K (IPRK) IPR[7:4] 7-4 Set the priority order of AD_0 interrupt factor. Priority level is set between 0 to : Priority level 0 (lowest) : Priority level 5 (highest) H'000 Table 2 CPG Setting Register Name Bit Name Bit Function Set Value Frequency Control Register Reserve 5 0 (FRQCR) IFC[2:0] 4-2 Division ratio of internal clock (Iφ) frequency 0 0:, When input clock 8MHz Iφ: 64MHz BFC[2:0] -9 Division ratio of bus clock (Bφ) frequency : /2, When input clock 8MHz Bφ: 32MHz PFC[2:0] 8-6 Division ratio of peripheral clock (Pφ) frequency : /2, When input clock 8MHz Pφ: 32MHz MIFC[2:0] 5-3 Division ratio of MTU2S clock (MIφ) frequency 0 0:, When input clock 8MHz MIφ: 64MHz MPFC[2:0] 2-0 Division ratio of MTU2S clock (Iφ) frequency : /2, When input clock 8MHz MPφ: 32MHz REJ05B /Rev Page 3 of 55

32 3.4 Used Function Setting Procedure SH747 Following describes procedure flow of sample programs. Please refer Table to 7 or SH747 Hardware Manual for each register settings. main SR 5: Set interrupt mask bit to 5 and prohibit interrupt Frequency setting (set_cpg_init) ADC_0 initial setting (set_ad_init) MTU2S initial setting (set_mtu2s_init) CMT_0, initial setting (set_cmt_init) ADC_0 conversion start [ADCR_0 setting] Set to ADST MTU2S CH3,4 count start [TSTR_S setting] Set H C0 to TSTR_S CMT_0, count start [CMSTR setting] Set H 03 to CMSTR SR 0: Set interrupt mask bit to 0 and enable interrupt Figure 6 Main Function Processing Flow REJ05B /Rev Page 32 of 55

33 set_cpg_init (frequency setting) IΦ (internal clock): Set to 64MHz [FRQCR setting] Set IFC to 0 BΦ (bus clock): Set to 32MHz Note: Bus clock do not affect this application example [FRQCR setting] Set BFC to PΦ (peripheral clock): Set to 32MHz [FRQCR setting] Set PFC to MIΦ (MTU2S clock): Set to 64MHz [FRQCR setting] Set MIFC to 0 MPΦ (MTU2 clock): Set to 32MHz Note: MTU2 clock do not affect this application example [FRQCR setting] Set MPFC to return Figure 7 Frequency Setting Process Flow REJ05B /Rev Page 33 of 55

34 set_ad_init (ADC_0 initial setting) ADC_0 module standby release [STBCR4 setting] ADC_0 conversion stop [ADCR setting] Conversion stop ADC_0 operation setting [ADCR setting] Set continuous scan mode Enable A/D conversion end interrupt Select analog input channel [ADANDR0-2 setting] Select AN0-2 as input channel Set interrupt priority of A/D conversion end interrupt [INTC setting] Set interrupt priority level to return Figure 8 ADC_0 Initial Setting Flow REJ05B /Rev Page 34 of 55

35 set_mtu2s_int (MTU2S initial setting) MTU2S module standby release [STBCR4 setting] Timer counter channel_3,4 operation stop [TSTRS setting] Timer counter channel_3,4 operation setting DC brushless motor control setting Timer counter channel_3,4 initial setting Duty setting Dead time setting Carrier period setting PWM output level setting Operation mode setting Output enable setting PFC setting return [TCR_3S/4S setting] Prohibit counter clear Count by rising edge MPΦ/ as count clock [TGCRS setting] TGCRS effective Antiphase PWM output Positive phase level output Output switch by software [TGCRS setting] Set dead time to TCNT_3S Set H 0000 to TCNT_4S [TGRD_3S/TGRB_3S setting] U-phase duty setting [TGRC_4S/TGRA_4S setting] V-phase duty setting [TGRD_4S/TGRB_4S setting] W-phase duty setting [TDERS setting] Generate dead time [TDDRS setting] Set dead time [TCBRS/TCDRS setting] Set /2 carrier period [TGRC_3S/TGRA_3 setting] Set /2 carrier period + dead time [TIOCRS setting] Prohibit toggle output synchronized to PWM cycle Select positive/anti-phase output level [TMDR_3S/4S setting] TGRB and TGRC is in buffer operation TGRA and TGRC is in buffer operation Complementary PWM mode (transfer at peak) [TOERS setting] Set output enable [PEIORH setting] Set MTU2S pin output [PECRH2/ setting] Select MTU2S pin Figure 9 MTU2S Initial Setting Flow REJ05B /Rev Page 35 of 55

36 set_cmt_init (CMT_0/ initial setting) Release CMT_0, module standby [STBCR4 setting] CMT_0, operation stop CMT_0 operation setting CMT_0 compare match period setting CMT_0 counter 0 clear CMT_ operation setting CMT_ compare match period setting CMT_ counter 0 clear CMT_0, compare match interrupt priority setting [CMSTR setting] Operation stop [CMCSR_0 setting] PΦ/8 as count clock [CMCOR_0 setting] Compare match at 50μ[s] [CMCNT_0 setting] Set to H 0000 [CMCSR_0 setting] Enable compare match interrupt PΦ/52 as count clock [CMCOR_ setting] Compare match at 0.8[s] [CMCNT_ setting] Set to H 0000 [INTC setting] Set CMT_0 interrupt priority level to 2 Set CMT_ interrupt priority level to 3 return Figure 20 CMT Initial Setting Flow REJ05B /Rev Page 36 of 55

37 ADI_3 (ADC_0 conversion end interrupt) Store ADDR0(AN0 conversion result) to RAM (resolver_re) resolver_ref? H 0B30? Yes No Flag set (flag_ref? H FF) resolver_ref? H 0570? Yes No Flag clear (flag_ref? H 00) H 980 > resolver_ref > H 0900? Yes No Flag clear? (flag_ref = H 00?) Yes No Transfer ADDR(AN conversion result) to RAM(Sin) Transfer ADDR2(AN2 conversion result) to RAM(Cos) Figure 2 ADC_0 Interrupt Process Flow () REJ05B /Rev Page 37 of 55

38 Sin H 0000 and Cos H 0000? Yes No i <? Yes No Enable compare match interrupt by CMT_0 CMIE i ++ Clear A/D end flag (ADF) ADF 0 return Figure 22 ADC_0 Interrupt Process Flow (2) REJ05B /Rev Page 38 of 55

39 CMI_0 (CMT_0 compare match interrupt) Clockwise motor revolving? No Yes Switch TGCRS depending on values of Sin and Cos Counterclockwise motor revolving? Yes No Switch TGCRS depending on values of Sin and Cos Clear compare match flag (CMF) CMF 0 return Figure 23 CMT_0 Interrupt Process Flow REJ05B /Rev Page 39 of 55

40 CMI_(CMT_ compare match interrupt) k < 5 No Yes Assign clockwise revolving k < 9? Yes No k ++ Assign counterclockwise revolving k ++ Assign counterclockwise revolving k 0 Clear compare match flag (CMF) CMF 0 return Figure 24 CMT_ Interrupt Process Flow REJ05B /Rev Page 40 of 55

41 4. Sample program /************************************************************************/ /* SH747 Motor Control */ /* - Resolver Built-in DC Brushless Motor - */ /* Used Module: */ /* ADC/MTU2S/CMT: */ /************************************************************************/ /* Include File */ #include <machine.h> #include"iodefine.h" /************************************************************************/ /* Function Declaration */ /************************************************************************/ void main(void); /* Main Function */ void set_cpg_init(void); /* Each Clock Setting */ void initial_value(void); /* Initializing Variable */ void set_ad_init(void); /* ADC Initial Setting */ void set_cmt_init(void); /* CMT Initial Setting */ void set_mtu2s_init(void); /* MTU2S Initial Setting */ /************************************************************************/ /* Variable Declaration */ /************************************************************************/ /* Used in ADC Interrupt Routine */ unsigned char flag_ref; /* Resolver Excitation Signal Slope Determination Flag */ unsigned short resolver_ref; /* Result of A/D Converting Resolver Excitation Signal */ unsigned short Sin; /* Result of A/D Converting Resolver Output Sin Wave */ unsigned short Cos; /* Result of A/D Converting Resolver Output Cos Wave */ unsigned char i; /* CMT_0 Interrupt Enable Flag */ /* Used in CMT_0 Interrupt Routine */ unsigned char flag_rot; /* Motor Revolving Direction Assigning Flag */ REJ05B /Rev Page 4 of 55

42 /* Used in CMT_ Interrupt Routine */ unsigned char k; /* CMT_ Interrupting Times Counting Flag */ /************************************************************************/ /* Symbol Declaration */ /************************************************************************/ /* Angle and A/D Conversion Result of Resolver Output Sin Wave */ #define Sin_0 0x0332 /* Result of A/D Converting Sin0 */ #define Sin_60 0x0522 /* Result of A/D Converting Sin60 */ #define Sin_80 0x0332 /* Result of A/D Converting Sin80 */ #define Sin_240 0x042 /* Result of A/D Converting Sin240 */ /* Angle and A/D Conversion Result of Resolver Output Cos Wave */ #define Cos_90 0x0332 /* Result of A/D Converting Cos90 */ #define Cos_50 0x042 /* Result of A/D Converting Cos50 */ #define Cos_270 0x0332 /* Result of A/D Converting Cos270 */ #define Cos_330 0x0522 /* Result of A/D Converting Cos330 */ /* Revolving Direction */ #define CW /* Clockwise of motor */ #define CCW 2 /* Counterclockwise of motor */ /* PWM Carrier Period/Dead Time */ #define CARRIER 0x0c80 /* PWM Carrier Period: 50[μs] */ #define HALF_CARRIER 0x0640 /* /2 of PWM Carrier Period: 25[μs] */ #define DEAD_TIME 0x000 /* Dead Time: 5.625[ns] */ #define TCNT3_COMP (DEAD_TIME + HALF_CARRIER) /* Dead Time + /2 of PWM Carrier Period */ /************************************************************************/ /* Main Function */ /************************************************************************/ void main(void){ set_imask(5); /* Interrupt Prohibited */ REJ05B /Rev Page 42 of 55

43 initial_value(); /* Initializing Variable */ set_cpg_init(); /* Each Clock Setting */ set_ad_init(); /* ADC Initial Setting */ set_mtu2s_init(); /* MTU2S Initial Setting */ set_cmt_init(); /* CMT Initial Setting */ AD0.ADCR.BIT.ADST = ; /* ADC_0 Conversion Start */ MTU2S.TSTR.BYTE = 0xC0; /* MTU2S ch3,4 Count Start */ CMT.CMSTR.WORD = 0x03; /* CMT ch0, Count Start */ SH747 set_imask(0); /* Interrupt Enable */ while(); /************************************************************************/ /* Initializing Variable */ /************************************************************************/ void initial_value(void){ /* Used in ADC Interrupt Routine */ flag_ref = 0; /* Resolver Excitation Signal Slope Flag */ i = 0; /* CMT_0 Interrupt Enable Flag */ resolver_ref = 0x00; /* Result of A/D Converting Resolver Excitation Signal */ Sin = 0x0000; /* Result of A/D Converting Resolver Output Sin Wave */ Cos = 0x0000; /* Result of A/D Converting Resolver Output Cos Wave */ /* Used in CMT_0 Interrupt Routine */ flag_rot = 0; /* Motor Revolving Direction Assigning Flag */ /* Used in CMT_ Interrupt Routine */ k = 0; /* CMT_ Interrupting Times Counting Flag */ /************************************************************************/ /* Each Clock Setting */ /* IΦ:BΦ:PΦ:MIΦ:MPΦ = 64MHz:32MHz:32MHz:64MHz:32MHz */ REJ05B /Rev Page 43 of 55