Preface. * ZTAT (Zero Turn-Around Time) is a trademark of Hitachi, Ltd.

Transcription

1 OMC Hitachi Single-Chip Microcomputer H8/534, H8/536 HD R, HD R HD R, HD R HD S, HD S HD S, HD S Hardware Manual ADE B

2 Preface The H8/534 and H8/536 are high-performance single-chip Hitachi-original microcomputers, featuring a high-speed CPU with 16-bit internal data paths and a full complement of on-chip supporting modules. They are ideal microcontrollers for a wide variety of medium-scale devices, including both office and industrial equipment and consumer products. The CPU has a general-register architecture. Its instruction set is highly orthogonal and is optimized for fast execution of programs coded in the high-level C language. For further speed, the existing 10-MHz lineup has been extended to include high-speed versions that operate at 16 MHz. Low-voltage versions that operate at 3 V and 2.7 V have also been developed. On-chip facilities include large RAM and ROM memories, numerous timers, serial I/O, an A/D converter, I/O ports, and other functions for compact implementation of high-performance application systems. H8/534 and H8/536 are available in both a ZTAT version* with on-chip PROM, ideal for the early stages of production or for products with frequently-changing specifications, and a masked- ROM version suitable for volume production. This manual gives a hardware description of the H8/534 and H8/536. For details of the instruction set, refer to the H8/500 Series Programming Manual, which applies to all chips in the H8/500 Series. * ZTAT (Zero Turn-Around Time) is a trademark of Hitachi, Ltd. 2

3 Contents Section 1 Overview 1.1 Features Block Diagram Pin Arrangements and Functions Pin Arrangement Pin Functions 9 Section 2 MCU Operating Modes and Address Space 2.1 Overview Mode Descriptions Address Space Map Page Segmentation Page 0 Address Allocations Mode Control Register (MDCR) 27 Section 3 CPU 3.1 Overview Features Address Space Register Configuration CPU Register Descriptions General Registers Control Registers Initial Register Values Data Formats Data Formats in General Registers Data Formats in Memory Instructions Basic Instruction Formats Addressing Modes Effective Address Calculation Instruction Set Overview Data Transfer Instructions Arithmetic Instructions Logic Operations Shift Operations Bit Manipulations Branching Instructions 57

4 3.5.8 System Control Instructions Short-Format Instructions Operating Modes Minimum Mode Maximum Mode Basic Operational Timing Overview On-Chip Memory Access Cycle Pin States during On-Chip Memory Access Register Field Access Cycle (Addresses H'FE80 to H'FFFF) Pin States during Register Field Access (Addresses H'FE80 to H'FFFF) External Access Cycle CPU States Overview Program Execution State Exception-Handling State Bus-Released State Reset State Power-Down State Programming Notes Restriction on Address Location 78 Section 4 Exception Handling 4.1 Overview Types of Exception Handling and Their Priority Hardware Exception-Handling Sequence Exception Factors and Vector Table Reset Overview Reset Sequence Stack Pointer Initialization Address Error Illegal Instruction Prefetch Word Data Access at Odd Address Off-Chip Address Access in Single-Chip Mode Trace Interrupts Invalid Instruction Trap Instructions and Zero Divide Cases in Which Exception Handling is Deferred Instructions that Disable Interrupts 91

5 4.8.2 Disabling of Exceptions Immediately after a Reset Disabling of Interrupts after a Data Transfer Cycle Stack Status after Completion of Exception Handling PC Value Pushed on Stack for Trace, Interrupts, Trap Instructions, and Zero Divide Exceptions PC Value Pushed on Stack for Address Error and Invalid Instruction Exceptions Notes on Use of the Stack 95 Section 5 Interrupt Controller 5.1 Overview Features Block Diagram Register Configuration Interrupt Types External Interrupts Internal Interrupts Interrupt Vector Table Register Descriptions Interrupt Priority Registers A to F (IPRA to IPRF) Timing of Priority Setting Interrupt Handling Sequence Interrupt Handling Flow Stack Status after Interrupt Handling Sequence Timing of Interrupt Exception-Handling Sequence Interrupts During Operation of the Data Transfer Controller Interrupt Response Time 112 Section 6 Data Transfer Controller 6.1 Overview Features Block Diagram Register Configuration Register Descriptions Data Transfer Mode Register (DTMR) Data Transfer Source Address Register (DTSR) Data Transfer Destination Register (DTDR) Data Transfer Count Register (DTCR) Data Transfer Enable Registers A to F (DTEA to DTEF) Data Transfer Operation Data Transfer Cycle 118

6 6.3.2 DTC Vector Table Location of Register Information in Memory Length of Data Transfer Cycle Procedure for Using the DTC Example 125 Section 7 Wait-State Controller 7.1 Overview Features Block Diagram Register Configuration Wait-State Control Register Operation in Each Wait Mode Programmable Wait Mode Pin Wait Mode Pin Auto-Wait Mode 133 Section 8 Clock Pulse Generator 8.1 Overview Block Diagram Oscillator Circuit System Clock Divider 139 Section 9 I/O Ports 9.1 Overview Port Overview Port 1 Registers Pin Functions in Each Mode Port Overview Port 2 Registers Pin Functions in Each Mode Port Overview Port 3 Registers Pin Functions in Each Mode Port Overview Port 4 Registers Pin Functions in Each Mode 158

7 9.6 Port Overview Port 5 Registers Pin Functions in Each Mode Built-In MOS Pull-Up Port Overview Port 6 Registers Pin Functions in Each Mode Built-In MOS Pull-Up Port Overview Port 7 Registers Pin Functions Port Overview Port 8 Registers Port Overview Port 9 Registers Pin Functions 179 Section Bit Free-Running Timers 10.1 Overview Features Block Diagram Input and Output Pins Register Configuration Register Descriptions Free-Running Counter (FRC) H'FE92, H'FEA2, H'FEB Output Compare Registers A and B (OCRA and OCRB) H'FE94 and H'FE96, H'FEA4 and H'FEA6, H'FEB4 and H'FEB Input Capture Register (ICR) H'FE98, H'FEA8, H'FEB Timer Control Register (TCR) Timer Control/Status Register (TCSR) CPU Interface Operation FRC Incrementation Timing Output Compare Timing Input Capture Timing Setting of FRC Overflow Flag (OVF) 201

8 10.5 CPU Interrupts and DTC Interrupts Synchronization of Free-Running Timers 1 to Synchronization after a Reset Synchronization by Writing to FRCs Sample Application Application Notes 206 Section 11 8-Bit Timer 11.1 Overview Features Block Diagram Input and Output Pins Register Configuration Register Descriptions Timer Counter (TCNT) H'FED Time Constant Registers A and B (TCORA and TCORB) H'FED2 and H'FED Timer Control Register (TCR) H'FED Timer Control/Status Register (TCSR) H'FED Operation TCNT Incrementation Timing Compare Match Timing External Reset of TCNT Setting of TCNT Overflow Flag CPU Interrupts and DTC Interrupts Sample Application Application Notes 226 Section 12 PWM Timer 12.1 Overview Features Block Diagram Input and Output Pins Register Configuration Register Descriptions Timer Counter (TCNT) H'FEC2, H'FEC4, H'FECA Duty Register (DTR) H'FEC1, H'FEC5, H'FEC Timer Control Register (TCR) H'FEC0, H'FEC4, H'FEC Operation Application Notes 240

9 Section 13 Watchdog Timer 13.1 Overview Features Block Diagram Register Configuration Register Descriptions Timer Counter TCNT H'FEEC (Write), H'FEED (Read) Timer Control/Status Register (TCSR) H'FEEC Reset Control/Status Register (RSTCSR) H'FF14 (Write), H'FF15 (Read) Notes on Register Access Operation Watchdog Timer Mode Interval Timer Mode Operation in Software Standby Mode Setting of Overflow Flag Setting of Watchdog Timer Reset (WRST) Bit Application Notes 252 Section 14 Serial Communication Interface 14.1 Overview Features Block Diagram Input and Output Pins Register Configuration Register Descriptions Receive Shift Register (RSR) Receive Data Register (RDR) H'FEDD, H'FEF Transmit Shift Register (TSR) Transmit Data Register (TDR) H'FEDB, H'FEF Serial Mode Register (SMR) H'FED8, H'FEF Serial Control Register (SCR) H'FEDA, H'FEF Serial Status Register (SSR) H'FEDC, H'FEF Bit Rate Register (BRR) H'FED9, H'FEF Operation Overview Asynchronous Mode Synchronous Mode CPU Interrupts and DTC Interrupts Application Notes 280

10 Section 15 A/D Converter 15.1 Overview Features Block Diagram Input Pins Register Configuration Register Descriptions A/D Data Registers (ADDR) H'FEE0 to H'FEE A/D Control/Status Register (ADCSR) H'FEE A/D Control Register (ADCR) H'FEE CPU Interface Operation Single Mode (SCAN = 0) Scan Mode (SCAN = 1) Input Sampling Time and A/D Conversion Time External Triggering of A/D Conversion Interrupts and the Data Transfer Controller 298 Section 16 RAM 16.1 Overview Block Diagram Register Configuration RAM Control Register (RAMCR) Operation Expanded Modes (Modes 1, 2, 3, and 4) Single-Chip Mode (Mode 7) 301 Section 17 ROM 17.1 Overview Block Diagram PROM Mode PROM Mode Setup Socket Adapter Pin Arrangements and Memory Map H8/534 Programming Writing and Verifying Notes on Writing H8/536 Programming Writing and Verifying Notes on Programming Reliability of Written Data Erasing of Data 318

11 17.7 Handling of Windowed Packages 319 Section 18 Power-Down State 18.1 Overview Sleep Mode Transition to Sleep Mode Exit from Sleep Mode Software Standby Mode Transition to Software Standby Mode Software Standby Control Register (SBYCR) Exit from Software Standby Mode Sample Application of Software Standby Mode Application Notes Hardware Standby Mode Transition to Hardware Standby Mode Recovery from Hardware Standby Mode Timing Sequence of Hardware Standby Mode 326 Section 19 E Clock Interface 19.1 Overview 327 Section 20 Electrical Specifications 20.1 Absolute Maximum Ratings Electrical Characteristics DC Characteristics AC Characteristics A/D Converter Characteristics MCU Operational Timing Bus Timing Control Signal Timing Clock Timing I/O Port Timing Bit Free-Running Timer Timing Bit Timer Timing Pulse Width Modulation Timer Timing Serial Communication Interface Timing A/D Trigger Signal Input Timing 361 Appendix A Instructions A.1 Instruction Set 363 A.2 Instruction Codes 368

12 A.3 Operation Code Map 379 A.4 Instruction Execution Cycles 384 A.4.1 Calculation of Instruction Execution States 384 A.4.2 Tables of Instruction Execution Cycles 385 Appendix B Register Field B.1 Register Addresses and Bit Names 393 B.2 Register Descriptions 398 Appendix C I/O Port Schematic Diagrams C.1 Schematic Diagram of Port C.2 Schematic Diagram of Port C.3 Schematic Diagram of Port C.4 Schematic Diagram of Port C.5 Schematic Diagram of Port C.6 Schematic Diagram of Port C.7 Schematic Diagram of Port C.8 Schematic Diagram of Port C.9 Schematic Diagram of Port Appendix D Memory Maps 463 Appendix E Pin States E.1 Port State of Each Pin State 465 E.2 Pin States in Reset State 468 Appendix F Timing of Transition to and Recovery from Hardware Standby Mode 475 Appendix G Package Dimensions 476

13 Figures 1-1 Block Diagram Pin Arrangement (CP-84, Top View) Pin Arrangement (CG-84, Top View) Pin Arrangement (FP-80A, TFP-80C, Top View) H8/534 Memory Map in Each Operating Mode H8/536 Memory Map in Each Operating Mode CPU Operating Modes Registers in the CPU Stack Pointer Combinations of Page Registers with Other Registers Short Absolute Addressing Mode and Base Register On-Chip Memory Access Timing Pin States during Access to On-Chip Memory Register Field Access Timing Pin States during Register Field Access (a) External Access Cycle (Read Access) (b) External Access Cycle (Write Access) Operating States State Transitions Bus-Right Release Cycle (During On-chip Memory Access Cycle) Bus-Right Release Cycle (During External Access Cycle) Bus-Right Release Cycle (During Internal CPU Operation) Types of Factors Causing Exception Handling Reset Vector Reset Sequence (Minimum Mode, On-Chip Memory) Reset Sequence (Maximum Mode, External Memory) Interrupt Sources (and Number of Interrupt Types) Interrupt Controller Block Diagram Interrupt Handling Flowchart (a) Stack before and after Interrupt Exception-Handling (Minimum Mode) (b) Stack before and after Interrupt Exception-Handling (Maximum Mode) Interrupt Sequence (Minimum Mode, On-Chip Memory) Interrupt Sequence (Maximum Mode, External Memory) Block Diagram of Data Transfer Controller Flowchart of Data Transfer Cycle DTC Vector Table DTC Vector Table Entry Order of Register Information Use of DTC to Receive Data via Serial Communication Interface Block Diagram of Wait-State Controller 128

14 7-2 Programmable Wait Mode Pin Wait Mode Pin Auto-Wait Mode Block Diagram of Clock Pulse Generator Connection of Crystal Oscillator (Example) Crystal Oscillator Equivalent Circuit Notes on Board Design around External Crystal External Clock Input (Example) External Clock Input (Examples) Phase Relationship of ø Clock and E clock Pin Functions of Port Pin Functions of Port Port 2 Pin Functions in Expanded Modes Port 2 Pin Functions in Single-Chip Mode Pin Functions of Port Port 3 Pin Functions in Expanded Modes Port 3 Pin Functions in Single-Chip Mode Pin Functions of Port Port 4 Pin Functions in Expanded Modes Port 4 Pin Functions in Single-Chip Mode Pin Functions of Port Port 5 Pin Functions in Modes 1 and Port 5 Pin Functions in Modes 2 and Port 5 Pin Functions in Single-Chip Mode Pin Functions of Port Port 6 Pin Functions in Mode Port 6 Pin Functions in Mode Port 6 Pin Functions in Modes 7, 2, and Pin Functions of Port Pin Functions of Port Pin Functions of Port Block Diagram of 16-Bit Free-Running Timer (a) Write Access to FRC (When CPU Writes H'AA55) (b) Read Access to FRC (When FRC Contains H'AA55) Increment Timing for External Clock Input Setting of Output Compare Flags Timing of Output Compare A Clearing of FRC by Compare-Match A Input Capture Timing (Usual Case) Input Capture Timing (1-State Delay) Setting of Input Capture Flag 200

15 10-10 Setting of Overflow Flag (OVF) Square-Wave Output (Example) FRC Write-Clear Contention FRC Write-Increment Contention Contention between OCR Write and Compare-Match Block Diagram of 8-Bit Timer Count Timing for External Clock Input Setting of Compare-Match Flags Timing of Timer Output Timing of Compare-Match Clear Timing of External Reset Setting of Overflow Flag (OVF) Example of Pulse Output TCNT Write-Clear Contention TCNT Write-Increment Contention Contention between TCOR Write and Compare-Match Block Diagram of PWM Timer PWM Timing Block Diagram of Timer Counter Writing to TCNT and TCSR Writing to RSTCSR Operation in Watchdog Timer Mode Operation in Interval Timer Mode Setting of OVF Bit Setting of WRST Bit and Internal Reset Signal TCNT Write-Increment Contention Reset Circuit (Example) Block Diagram of Serial Communication Interface Data Format in Asynchronous Mode Phase Relationship between Clock Output and Transmit Data Data Format in Synchronous Mode Sampling Timing (Asynchronous Mode) Block Diagram of A/D Converter Read Access to A/D Data Register (When Register Contains H'AA40) A/D Operation in Single Mode (When Channel 1 is Selected) A/D Operation in Scan Mode (When Channels 0 to 2 are Selected) A/D Conversion Timing Timing of Setting of ADST Bit Block Diagram of On-Chip RAM Block Diagram of On-Chip ROM (a) Socket Adapter Pin Arrangements (H8/534) 306

16 17-2 (b) Socket Adapter Pin Arrangements (H8/536) Memory Map in PROM Mode High-Speed Programming Flowchart (H8/534) PROM Write/Verify Timing (H8/534) High-Speed Programming Flowchart (H8/536) PROM Write/Verify Timing (H8/536) Recommended Screening Procedure NMI Timing of Software Standby Mode (Application Example) Hardware Standby Sequence Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes (Maximum Synchronization Delay) Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes (Minimum Synchronization Delay) Example of Circuit for Driving a Darlington Transistor Pair Example of Circuit for Driving an LED Output Load Circuit Basic Bus Cycle (without Wait States) in Expanded Modes Basic Bus Cycle (with 1 Wait State) in Expanded Modes Bus Cycle Synchronized with E Clock Reset Input Timing Reset Output Timing Interrupt Input Timing Bus Release State Timing E Clock Timing Clock Oscillator Stabilization Timing I/O Port Input/Output Timing Free-Running Timer Input/Output Timing External Clock Input Timing for Free-Running Timers Bit Timer Output Timing Bit Timer Clock Input Timing Bit Timer Reset Input Timing PWM Timer Output Timing SCI Input Clock Timing SCI Input/Output Timing (Synchronous Mode) A/D Trigger Signal Input Timing 361 C-1 (a) Schematic Diagram of Port 1, Pin P C-1 (b) Schematic Diagram of Port 1, Pin P C-1 (c) Schematic Diagram of Port 1, Pin P C-1 (d) Schematic Diagram of Port 1, Pin P C-1 (e) Schematic Diagram of Port 1, Pin P C-1 (f) Schematic Diagram of Port 1, Pin P15 441

17 C-1 (g) Schematic Diagram of Port 1, Pin P C-1 (h) Schematic Diagram of Port 1, Pin P C-2 Schematic Diagram of Port C-3 Schematic Diagram of Port C-4 Schematic Diagram of Port C-5 Schematic Diagram of Port C-6 (a) Schematic Diagram of Port 6, Pin P C-6 (b) Schematic Diagram of Port 6, Pin P61 to P C-7 (a) Schematic Diagram of Port 7, Pin P C-7 (b) Schematic Diagram of Port 7, Pins P71 and P C-7 (c) Schematic Diagram of Port 7, Pin P C-7 (d) Schematic Diagram of Port 7, Pins P74, P75 and P C-7 (e) Schematic Diagram of Port 7, Pin P C-8 Schematic Diagram of Port C-9 (a) Schematic Diagram of Port 9, Pins P90 and P C-9 (b) Schematic Diagram of Port 9, Pin P C-9 (c) Schematic Diagram of Port 9, Pin P C-9 (d) Schematic Diagram of Port 9, Pin P C-9 (e) Schematic Diagram of Port 9, Pin P C-9 (f) Schematic Diagram of Port 9, Pin P C-9 (g) Schematic Diagram of Port 9, Pin P E-1 Reset during Memory Access (Mode 1) 469 E-2 Reset during Memory Access (Mode 2) 470 E-3 Reset during Memory Access (Mode 3) 472 E-4 Reset during Memory Access (Mode 4) 473 E-5 Reset during Memory Access (Mode 7) 474 G-1 Package Dimensions (CP-84) 476 G-2 Package Dimensions (CG-84) 476 G-3 Package Dimensions (FP-80A) 477 G-4 Package Dimensions (TFP-80C) 477 Tables 1-1 Features Pin Arrangements in Each Operating Mode (CP-84, CG-84) Pin Arrangements in Each Operating Mode (FP-80A, TFP-80C) Pin Functions Operating Modes Mode Control Register Interrupt Mask Levels Interrupt Mask Bits after an Interrupt is Accepted Initial Values of Registers 41

18 3-4 General Register Data Formats Data Formats in Memory Data Formats on the Stack Addressing Modes Effective Address Calculation Instruction Classification Data Transfer Instructions Arithmetic Instructions Logic Operation Instructions Shift Instructions Bit-Manipulation Instructions Branching Instructions System Control Instructions Short-Format Instructions and Equivalent General Formats (a) Exceptions and Their Priority (b) Instruction Exceptions Exception Vector Table Stack after Exception Handling Sequence Interrupt Controller Registers Interrupts, Vectors, and Priorities Assignment of Interrupt Priority Registers Number of States before Interrupt Service Internal Control Registers of the DTC Data Transfer Enable Registers Assignment of Data Transfer Enable Registers Addresses of DTC Vectors Number of States per Data Transfer Number of States before Interrupt Service DTC Control Register Information Set in RAM Register Configuration Wait Modes (1) External Crystal Parameters (HD R, HD R, HD R, HD R) (2) External Crystal Parameters (HD S, HD S, HD S, HD S) Input/Output Port Summary Port 1 Registers Port 1 Pin Functions in Expanded Modes Port 1 Pin Functions in Single-Chip Modes Port 2 Registers Port 3 Registers 154

19 9-7 Port 4 Registers Port 5 Registers Status of MOS Pull-Ups for Port Port 6 Registers Port 6 Pin Functions in Modes 7, 2, and Status of MOS Pull-Ups for Port Port 7 Registers Port 7 Pin Functions Port 8 Registers Port 9 Registers Port 9 Pin Functions Input and Output Pins of Free-Running Timer Module Register Configuration Free-Running Timer Interrupts Synchronization by Writing to FRCs Effect of Changing Internal Clock Sources Input and Output Pins of 8-Bit Timer Bit Timer Registers Bit Timer Interrupts Priority Order of Timer Output Effect of Changing Internal Clock Sources Output Pins of PWM Timer Module PWM Timer Registers PWM Timer Parameters for 10 MHz System Clock Register Configuration Read Addresses of TCNT and TCSR SCI Input/Output Pins SCI Registers Examples of BRR Settings in Asynchronous Mode Examples of BRR Settings in Synchronous Mode Communication Formats Used by SCI SCI Clock Source Selection Data Formats in Asynchronous Mode Receive Errors SCI Interrupts SSR Bit States and Data Transfer When Multiple Receive Errors Occur A/D Input Pins A/D Registers Assignment of Data Registers to Analog Input Channels A/D Conversion Time (Single Mode) RAM Control Register 300

20 17-1 ROM Usage in Each MCU Mode Selection of PROM Mode Socket Adapter Selection of Sub-Modes in PROM Mode (H8/534) DC Characteristics (H8/534) (When VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, VSS = 0 V, Ta = 25 C ±5 C) AC Characteristics (H8/534) (When VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, Ta = 25 C ±5 C) Selection of Sub-Modes in PROM Mode (H8/536) DC Characteristics (H8/536) (When VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, VSS = 0 V, Ta = 25 C ±5 C) AC Characteristics (H8/536) (When VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, Ta = 25 C ±5 C) PROM Writers Erasing Conditions Socket for 84-Pin LCC Package Power-Down State Software Standby Control Register Absolute Maximum Ratings DC Characteristics (5-V Versions) DC Characteristics (3-V S-Mask Versions) DC Characteristics (2.7-V S-Mask Versions) Allowable Output Current Values (5-V Versions) Allowable Output Current Values (3-V S-Mask Versions) Allowable Output Current Values (2.7-V S-Mask Versions) (1) Bus Timing (R-Mask Versions) (2) Bus Timing (S-Mask Versions) (1) Control Signal Timing (R-Mask Versions) (2) Control Signal Timing (S-Mask Versions) Timing Conditions of On-Chip Supporting Modules A/D Converter Characteristics (5-V Versions) A/D Converter Characteristics 350 A-1 (a) Machine Language Coding [General Format] 372 A-1 (b) Machine Language Coding [Special Format: Short Format] 376 A-1 (c) Machine Language Coding [Special Format: Branch Instruction] 377 A-1 (d) Machine Language Coding [Special Format: System Control Instructions] 378 A-2 Operation Codes in Byte A-3 Operation Codes in Byte 2 (Axxx) 380 A-4 Operation Codes in Byte 2 (05xx, 15xx, 0Dxx, 1Dxx, Bxxx, Cxxx, Dxxx, Exxx, Fxxx) 381 A-5 Operation Codes in Byte 2 (04xx, 0Cxx) 382

21 A-6 Operation Codes in Bytes 2 and 3 (11xx, 01xx, 06xx, 07xx, xx00xx) 383 A-7 Instruction Execution Cycles (1) 387 A-7 Instruction Execution Cycles (2) 388 A-7 Instruction Execution Cycles (3) 389 A-7 Instruction Execution Cycles (4) 390 A-7 Instruction Execution Cycles (5) 391 A-7 Instruction Execution Cycles (6) 392 A-8 (a) Adjusted Value (Branch Instruction) 392 A-8 (b) Adjusted Value (Other Instructions by Addressing Modes) 392 C-1 (a) Port 1 Port Read (Pin P10) 437 C-1 (b) Port 1 Port Read (Pin P11) 438 C-1 (c) Port 1 Port Read (Pin P12) 438 C-1 (d) Port 1 Port Read (Pin P13) 439 C-1 (e) Port 1 Port Read (Pin P14) 440 C-1 (f) Port 1 Port Read (Pin P15) 441 C-1 (g) Port 1 Port Read (Pin P16) 442 C-1 (h) Port 1 Port Read (Pin P17) 443 C-2 Port 2 Port Read 444 C-3 Port 3 Port Read 445 C-4 Port 4 Port Read 446 C-5 Port 5 Port Read 447 C-6 (a) Port 6 Port Read (Pin P60) 448 C-6 (b) Port 6 Port Read (Pin P61 to P63) 449 C-7 (a) Port 7 Port Read (Pin P70) 450 C-7 (b) Port 7 Port Read (Pins P71, P72) 451 C-7 (c) Port 7 Port Read (Pin P73) 452 C-7 (d) Port 7 Port Read (Pins P74 to P76) 453 C-7 (e) Port 7 Port Read (Pin P77) 454 C-9 (a) Port 9 Port Read (Pins P90, P91) 456 C-9 (b) Port 9 Port Read (Pin P92) 457 C-9 (c) Port 9 Port Read (Pin P93) 458 C-9 (d) Port 9 Port Read (Pin P94) 459 C-9 (e) Port 9 Port Read (Pin P95) 460 C-9 (f) Port 9 Port Read (Pin P96) 461 C-9 (g) Port 9 Port Read (Pin P97) 462 D-1 H8/534 Memory Map 463 D-2 H8/536 Memory Map 464 E-1 Port State 465 E-2 MOS Pull-Up State 467

22 Section 1 Overview 1.1 Features The H8/534 and H8/536 are CMOS microcomputer units (MCUs) comprising a CPU core plus a full range of supporting functions an entire system integrated onto a single chip. The CPU features a highly orthogonal instruction set that permits addressing modes and data sizes to be specified independently in each instruction. An internal 16-bit architecture and 16-bit access to on-chip memory enhance the CPU s data-processing capability and provide the speed needed for realtime control applications. The on-chip supporting functions include RAM, ROM, timers, a serial communication interface (SCI), A/D conversion, and I/O ports. An on-chip data transfer controller (DTC) can transfer data in either direction between memory and I/O independently of the CPU. For the on-chip ROM, a choice is offered between masked ROM and programmable ROM (PROM). The PROM version can be programmed by the user with a general-purpose PROM writer. Table 1-1 lists the main features of the H8/534 and H8/536. 1

23 Table 1-1 Features Feature CPU Memory (H8/534) Memory (H8/536) 16-Bit freerunning timer (FRT) Description General-register machine Eight 16-bit general registers Five 8-bit and two 16-bit control registers High speed Maximum clock rate: 10 MHz (oscillator frequency: 20 MHz, R-mask versions) 16 MHz (oscillator frequency: 32 MHz, S-mask versions) Expanded operating modes supporting external memory Minimum mode: up to 64-kbyte address space Maximum mode: up to 1 M-byte address space Highly orthogonal instruction set Addressing modes and data size can be specified independently for each instruction 1.5 Addressing modes Register-register operations Register-memory operations Instruction set optimized for C language Special short formats for frequently-used instructions and addressing modes 2-kbyte high-speed RAM on-chip 32-kbyte programmable or masked ROM on-chip 2-kbyte high-speed RAM on-chip 62-kbyte programmable or masked ROM on-chip Each channel provides: 1 free-running counter (which can count external events) 2 output-compare registers (3 channels) 1 input capture register 8-Bit timer One 8-bit up-counter (which can count external events) (1 channel) 2 time constant registers PWM timer Generates pulses with any duty ratio from 0 to 100% (3 channels) Resolution: 1/250 Watchdog An overflow generates a nonmaskable interrupt timer (WDT) Can also be used as an interval timer (1 channel) 2

24 Table 1-1 Features (cont) Feature Serial communication interface (SCI) (2 channels) A/D converter I/O ports Description Asynchronous or synchronous mode (selectable) Full duplex: can send and receive simultaneously Built-in baud rate generator 10-Bit resolution 8 channels, controllable in single mode or scan mode (selectable) Sample-and-hold function Start of A/D conversion can be externally triggered 57 Input/output pins (six 8-bit ports, one 5-bit port, one 4-bit port) 8 Input-only pins (one 8-bit port) 7 external interrupt pins (NMI, IRQ0, IRQ1 to IRQ5) 23 internal interrupts 8 priority levels Performs bidirectional data transfer between memory and I/O independently of the CPU Can insert wait states in access to external memory or I/O Interrupt controller (INTC) Data transfer controller (DTC) Wait-state controller (WSC) Operating 5 MCU operating modes modes Other features Expanded minimum modes, supporting up to 64 kbytes external memory with or without using on-chip ROM (Modes 1 and 2) Expanded maximum modes, supporting up to 1 Mbyte external memory with or without using on-chip ROM (Modes 3 and 4) Single-chip mode (Mode 7) 3 power-down modes Sleep mode Software standby mode Hardware standby mode E clock output available Clock generator on-chip Product line-up (H8/534 R-mask versions) Product line-up (H8/534 S-mask versions) Model Name Package Options ROM HD RCG 84-Pin windowed LCC (CG-84) PROM HD RCP 84-Pin PLCC (CP-84) HD RF 80-Pin QFP (FP-80A) HD RCP 84-Pin PLCC (CP-84) Mask HD RF 80-Pin QFP (FP-80A) ROM Model Name Package Options ROM HD SCG 84-Pin windowed LCC (CG-84) PROM HD SCP 84-Pin PLCC (CP-84) HD SF 80-Pin QFP (FP-80A) HD STF 80-Pin TQFP (TFP-80C) HD SCP 84-Pin PLCC (CP-84) Mask HD SF 80-Pin QFP (FP-80A) ROM HD STF 80-Pin TQFP (TFP-80C) 3

25 Table 1-1 Features (cont) Feature Product line-up (H8/536 R-mask versions) Product line-up (H8/536 S-mask versions) Description Model Name Package Options ROM HD RCG 84-Pin windowed LCC (CG-84) PROM HD RCP 84-Pin PLCC (CP-84) HD RF 80-Pin QFP (FP-80A) HD RCP 84-Pin PLCC (CP-84) Mask HD RF 80-Pin QFP (FP-80A) ROM Model Name Package Options ROM HD SCG 84-Pin windowed LCC (CG-84) PROM HD SCP 84-Pin PLCC (CP-84) HD SF 80-Pin QFP (FP-80A) HD STF 80-Pin TQFP (TFP-80C) HD SCP 84-Pin PLCC (CP-84) Mask HD SF 80-Pin QFP (FP-80A) ROM HD STF 80-Pin TQFP (TFP-80C) Product 16-MHz High- 3-V 2.7-V line-up Regular Speed Low-Voltage Low-Voltage Versions Versions Versions* Versions* Model PROM HD R HD S HD SV HD SV name HD R HD S HD SV HD SV Mask HD R HD S HD SV HD SV ROM HD R HD S HD SV HD SV Clock speed 0.5 MHz to 2 MHz to 2 MHz to 2 MHz to Supply voltage 10 MHz 16 MHz 10 MHz 8 MHz 5 V ± 10% 5 V ± 10% 3 V to 5.5 V 2.7 V to 5.5 V Notes: The product codes of the 3-V and 2.7-V low-voltage versions include a suffix that identifies the clock speed. Examples are shown below for the H8/536 PROM version in an 80-pin QFP package. Examples: 3-V versions: HD SVF V versions: HD SVF8 * Under development 4

26 1.2 Block Diagram Figure 1-1 shows a block diagram of the H8/534 and H8/536. Port 1 Port 2 Port 3 EXTAL XTAL RES STBY MD0 MD1 MD2 NMI V cc V cc V ss V ss V ss V ss * V ss V ss AVcc AVss Clock Generator Wait- State Controller RAM 2 kbyte Interrupt Controller Data Transfer Controller Serial Communication Interface PWM Timer (x 3 channels) 10-bit A/D Converter PROM/Mask ROM 32 kbytes (H8/534) 62 kbytes (H8/536) CPU 8-bit Timer 16-bit Free Running Timer (x 3 channels) Watchdog Timer Data bus (Low) P4 7/A 7 P4 6/A 6 P4 5/A 5 P4 4/A 4 P4 3/A 3 P4 2/A 2 P4 1/A 1 P4 0/A 0 P5 7/A15 P5 6/A14 P5 5/A13 P5 4/A12 P5 3/A11 P5 2/A10 P5 1/A 9 P5 0/A 8 Port 9 Port 8 Port 7 P8 7 /AN 7 P8 6 /AN 6 P8 5 /AN 5 P8 4 /AN 4 P8 3 /AN 3 P8 2 /AN 2 P8 1 /AN 1 P8 0 /AN 0 P7 7 /FTOA1 P7 6 /FTOB 3 /FTCI 3 P7 5 /FTOB 2 /FTCI 2 P7 4 /FTOB 1 /FTCI 1 P7 3 /FTI 3 /TMRI P7 2 /FTI 2 P7 1 /FTI 1 P7 0 /TMCI Data bus (High) Address bus P1 7 /TMO P1 6 /IRQ 1 /ADTRG P1 5 /IRQ 0 P1 4 /WAIT P1 3 /BREQ P1 2 /BACK P1 1 /E P1 0 /ø Port 6 Port 5 Port 4 P2 4 /WR P2 3 /RD P2 2 /DS P2 1 /R/W P2 0 /AS P3 7 /D 7 P3 6 /D 6 P3 5 /D 5 P3 4 /D 4 P3 3 /D 3 P3 2 /D 2 P3 1 /D 1 P3 0 /D 0 P6 3/PW 3/IRQ 5/A19 P6 2/PW 2/IRQ 4/A18 P6 1/PW 1/IRQ 3/A17 P6 0/IRQ 2/A16 P9 7 /SCK P9 6 /RXD P9 5 /TXD P9 4 /SCK 2 /PW 3 P9 3 /RXD 2 /PW 2 P9 2 /TXD 2 /PW 1 P9 1 /FTOA 3 P9 0 /FTOA * CP-84 and CG-84 only Figure 1-1 Block Diagram 5

27 1.3 Pin Arrangements and Functions Pin Arrangement Figure 1-2 shows the pin arrangement of the CP-84 package. Figure 1-3 shows the pin arrangement of the CG-84 package. Figure 1-4 shows the pin arrangement of the FP-80A package. These pin arrangements apply to both the H8/534 and H8/536. P2 0 /AS P1 7 /TMO P1 6 /IRQ 1 /ADTRG P1 5 /IRQ 0 P1 4 /WAIT P1 3 /BREQ P1 2 /BACK P1 1 /E P1 0 /ø V ss XTAL EXTAL V ss P9 7 /SCK 1 P9 6 /RXD 1 P9 5 /TXD 1 P9 4 /SCK 2 /PW 3 P9 3 /RXD 2 /PW 2 P9 2 /TXD 2 /PW 1 P9 1 /FTOA 3 P9 0 /FTOA 2 P2 1 /R/W P2 2/DS P2 3 /RD P2 4/WR V cc MD 0 MD 1 MD 2 STBY RES NMI NC V ss P3 0/D 0 P3 1/D 1 P3 2/D 2 P3 3/D 3 P3 4/D 4 P3 5/D 5 P3 6/D 6 P3 7/D PLCC P4 0 /A P4 1 /A P4 2 /A P4 3 /A P4 4 /A P4 5 /A P4 6 /A P4 7 /A ss ss V V P5 0 /A 8 P5 1 /A 9 P5 2 /A 10 P5 3 /A 11 P5 4 /A 12 P5 5 /A 13 P5 6 /A 14 P5 7 /A 15 P6 0 /IRQ 2 /A 16 P6 1 /PW 1 /IRQ 3 /A 17 P6 2 /PW 2 /IRQ 4 /A AVcc P8 7 /AN7 P8 6 /AN6 P8 5 /AN5 P8 4 /AN4 P8 3 /AN3 P8 2 /AN2 P8 1 /AN1 P8 0 /AN0 AVss Vss P7 7 /FTOA1 P7 6 /FTOB 3/FTCI 3 P7 5 /FTOB 2/FTCI 2 P7 4 /FTOB 1/FTCI 1 P7 3 /FTI 3/TMRI P7 2 /FTI 2 P7 1 /FTI1 P7 0 /TMCI Vcc P6 3 /PW 3/IRQ 5/A19 1 pin H8/534 HD CP JAPAN 1 pin H8/536 HD CP JAPAN Figure 1-2 Pin Arrangement (CP-84, Top View) 6

28 P2 0 /AS P1 7 /TMO P1 6 /IRQ 1 /ADTRG P1 5 /IRQ 0 P1 4 /WAIT P1 3 /BREQ P1 2 /BACK P1 1 /E P1 0 /ø V ss XTAL EXTAL V ss P9 7 /SCK 1 P9 6 /RXD 1 P9 5 /TXD 1 P9 4 /SCK 2 /PW 3 P9 3 /RXD 2 /PW 2 P9 2 /TXD 2 /PW 1 P9 1 /FTOA 3 P9 0 /FTOA P2 1 /R/W 12 P2 2/DS 13 P2 3 /RD 14 P2 4/WR 15 V cc 16 MD 0 17 MD 1 18 MD 2 19 STBY 20 RES 21 NMI 22 NC 23 V ss 24 P3 0/D 0 25 P3 1/D 1 26 P3 2/D 2 27 P3 3/D 3 28 P3 4/D 4 29 P3 5/D 5 30 P3 6/D 6 31 P3 7/D 7 32 LCC AVcc 73 P8 7 /AN7 72 P8 6 /AN6 71 P8 5 /AN5 70 P8 4 /AN4 69 P8 3 /AN3 68 P8 2 /AN2 67 P8 1 /AN1 66 P8 0 /AN0 65 AVss 64 Vss 63 P7 7 /FTOA1 62 P7 6 /FTOB 3/FTCI 3 61 P7 5 /FTOB 2/FTCI 2 60 P7 4 /FTOB 1/FTCI 1 59 P7 3 /FTI 3/TMRI 58 P7 2 /FTI 2 57 P7 1 /FTI1 56 P7 0 /TMCI 55 Vcc 54 P6 3 /PW 3 /IRQ 5/A P4 0 /A P4 1 /A P4 2 /A P4 3 /A P4 4 /A P4 5 /A P4 6 /A P4 7 /A ss ss V V P5 0 /A 8 P5 1 /A 9 P5 2 /A 10 P5 3 /A 11 P5 4 /A 12 P5 5 /A 13 P5 6 /A 14 P5 7 /A 15 P6 0 /IRQ 2 /A 16 P6 1 /PW 1 /IRQ 3 /A 17 P6 2 /PW 2 /IRQ 4 /A 18 Index Index H8/534 HD CG JAPAN H8/536 HD CG JAPAN Figure 1-3 Pin Arrangement (CG-84, Top View) 7

29 P2 0 /AS P1 7 /TMO P1 6 /IRQ 1 /ADTRG P1 5 /IRQ 0 P1 4 /WAIT P1 3 /BREQ P1 2 /BACK P1 1 /E P1 0 /ø V ss XTAL EXTAL P9 7 /SCK 1 P9 6 /RXD 1 P9 5 /TXD 1 P9 4 /SCK 2 /PW 3 P9 3 /RXD 2 /PW 2 P9 2 /TXD 2 /PW 1 P9 1 /FTOA 3 P9 0 /FTOA 2 P2 1 /R/W P2 2/DS P2 3 /RD P2 4/WR V cc MD 0 MD 1 MD 2 STBY RES NMI V ss P3 0/D 0 P3 1/D 1 P3 2/D 2 P3 3/D 3 P3 4/D 4 P3 5/D 5 P3 6/D 6 P3 7/D QFP-80A TQFP-80C AVcc P8 7 /AN7 P8 6 /AN6 P8 5 /AN5 P8 4 /AN4 P8 3 /AN3 P8 2 /AN2 P8 1 /AN1 P8 0 /AN0 AVss P7 7 /FTOA1 P7 6 /FTOB 3/FTCI 3 P7 5 /FTOB 2/FTCI 2 P7 4 /FTOB 1/FTCI 1 P7 3 /FTI 3/TMRI P7 2 /FTI 2 P7 1 /FTI1 P7 0 /TMCI Vcc P6 3 /PW 3 /IRQ 5/A H8/534 HD TF JAPAN ss P4 0 /A P4 1 /A P4 2 /A P4 3 /A P4 4 /A P4 5 /A P4 6 /A P4 7 /A V TQFP-80C H8/536 HD TF JAPAN P5 0 /A 8 P5 1 /A 9 P5 2 /A 10 P5 3 /A 11 P5 4 /A 12 P5 5 /A 13 P5 6 /A 14 P5 7 /A 15 P6 0 /IRQ 2 /A 16 P6 1 /PW 1 /IRQ 3 /A 17 P6 2 /PW 2 /IRQ 4 /A 18 H8/534 HD F JAPAN QFP-80A H8/536 HD F JAPAN Pin 1 Pin 1 Pin 1 Pin 1 Figure 1-4 Pin Arrangement (FP-80A, TFP-80C, Top View) 8

30 1.3.2 Pin Functions Pin Arrangements in Each Operating Mode: Table 1-2 lists the arrangements of the pins of the CP-84 and CG-84 packages in each operating mode. Table 1-3 lists the arrangements for the FP-80A package. Table 1-2 Pin Arrangements in Each Operating Mode (CP-84, CG-84) Pin Name Expanded Minimum Expanded Maximum Single-Chip PROM Pin Modes Modes Mode Mode No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 H8/534 H8/536 1 XTAL XTAL XTAL XTAL XTAL NC NC 2 VSS VSS VSS VSS VSS VSS VSS 3 P10/ø P10/ø P10/ø P10/ø P10/ø NC NC 4 P11/E P11/E P11/E P11/E P11/E NC NC 5 P12 / BACK P12 / BACK P12 / BACK P12 / BACK P12 NC NC 6 P13 / BREQ P13 / BREQ P13 / BREQ P13 / BREQ P13 NC NC 7 P14 / WAIT P14 / WAIT P14 / WAIT P14 / WAIT P14 NC A15 8 P15 / IRQ0 P15 / IRQ0 P15 / IRQ0 P15 / IRQ0 P15 / IRQ0 NC A16 9 P16 / IRQ1 / P16 / IRQ1 / P16 / IRQ1 / P16 / IRQ1 / P16 / IRQ1 / NC PGM ADTRG ADTRG ADTRG ADTRG ADTRG 10 P17 / TMO P17 / TMO P17 / TMO P17 / TMO P17 / TMO NC NC 11 AS AS AS AS P20 NC NC 12 R/W R/W R/W R/W P21 NC NC 13 DS DS DS DS P22 NC NC 14 RD RD RD RD P23 NC NC 15 WR WR WR WR P24 NC NC 16 VCC VCC VCC VCC VCC VCC VCC 17 MD0 MD0 MD0 MD0 MD0 VSS VSS 18 MD1 MD1 MD1 MD1 MD1 VSS VSS Notes: 1. For the PROM mode, see section 17, ROM. 2. Pins marked NC should be left unconnected. 9

31 Table 1-2 Pin Arrangements in Each Operating Mode (CP-84, CG-84) (cont) Pin Name Expanded Minimum Expanded Maximum Single-Chip PROM Pin Modes Modes Mode Mode No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 H8/534 H8/ MD2 MD2 MD2 MD2 MD2 VSS VSS 20 STBY STBY STBY STBY STBY VSS VSS 21 RES RES RES RES RES VPP VPP 22 NMI NMI NMI NMI NMI A9 A9 23 NC NC NC NC NC NC NC 24 VSS VSS VSS VSS VSS VSS VSS 25 D0 D0 D0 D0 P30 O0 O0 26 D1 D1 D1 D1 P31 O1 O1 27 D2 D2 D2 D2 P32 O2 O2 28 D3 D3 D3 D3 P33 O3 O3 29 D4 D4 D4 D4 P34 O4 O4 30 D5 D5 D5 D5 P35 O5 O5 31 D6 D6 D6 D6 P36 O6 O6 32 D7 D7 D7 D7 P37 O7 O7 33 A0 A0 A0 A0 P40 A0 A0 34 A1 A1 A1 A1 P41 A1 A1 35 A2 A2 A2 A2 P42 A2 A2 36 A3 A3 A3 A3 P43 A3 A3 37 A4 A4 A4 A4 P44 A4 A4 38 A5 A5 A5 A5 P45 A5 A5 39 A6 A6 A6 A6 P46 A6 A6 40 A7 A7 A7 A7 P47 A7 A7 41 VSS VSS VSS VSS VSS VSS VSS Notes: 1. For the PROM mode, see section 17, ROM. 2. Pins marked NC should be left unconnected. 10

32 Table 1-2 Pin Arrangements in Each Operating Mode (CP-84, CG-84) (cont) Pin Name Expanded Minimum Expanded Maximum Single-Chip PROM Pin Modes Modes Mode Mode No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 H8/534 H8/ VSS VSS VSS VSS VSS VSS VSS 43 A8 P50 / A8 A8 P50 / A8 P50 A8 A8 44 A9 P51 / A9 A9 P51 / A9 P51 OE OE 45 A10 P52 / A10 A10 P52 / A10 P52 A10 A10 46 A11 P53 / A11 A11 P53 / A11 P53 A11 A11 47 A12 P54 / A12 A12 P54 / A12 P54 A12 A12 48 A13 P55 / A13 A13 P55 / A13 P55 A13 A13 49 A14 P56 / A14 A14 P56 / A14 P56 A14 A14 50 A15 P57 / A15 A15 P57 / A15 P57 CE CE 51 P60 / IRQ2 P60 / IRQ2 A16 P60 / IRQ2 / P60 / IRQ2 VCC VCC 52 P61 / PW1 / P61 / PW1 / A17 P61 / IRQ3 / P61 / PW1 / VCC VCC IRQ3 IRQ3 A17 IRQ3 53 P62 / PW2 / P62 / PW2 / A18 P62 / IRQ4 / P62 / PW2 / NC NC IRQ4 IRQ4 A18 IRQ4 54 P63 / PW3 / P63 / PW3 / A19 P63 / IRQ5 / P63 / PW3 / NC NC A16 IRQ5 IRQ5 A19 IRQ5 55 VCC VCC VCC VCC VCC VCC VCC 56 P70 / TMCI P70 / TMCI P70 / TMCI P70 / TMCI P70 / TMCI NC NC 57 P71 / FTI1 P71 / FTI1 P71 / FTI1 P71 / FTI1 P71 / FTI1 NC NC 58 P72 / FTI2 P72 / FTI2 P72 / FTI2 P72 / FTI2 P72 / FTI2 NC NC 59 P73 / FTI3 / P73 / FTI3 / P73 / FTI3 / P73 / FTI3 / P73 / FTI3 / NC NC TMRI TMRI TMRI TMRI TMRI 60 P74 / FTOB1 / P74 / FTOB1 / P74 / FTOB1 / P74 / FTOB1 / P74 / FTOB1 / NC NC FTCI1 FTCI1 FTCI1 FTCI1 FTCI1 61 P75 / FTOB2 / P75 / FTOB2 / P75 / FTOB2 / P75 / FTOB2 / P75 / FTOB2 / NC NC FTCI2 FTCI2 FTCI2 FTCI2 FTCI2 Notes: 1. For the PROM mode, see section 17, ROM. 2. Pins marked NC should be left unconnected. 11

33 Table 1-2 Pin Arrangements in Each Operating Mode (CP-84, CG-84) (cont) Pin Name Expanded Minimum Expanded Maximum Single-Chip PROM Pin Modes Modes Mode Mode No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 H8/534 H8/ P76 / FTOB3 / P76 / FTOB3 / P76 / FTOB3 / P76 / FTOB3 / P76/ FTOB3 / NC NC FTCI3 FTCI3 FTCI3 FTCI3 FTCI3 63 P77 / FTOA1 P77 / FTOA1 P77 / FTOA1 P77 / FTOA1 P77 / FTOA1 NC NC 64 VSS VSS VSS VSS VSS VSS VSS 65 AVSS AVSS AVSS AVSS AVSS VSS VSS 66 P80 / AN0 P80 / AN0 P80 / AN0 P80 / AN0 P80 / AN0 NC NC 67 P81 / AN1 P81 / AN1 P81 / AN1 P81 / AN1 P81 / AN1 NC NC 68 P82 / AN2 P82 / AN2 P82 / AN2 P82 / AN2 P82 / AN2 NC NC 69 P83 / AN3 P83 / AN3 P83 / AN3 P83 / AN3 P83 / AN3 NC NC 70 P84 / AN4 P84 / AN4 P84 / AN4 P84 / AN4 P84 / AN4 NC NC 71 P85 / AN5 P85 / AN5 P85 / AN5 P85 / AN5 P85 / AN5 NC NC 72 P86 / AN6 P86 / AN6 P86 / AN6 P86 / AN6 P86 / AN6 NC NC 73 P87 / AN7 P87 / AN7 P87 / AN7 P87 / AN7 P87 / AN7 NC NC 74 AVCC AVCC AVCC AVCC AVCC VCC VCC 75 P90 / FTOA2 P90 / FTOA2 P90 / FTOA2 P90 / FTOA2 P90 / FTOA2 NC NC 76 P91 / FTOA3 P91 / FTOA3 P91 / FTOA3 P91 / FTOA3 P91 / FTOA3 NC NC 77 P92 / TXD2 / P92 / TXD2 / P92 / TXD2 / P92 / TXD2 / P92 / TXD2 / NC NC PW1 PW1 PW1 PW1 PW1 78 P93 / RXD2 / P93 / RXD2 / P93 / RXD2 / P93 / RXD2 / P93 / RXD2 / NC NC PW2 PW2 PW2 PW2 PW2 79 P94 / SCK2 / P94 / SCK2 / P94 / SCK2 / P94 / SCK2 / P94 / SCK2 / NC NC PW3 PW3 PW3 PW3 PW3 80 P95 / TXD1 P95 / TXD1 P95 / TXD1 P95 / TXD1 P95 / TXD1 NC NC 81 P96 / RXD1 P96 / RXD1 P96 / RXD1 P96 / RXD1 P96 / RXD1 NC NC 82 P97 / SCK1 P97 / SCK1 P97 / SCK1 P97 / SCK1 P97 / SCK1 NC NC 83 VSS VSS VSS VSS VSS VSS VSS 84 EXTAL EXTAL EXTAL EXTAL EXTAL NC NC Notes: 1. For the PROM mode, see section 17, ROM. 2. Pins marked NC should be left unconnected. 12

34 Table 1-3 Pin Arrangements in Each Operating Mode (FP-80A, TFP-80C) Pin Name Expanded Minimum Expanded Maximum Single-Chip PROM Pin Modes Modes Mode Mode No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 H8/534 H8/536 1 R/W R/W R/W R/W P21 NC NC 2 DS DS DS DS P22 NC NC 3 RD RD RD RD P23 NC NC 4 WR WR WR WR P24 NC NC 5 VCC VCC VCC VCC VCC VCC VCC 6 MD0 MD0 MD0 MD0 MD0 VSS VSS 7 MD1 MD1 MD1 MD1 MD1 VSS VSS 8 MD2 MD2 MD2 MD2 MD2 VSS VSS 9 STBY STBY STBY STBY STBY VSS VSS 10 RES RES RES RES RES VPP VPP 11 NMI NMI NMI NMI NMI A9 A9 12 VSS VSS VSS VSS VSS VSS VSS 13 D0 D0 D0 D0 P30 O0 O0 14 D1 D1 D1 D1 P31 O1 O1 15 D2 D2 D2 D2 P32 O2 O2 16 D3 D3 D3 D3 P33 O3 O3 17 D4 D4 D4 D4 P34 O4 O4 18 D5 D5 D5 D5 P35 O5 O5 19 D6 D6 D6 D6 P36 O6 O6 20 D7 D7 D7 D7 P37 O7 O7 21 A0 A0 A0 A0 P40 A0 A0 Notes: 1. For the PROM mode, see section 17, ROM. 2. Pins marked NC should be left unconnected. 13

35 Table 1-3 Pin Arrangements in Each Operating Mode (FP-80A, TFP-80C) (cont) Pin Name Expanded Minimum Expanded Maximum Single-Chip PROM Pin Modes Modes Mode Mode No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 H8/534 H8/ A1 A1 A1 A1 P41 A1 A1 23 A2 A2 A2 A2 P42 A2 A2 24 A3 A3 A3 A3 P43 A3 A3 25 A4 A4 A4 A4 P44 A4 A4 26 A5 A5 A5 A5 P45 A5 A5 27 A6 A6 A6 A6 P46 A6 A6 28 A7 A7 A7 A7 P47 A7 A7 29 VSS VSS VSS VSS VSS VSS VSS 30 A8 P50 / A8 A8 P50/ A8 P50 A8 A8 31 A9 P51 / A9 A9 P51/ A9 P51 OE OE 32 A10 P52 / A10 A10 P52/ A10 P52 A10 A10 33 A11 P53 / A11 A11 P53 / A11 P53 A11 A11 34 A12 P54 / A12 A12 P54 / A12 P54 A12 A12 35 A13 P55 / A13 A13 P55 / A13 P55 A13 A13 36 A14 P56 / A14 A14 P56 / A14 P56 A14 A14 37 A15 P57 / A15 A15 P57 / A15 P57 CE CE 38 P60 / IRQ2 P60 / IRQ2 A16 P60 / IRQ2 / P60 / IRQ2 VCC VCC 39 P61 / PW1 / P61 / PW1 / A17 P61 / IRQ3 / P61 / PW1 / VCC VCC IRQ3 IRQ3 A17 IRQ3 40 P62 / PW2 / P62 / PW2 / A18 P62 / IRQ4 / P62 / PW2 / NC NC IRQ4 IRQ4 A18 IRQ4 41 P63 / PW3 / P63 / PW3 / A19 P63 / IRQ5 / P63 / PW3 / NC NC A16 IRQ5 IRQ5 A19 IRQ5 42 VCC VCC VCC VCC VCC VCC VCC Notes: 1. For the PROM mode, see section 17, ROM. 2. Pins marked NC should be left unconnected. 14

36 Table 1-3 Pin Arrangements in Each Operating Mode (FP-80A, TFP-80C) (cont) Pin Name Expanded Minimum Expanded Maximum Single-Chip PROM Pin Modes Modes Mode Mode No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 H8/534 H8/ P70 / TMCI P70/ TMCI P70/ TMCI P70/ TMCI P70/ TMCI NC NC 44 P71 / FTI1 P71/ FTI1 P71/ FTI1 P71/ FTI1 P71/ FTI1 NC NC 45 P72 / FTI2 P72 / FTI2 P72 / FTI2 P72 / FTI2 P72 / FTI2 NC NC 46 P73 / FTI3 / P73 / FTI3 / P73 / FTI3 / P73 / FTI3 / P73 / FTI3 / NC NC TMRI TMRI TMRI TMRI TMRI 47 P74 / FTOB1 / P74 / FTOB1 / P74 / FTOB1 / P74/ FTOB1 / P74 / FTOB1 / NC NC FTCI1 FTCI1 FTCI1 FTCI1 FTCI1 48 P75 / FTOB2 / P75 / FTOB2 / P75 / FTOB2 / P75 / FTOB2 / P75 / FTOB2 / NC NC FTCI2 FTCI2 FTCI2 FTCI2 FTCI2 49 P76 / FTOB3 / P76 / FTOB3 / P76 / FTOB3 / P76 / FTOB3 / P76 / FTOB3 / NC NC FTCI3 FTCI3 FTCI3 FTCI3 FTCI3 50 P77 / FTOA1 P77 / FTOA1 P77 / FTOA1 P77 / FTOA1 P77 / FTOA1 NC NC 51 AVSS AVSS AVSS AVSS AVSS VSS VSS 52 P80 / AN0 P80 / AN0 P80 / AN0 P80 / AN0 P80 / AN0 NC NC 53 P81 / AN1 P81 / AN1 P81 / AN1 P81 / AN1 P81 / AN1 NC NC 54 P82 / AN2 P82 / AN2 P82 / AN2 P82 / AN2 P82 / AN2 NC NC 55 P83 / AN3 P83 / AN3 P83 / AN3 P83 / AN3 P83 / AN3 NC NC 56 P84 / AN4 P84 / AN4 P84 / AN4 P84 / AN4 P84 / AN4 NC NC 57 P85 / AN5 P85 / AN5 P85 / AN5 P85 / AN5 P85 / AN5 NC NC 58 P86 / AN6 P86 / AN6 P86 / AN6 P86 / AN6 P86 / AN6 NC NC 59 P87 / AN7 P87 / AN7 P87 / AN7 P87 / AN7 P87 / AN7 NC NC Notes: 1. For the PROM mode, see section 17, ROM. 2. Pins marked NC should be left unconnected. 15

37 Table 1-3 Pin Arrangements in Each Operating Mode (FP-80A, TFP-80C) (cont) Pin Name Expanded Minimum Expanded Maximum Single-Chip PROM Pin Modes Modes Mode Mode No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 H8/534 H8/ AVCC AVCC AVCC AVCC AVCC VCC VCC 61 P90 / FTOA2 P90 / FTOA2 P90 / FTOA2 P90 / FTOA2 P90 / FTOA2 NC NC 62 P91 / FTOA3 P91 / FTOA3 P91 / FTOA3 P91 / FTOA3 P91 / FTOA3 NC NC 63 P92 / PW1 P92 / PW1 P92 / PW1 P92 / PW1 P92 / PW1 NC NC 64 P93 / PW2 P93 / PW2 P93 / PW2 P93 / PW2 P93 / PW2 NC NC 65 P94 / PW3 P94 / PW3 P94 / PW3 P94 / PW3 P94 / PW3 NC NC 66 P95 / TXD P95 / TXD P95 / TXD P95 / TXD P95 / TXD NC NC 67 P96 / RXD P96 / RXD P96 / RXD P96 / RXD P96 / RXD NC NC 68 P97 / SCK P97 / SCK P97 / SCK P97 / SCK P97 / SCK NC NC 69 EXTAL EXTAL EXTAL EXTAL EXTAL NC NC 70 XTAL XTAL XTAL XTAL XTAL NC NC 71 VSS VSS VSS VSS VSS VSS VSS 72 P10 / ø P10 / ø P10 / ø P10 / ø P10 / ø NC NC 73 P11 / E P11 / E P11 / E P11 / E P11 / E NC NC 74 P12 / BACK P12 / BACK P12 / BACK P12 / BACK P12 NC NC 75 P13 / BREQ P13 / BREQ P13 / BREQ P13 / BREQ P13 NC NC 76 P14 / WAIT P14 / WAIT P14 / WAIT P14 / WAIT P14 NC A15 77 P15 / IRQ0 P15 / IRQ0 P15 / IRQ0 P15 / IRQ0 P15 / IRQ0 NC A16 78 P16 / IRQ1 / P16 / IRQ1 / P16 / IRQ1 / P16 / IRQ1 / P16 / IRQ1 / NC PGM ADTRG ADTRG ADTRG ADTRG ADTRG 79 P17 / TMO P17 / TMO P17 / TMO P17 / TMO P17 / TMO NC NC 80 AS AS AS AS P20 NC NC Notes: 1. For the PROM mode, see section 17, ROM. 2. Pins marked NC should be left unconnected. 16