FPGA PLB EVALUATION USING QUANTIFIED BOOLEAN SATISFIABILITY

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1 FPGA PLB EVALUATION USING QUANTIFIED BOOLEAN SATISFIABILITY Andrew C. Ling Electrical and Computer Engineering University o Toronto Toronto, CANADA aling@eecg.toronto.edu Deshanand P. Singh, Stephen D. Brown Altera Corporation Toronto Technology Centre Toronto, CANADA dsingh sbrown@altera.com ABSTRACT This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines i a logic unction can be implemented in a given programmable circuit and describes how this problem can be ormalized and solved using Quantiied Boolean Satisiability. This technique is general enough to be applied to any type o logic unction and programmable circuit; thus, it has many applications to FPGAs. The application demonstrated in this paper is FPGA PLB evaluation where their results show that this tool allows radical new eatures o FPGA logic blocks to be evaluated in a rigorous scientiic way. 1. INTRODUCTION FPGAs are integrated circuits characterized by a sea o programmable logic blocks (PLBs). Coniguration IN Coniguration OUT LUT 16:1 D Q A B C D R Reset Clock LE Out Fig. 1. A simpliied FPGA PLB. An example o a PLB is shown in Fig. 1. The logic block is composed o a 4-input lookup table (4-LUT) that is capable o implementing any arbitrary Boolean unction o 4 variables. The LUT is implemented with a set o 2 4 = 16 static RAM (SRAM) bits that are programmed with the truth-table values or the unction to be implemented. In general, many modern PLBs are based on the k-input lookup table (k-lut) which contains 2 k SRAM bits. Although the k-input LUT is very lexible, it is usually beneicial to add dedicated non-programmable logic to the PLB such as adders and XOR/AND-gates [1, 2]. These eatures increase the number o unctions that can be implemented by a PLB without the power, speed, and area costs associated with programmable logic. However, because this reduces the lexibility o the PLB, optimal mapping o unctions to these non-programmable components is diicult Motivation The cost o implementing a circuit in an FPGA is directly proportional to the number o PLBs required to implement the unctionality o the circuit. FPGAs are sold in a number o pre-abricated sizes. Decreasing the number o PLBs may allow a circuit to be realized in a smaller FPGA. Typical pricing is roughly linear to the number o PLBs in the FPGA device [3]. The PLB architecture has a signiicant impact on the number o PLBs required to realize a particular circuit. Thus, clever PLB designs are necessary that capture the majority o the unctions encountered in typical circuits. In this paper we will show how methods based on Quantiied Boolean Satisiability can be used to rapidly determine i a PLB architecture will achieve a high capture rate. 2. BACKGROUND 3. TECHNOLOGY MAPPING The technology mapping step in the FPGA CAD low converts a gate-level network consisting o primitive gates into the PLBs that are present in the target FPGA architecture. The goal o the technology mapping step is to reduce area, delay, or a combination thereo in the network o PLBs that is produced. In this work, delay is proportional to the depth o a circuit where the depth o a node is deined as the longest path rom the node to a primary input. Previous work showed that the depth-optimal mapping solution can be obtained in

2 polynomial time using a dynamic programming procedure [4]. a b x c d e a b x c d e a b c d e L 1 L 2 L 3 L LUT AND-GATE M N Vcc L 5 x 1 x 2 x 3 Fig. 3. Example PLB. g (a) Initial Netlist (b) Possible Covering (c) LUT Mapping Fig. 2. Technology mapping as a covering problem. The process o technology mapping is oten treated as a covering problem. For example, consider the process o mapping a circuit into LUTs as illustrated in Fig. 2. Fig. 2a illustrates the initial gate level network, Fig. 2b illustrates a possible covering o the initial network using 4-LUTs, and Fig. 2c illustrates the LUT network produced by the covering. In the mapping given, the gate labeled x is covered by both LUTs and is said to be duplicated. In a duplicationree mapping, each gate in the initial circuit is covered by a single LUT in the mapped circuit [5]. However, surprisingly, the controlled use o duplication can lead to urther area savings [6]. In contrast to the depth minimization problem, the area minimization problem was shown to be NPhard or LUTs o size our and greater [7]. Thus, heuristics are necessary to solve the area minimization problem. Another way to look at technology mapping is as a cone selection problem. The subcircuits circled in Fig. 2b are examples o cones. Technology mapping seeks to ind the best set o cones that can be mapped to the current PLB architecture. Best is determined by the optimizing goal such as area, speed, or power. I the FPGA architecture consists solely o K-LUTs, mapping rom cones to K-LUTs is a direct process since any cone with K-inputs or less can be implemented in a K-LUT. A cone with K-inputs or less is known to be K-easible. Thus, to technology map circuits to K-LUTs, the circuit simply has to be decomposed into a set o K-easible cones. However, i the FPGA architecture consists o generic K-input PLBs, mapping rom cones to PLBs is much more diicult since PLBs cannot implement all possible K-easible cones. For example, the PLB shown in Fig. 3 cannot implement a 3-input OR gate. Although more limited in unctionality, PLBs oer speed, area, and power advantages over ully programmable K- LUTs. Furthermore, in general only a small subset o K- easible cones will appear in most logic circuits. Thus, so long as a given PLB architecture can capture most cones encountered in real circuits, it will be successul in implement- g g ing circuits. One way to determine i a PLB will capture most K-easible cones ound in circuits is to extract a set o K-easible cones rom a set o circuits and determine how many o these cones can it into a given PLB where a high it percentage is desired. The tool presented in this paper does this exact task, which will be described in Sec Quantiied SAT As stated in Sec. 1, the main contribution o this work is to examine the use o Quantiied Boolean Satisiability (QSAT) or use in PLB evaluation. QSAT is the problem o determining i a quantiied Boolean ormula (QBF), F = Q 1 x 1...Q n x n (x 1...x n ) where Q i {, }, has an assignment to its variables, x 1...x n, such that F evaluates to true. I so, F is said to be satisiable, otherwise it is unsatisiable. This is analogous to the much simplier problem o Boolean Satisiability (SAT) where SAT seeks a single assignment to a Boolean ormula F such that F evaluates to true. SAT is actually a special case o QSAT where SAT deals with Boolean ormulae without any universal quantiiers (variables in Boolean ormulae without any quantiiers implicitly have a single existential quantiier bound to them). QSAT, however, may have universally quantiied variables, and thus seeks all assignments to its universally quantiied variables to satisy a QBF. For example, consider the expressions in Equ. 1. The irst expression shows a satisiable Boolean ormula with its associated satisying assignment. In contrast, simply by adding quantiiers to it, the QBF shown in the second expression is unsatisiable due to the universally quantiied variable x 2. (x 1 + x 2 ) (x 1 + x 2 ) satisiable [x 1 = 0, x 2 = 1] x 1 x 2 (x 1 + x 2 ) (x 1 + x 2 ) unsatisiable [x 1 = 0, x 2 = {0, 1}] unsatisiable [x 1 = 1, x 2 = {0, 1}] For all practical purposes, QSAT only deals with QBFs in Conjunctive-Normal-Form (CNF, sometimes reerred as (1)

3 a Product-o-Sums). A Boolean unction is in CNF i it consists solely o a conjunction o clauses, where a clause is a disjunction o literals and a literal is any variable or its complement. Equ. 1 are examples o ormulae in CNF. In CNF, the problem o QSAT can be rephrased to: Given a QBF, F = Q 1 x 1...Q n x n (x 1...x n ) where Q i {, }, ind an assignment to its variables, x 1...x n, such that each clause in (x 1...x n ) has at least one literal that evaluates to true. 4. QUANTIFIED SAT APPLIED TO PLB EVALUATION The goal o PLB evaluation is to determine how useul a new PLB architecture will be in implementing circuits. A useul k-input PLB can be characterized by how many k- input cones can it into it where a high it percentage is desired. Thus, the underlying question asked when determining this it percentage is as ollows: Given an n-variable Boolean unction, F unction (x 1, x 2,..., x n ), does there exist a programmable coniguration to a circuit, G, such that the output o the circuit will equal F unction (x 1, x 2,..., x n ) or all inputs? Previously, robust heuristics to answer this question ell into two categories: a specialized PLB is proposed and a customized mapping algorithm is implemented to map benchmark circuits using the proposed element [8]; specialized Boolean matching techniques are developed to decompose a logic unction in such a way so that it matches the structure o the proposed PLB [9]. Both o these techniques suer a lack o generality, which we address in our novel QSAT based approach Formalizing Function Fitting Problem Assuming that a programmable circuit can be represented as a Boolean unction G circuit = G(x 1..x n, L 1..L m, z 1..z o ) where x i, L j, z k, G circuit represent the input signals, coniguration bits, intermediate circuit signals, and output unction o the circuit respectively, the problem o unction mapping into programmable logic can represented ormally as a QBF as ollows. L 1...L m x 1...x n z 1...z o (G circuit F unction ) (2) A satisying assignment to Equ. 2 implies that F unction can be realized in the programmable circuit. In order to derive Equ. 2, the proposition (G circuit F unction ) must be represented as a CNF Boolean ormula. This can be done using a well known derivation technique that converts logic circuits into a characteristic unction in CNF [10]. This characteristic unction describes all valid inputs, output, coniguration bits, and internal signal vectors or the conigurable circuit. For example, consider the truth-table in Fig. 4. Its onset describes all input-output relations o an AND gate. To extract the characteristic unction, A B Z F AND A B F AND = (A + Z) (B + Z) (A + B + Z) A B Z F CASCADE = (A + Z) (B + Z) (A + B + Z) (Z + Y ) (C + Y ) (Z + C + Y ) Fig. 4. Deriving a circuit characteristic unction. F AND, rom the truth-table, any standard minimization technique can be used. Deriving characteristic unctions directly rom the circuit input-output relation is only practical or primitive gates and logic blocks where the number o inputs and outputs is small. Fortunately, characteristic unctions or larger circuits can be derived iteratively rom the conjunction o its subcircuit characteristic unctions. For example, consider the cascaded gates shown in Fig. 4. Notice the wire connecting the two gates is labeled with variable Z or CNF construction. The characteristic unction o the cascaded circuit is simply the conjunction o the two AND gate characteristic unctions with variable Z as the logical link between the two unctions. The characteristic unction, F CASCADE evaluates to true i all wire signals are consistent. This includes the primary inputs and outputs as in F AND, plus any intermediate wire signals (i.e. Z). The previous conversion technique or the cascaded AND structure can be extended to much larger circuits such as PLBs. This creates a characteristic unction, Ψ, dependent on variables x 1,..., x n, L 1,..., L m, z 1,..., z o, and G which represent the inputs, programmable bits, intermediate wires, and output o the circuit respectively. Thus, the proposition (G circuit F unction ) can be ormed by substituting all instances o the output variable G in Ψ by the expression representing F unction. This is shown in Equ. 3 where the notation [G/F (x 1,..., x n )] indicates that all instances o G have been replaced by F (x 1,...x n ). Sections ollowing this will use similar notation to represent the substitution opera- C Z Y

4 tion. [G circuit F unction ] Ψ [G/F (x 1,..., x n )] L 1...L m x 1...x n z 1...z o ψ [G/F (x 1,..., x n )] 4.2. Removing Quantiied Variables Although QSAT solvers have shown initial promising results, it is oten still aster to solve a QBF by removing the universal quantiiers and converting it to a SAT problem [11]. Removing the universal quantiiers eliminates the need to ind multiple SAT instances or all universally quantiied variable assignments, thus saving time; however, in doing so, the size o the Boolean ormula increases substantially. To remove the universal quantiiers in a QBF, F, its proposition,, is replicated to explicitly enumerate all possible assignments o the universally quantiied variables. These replicated ormulae are then conjoined with the logical AND operator to orm a Boolean unction that can be solved with SAT. In order to give better understanding to the previously described ideas, an example is given. Assume that a 3-input unction F needs to be implemented in the PLB shown previously in Fig. 3. In the ollowing steps,f represents the unction o the cone under consideration or mapping, X represents input vector x 1 x 2 x 3 = i, and F i = F (X ). Step 1: Create CNF or individual elements in programmable circuit. G LUT = (x 1 + x 2 + L 1 + z 1) (x 1 + x 2 + L 1 + z 1) (x 1 + x 2 + L 2 + z 1) (x 1 + x 2 + L 2 + z 1) (x 1 + x 2 + L 3 + z 1) (x 1 + x 2 + L 3 + z 1) (x 1 + x 2 + L 4 + z 1) (x 1 + x 2 + L 4 + z 1) (3) G MUX = (L 5 + x 3 + z 2) (L 5 + x 3 + z 2) (L 5 + z 2) (5) G AND = (z 1 + G) (z 2 + G) (z 1 + z 2 + G) (6) Step 2: Formulate the programmable circuit CNF rom equations 4, 5, and 6. (4) G circuit = G LUT G MUX G AND (7) Step 3: Replication o equation 7 to remove quantiied variables. This ormulates G T otal where a satisiable assignment to G T otal implies F can be realized in the programmable circuit. Note that in equation 8, the coniguration bits are represented by the same variables (L 1 5 ) in each G circuit (X, i ) instance, where as all other signals are unique variables in each instance. This ensures that only one coniguration will exist or all entries o the truth table. In the previous example, the pins on the programmable circuit in Fig. 3 are not permutable. Given the labeling convention in Fig. 3, the unction F = (x 1 + x 2 ) x 3 can be implemented; however, the unction F = (x 1 + x 3 ) x 2 cannot. There is no need or restricting the labeling o the input pins in this manner because most programmable circuits are able to route signals to any input pins. In order to model this lexibility, virtual multiplexers controlled by virtual coniguration bits, V p, are added at each input pin o the programmable circuit. Going back to the circuit shown in the last example, Fig. 5 illustrates the previous circuit with virtual multiplexers added at the input pins. Thus, i F = (x 1 +x 3 ) x 2 is to be mapped into this network then the virtual multiplexers would orce x 1 and x 3 onto the irst two pins o the circuit and x 2 to the third pin eeding the AND gate to generate a satisiable solution. In order to add the virtual multiplexers to the previous example, the virtual multiplexer characteristic unctions need to be added in Step 1, then the the process proceeds normally as previously shown. L 1 L 2 L 3 L LUT AND-GATE M 0 1 L 5 Vcc V 1, V 2, V 3 V 7, V 8, V 9 x x 1 2 x 3 V 5, V 6, V 7 Fig. 5. An example PLB with virtual multiplexers added. N G T otal = G circuit[ / 0, G/F 0, z 1/z 3, z 2/z 4] G circuit[ / 1, G/F 1, z 1/z 5, z 2/z 6] G circuit[ / 2, G/F 2, z 1/z 7, z 2/z 8] G circuit[ / 3, G/F 3, z 1/z 9, z 2/z 10] G circuit[ / 4, G/F 4, z 1/z 11, z 2/z 12] G circuit[ / 5, G/F 5, z 1/z 13, z 2/z 14] G circuit[ / 6, G/F 6, z 1/z 15, z 2/z 16] G circuit[ / 7, G/F 7, z 1/z 17, z 2/z 18] (8) 4.3. Application to PLB Evaluation PLB Evaluate 1 X GENERATECONES() 2 Y REMOVENOFITCONES() 3 F itp ercent (X Y )/X Fig. 6. An overview o the PLB evaluation algorithm.

5 Fig. 6 shows a high-level overview o our PLB evaluation algorithm. As stated previously, PLBs that can capture the unctionality o most cones ound in real circuits are desired since their non-programmable components will not be wasted. In order to help ind such PLBs, our tool can be used to return a PLB cone it percentage where a high it percentage is preerred. This it percentage is ound by taking extracting a set o cones rom a list o circuits (Fig. 6, line 1), then applying our QSAT decision step to remove cones that do not it in the given architecture (Fig. 6, line 2). By recording the number o cones generated and discared, a it percentage or various PLB architectures can be ound (Fig. 6, line 3). A version o the algorithm described in [6] is used to generate and store all K-easible cones in the graph. The K-easible cones are generated as the graph is traversed in topological order rom primary inputs to primary outputs. At every internal node v, new cones are generated by combining the cones at the input nodes. 5. RESULTS 5.1. Evaluation o Various PLBs To show the power o the PLB evaluation algorithm, several unrelated PLB architectures were evaluated. Fig. 7 shows the ive dierent PLB architectures used or evaluation. Circuit a b c d e C ex5p clma dalu des i x m misex mm30a mult16b % Fit Table 1. PLB it results. Conig Bits SAT (sec) QBF (sec) Table 2. SAT and QBF solver running times. (a)! "$#&% (b) '!( )$*&+ the total percentage o all cones that it. Note that the cone it percentage varies wildly or all PLBs depending on the circuit. This shows that PLB useulness is dependent on the application o the circuit. Interestingly, PLB (b) ailed or all circuits except the ALU circuit (C2670). A reason or this is because PLB (b) uses an XOR gate and XOR gates are very rare in most control circuits and are generally used or arithmetic logic.! "$#&% '!( )$*& QBF vs. SAT (c) (d) Fig. 7. PLB architectures. To evaluate the versatility o each PLB, a set o cones were extracted rom a list o circuits taken rom the MCNC benchmark suite [12] (approximately 1000 K-input cones per circuit, where K was the input size o the PLB). These cones were tested or PLB itting using the Cha [13] SAT solver. The circuits used were unrelated to generate a large set o dissimilar cones. The table shown in Tab. 1 shows the PLB it percentage o cones per circuit. The last row shows (e) In order to show the power o removing quantiiers in our QBF to produce a SAT problem as shown in Sec. 4.2, we ran a ew cone itting examples using a QBF solver and a SAT solver. The example used a 7-input unction realized with a 7-input PLB consisting o two cascaded 4-LUTs. An unsatisiable unction was selected so the entire search space was explored. Furthermore, the coniguration bits were preconigured to vary the size o the search space. This is shown in Tab. 2. Conig Bits shows the number o unconigured programmable bits in the circuit; SAT shows the Cha SAT solver [13] running times on a Sunblade 150 with 2.5 GB o RAM; and QBF shows the Quale QBF solver [14] running times on the same machine.

6 6. CONCLUSION AND FUTURE WORK This work represents only the irst step in the search or the optimal FPGA PLB. Our research will progress in two distinct areas. The irst is hardware acceleration or the PLB evaluation tool. QSAT is P-Space complete and thus takes a large amount o computation time even with advanced heuristics. The use o specialized hardware acceleration circuitry should speed up our technology mapping time by an order o magnitude or more or very complex PLB structures. Our second area o research involves an automatic method o chosing the FPGA PLBs to explore. We are exploring a genetic algorithm that can create candidate PLBs rom primitive elements such as lookup tables, basic gates, multiplexers and adder structures. In addition to the presentation o QBF applications to FPGAs, we have shown this class o problem that arises in this work is very diicult or QBF solvers. In act, it seems that a naive translation to SAT is a ar better approach than the QBF representation. We hope to provide a number o benchmarks that will help to drive the development o an eicient QBF solver. 7. REFERENCES [1] Altera, Component selector guide ver 14.0, [2] Xilinx, Virtex-ii complete data sheet ver 3.3, [3] Arrow Electronics. [Online]. Available: [4] J. Cong and Y. Ding, An optimal technology mapping algorithm or delay optimization in lookup-table based FPGA designs, IEEE Transactions on Computer- Aided Design, vol. 13, no. 1, pp. 1 13, Jan [5], On area/depth trade-o in LUT-based FPGA technology mapping, in Design Automation Conerence, 1993, pp [Online]. Available: citeseer.ist.psu.edu/cong94areadepth.html [6] J. Cong, C. Wu, and Y. Ding, Cut ranking and pruning: enabling a general and eicient pga mapping solution, in Proceedings o the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays. ACM Press, 1999, pp [7] I. Levin and R. Y. Pinter, Realizing Expression Graphs using Table-Lookup FPGAs, in Proceedings o the European Design Automation Conerence, 1993, pp [8] A.Kaviani and S. Brown, The hybrid ield programmable architecture, IEEE Design and Test, pp , April June [9] J. Cong and Y.-Y. Hwang, Boolean matching or lutbased logic blocks with applications to architecture evaluation and technology mapping, IEEE Transactions on Computer-Aided Design, vol. 20, no. 9, pp , [10] T. Larrabee, Test Pattern Generation Using Boolean Satisiablity, IEEE Transactions on Computer-Aided Design, vol. 11, no. 1, pp. 6 22, [Online]. Available: citeseer.ist.psu.edu/larrabee92test.html [11] D. Tang, Y. Yu, D. P. Ranjan, and S. Malik, Analysis o search based algorithms or satisiability o quantiied boolean ormulas arising rom circuit state space diameter problems, in SAT 04: The Seventh International Conerence on Theory and Applications o Satisiability Testing, May 2004, pp [12] S. Yang, Logic synthesis and optimization benchmarks user guide version, [Online]. Available: citeseer.ist.psu.edu/yang91logic.html [13] M. W. Moskewicz, C. F. Madigan, Y. Zhao, L. Zhang, and S. Malik, Cha: Engineering an Eicient SAT Solver, in Proceedings o the 38th Design Automation Conerence (DAC 01), [Online]. Available: citeseer.ist.psu.edu/moskewicz01cha.html [14] L. Zhang and S. Malik, Conlict driven learning in a quantiied boolean satisiability solver, in ICCAD 02: Proceedings o the 2002 IEEE/ACM international conerence on Computer-aided design. ACM Press, 2002, pp