Logic Debugging of Arithmetic Circuits

Transcription

1 Logic Debugging o Arithmetic Circuits Samaneh Ghandali, Cunxi Yu, Duo Liu, Walter Brown, Maciej Ciesielski University o Massachusetts, Amherst, USA {samaneh, ycunxi, duo, webrown, ciesiel}@umass.edu Abstract This paper presents a novel diagnosis and logic debugging method or gate-level arithmetic circuits. It detects logic bugs in a synthesized circuit caused by using a wrong gate ( gate replacement error), which change the unctionality o the circuit. The method is based on modeling the circuit in an algebraic domain and computing its algebraic signature. The location and type o the bug is determined by comparing signatures computed in both directions, using orward (PI to PO) and backward (PO to PI) rewriting. It will also perorm automatic correction or the detected bugs. The approach is demonstrated and tested on a set o integer combinational arithmetic circuits. Keywords Formal veriication; Logic debugging; Arithmetic circuits. I. INTRODUCTION As today s VLSI designs grow in complexity and size, design errors become more requent and diicult to track []. The process o veriying the unctional correctness o a design, determining the source o potential errors and correcting those errors, can take up to 7% o the overall design time []. Recent developments have automated most o the veriication tasks, but debugging, i.e., error localization and correction, still remains a resource intensive, manually conducted process [4]. Eicient automated debugging techniques are necessary to complement and enhance the veriication techniques. Traditional automated debugging solutions or hardware designs are based on simulation, critical path tracing [5], BDDs and *BMDs [6]. Recent automated debugging methods tend to rely on SAT solvers. In [7] error detection is acilitated by adding corrector models to the circuit implementation and mapping it into a Boolean ormula in CNF. By solving the resulting SAT problem, a set o suspect error locations are obtained. This approach, however, is restricted by the perormance and capacity o the available SAT solvers. Other techniques, such as those based on Quantiied Boolean Formula (QBF) [8], abstraction and reinement in error localization [9], and maximum satisiability [], [], are used to improve SATbased debugging method. However, the perormance o these methods and their capability to handle large designs remain limited by SAT. In order to reduce the number o SAT solver calls, the concept o reverse dominators was introduced in [] to allow or early pruning o non-solution areas o the problem search space. FPGA-based debugging methodology, proposed in [], [4], [5], locally modiies the circuit structure. The diagnosis problem or sequential circuits is typically structured as bounded model checking (BMC) [6], [7] and ormulated as a SAT problem. In [7], resynthesis method guided by counterexamples perorms gate-level circuit repair, based on error traces composed o input vectors and output responses. The method described in [8],[9] introduces an abstraction and reinement algorithm or design debugging built upon a time-windowing ramework to manage excessive error trace lengths. Non-modeled portions o the trace are approximated using a path directed abstraction that represents structural circuit paths. Due to the inherent iterative nature o the algorithm, perormance remains the crucial issue in this work. A debugging technique applicable to divider circuits is proposed in []. It is based on a reverse-engineering mechanism o extracting a high level arithmetic model, called Functional Bit Level Adder (FBLA), which may be diicult to obtain in synthesized circuits. Furthermore, these methods can only reason about the correctness o the quotient part o the result using iterative subtraction model, but not about the entire divider circuit. In [] veriication o RTL code to optimize assertion coverage is proposed. Their algorithm can be used to isolate only those statements that are covered by an assertion as the most likely location o the bug. However, the problem o generating assertions remains open. In this paper, we introduce a novel diagnosis and logic debugging method or gate-level arithmetic circuits. The proposed method is part o the unctional veriication approach proposed in []. It detects the logical bugs, caused by using a wrong gate ( gate replacement bug) or inversion o an internal signal, that change the unctionality o the circuit. It will also perorm automatic correction or the detected bugs. The approach assumes a single-gate replacement error, caused by using a wrong gate, but it can correct multiple independent bugs. It consists o three phases: ) the circuit is scanned orward rom the primary inputs (PI) to primary outputs (PO) and an algebraic expression (signature) is derived or each cut (a set o signals that separate PI rom PO); ) the circuit is scanned backward rom PO to PI and an algebraic signature is generated or each cut; ) the dierence between the two expressions, Δ i, at each cut is then computed. A non-zero Δ i or a given cut indicates inconsistency between the two expressions, showing that there is a bug located at this cut. The value o Δ i is then analyzed to determine the source o the bug and to correct it. Under certain conditions several bugs in the same cut can be corrected simultaneously. The rest o this paper is organized as ollows. Section II describes preliminaries. Section III explains in detail the proposed diagnosis and debugging method. Section IV presents experimental results and Section V provides summary and conclusions.

2 II. PRELIMINARIES We ollow the arithmetic veriication approach proposed in [], with the circuit modeled as a network o basic logic gates (AND, OR, XOR, INV, etc.). Each gate is represented as a pseudo-boolean polynomial poly[x], with Boolean variables X = {x,..., x n} and integer coeicients rom Z n. The ollowing equations summarize algebraic representation o basic Boolean operators: a = a a b = a b a b = a + b a b () a b = a + b a b Deinition (Input Signature): The input signature, Sig in, is a polynomial in primary input variables that uniquely represents an integer unction computed by the circuit, i.e., its speciication. For example, an n-bit binary adder with inputs {a,,a n,b,,b n }, is described by n i n Sig i in = i= ai + i = bi. The input signature o a -bit signed multiplier is Sig in = ( a +a )( b +b ) = 4a b a b a b +a b, etc. The integer coeicients (weights) associated with the circuit signals are uniquely determined by the intended circuit unction (speciication). For example, in an adder, the coeicients o the primary inputs at bit position i are c(a i) = c(b i) = i. Deinition (Output Signature): the output signature, Sig out, o the circuit is deined as a polynomial in the primary output signals. Such a polynomial is uniquely determined by an n-bit encoding o the output provided by the designer. For example, the output signature o the -bit signed multiplier is 8z +4z +z +z. In general, an output signature o an unsigned arithmetic circuit with n output bits is represented as a n i linear polynomial, Sigout = i = zi. The coeicients o the primary outputs are also unique, deined by the known output encoding. Deinition (Cut Signature): The cut is a set o signals that separates PI rom PO. The signature o a cut is a polynomial expression in signal variables o the cut that represents the integer number computed by the circuit. The selection o the cuts is an important issue in this approach, as it aects the eiciency o inding the bugs. In the worst case, two cuts may only dier by a single gate. For illustration purpose we assume that the cuts are determined by the topological ordering o signals w.r.t. PI, but other choices exist (determining the best set is part o the uture work). Example : Figure shows a two-bit adder, with Sig in = a +b +a +b, Sig out = 4r +r +r, and topological cuts, labeled,...,. The meaning o Δ i in the igure will be explained in Section III.C. This circuit will be used as a running example in the paper. As shown in [], in a bug-ree arithmetic circuit, the expressions or any two cuts, although expressed by dierent polynomials, always evaluate to the same value, i.e., (cut i) = (cut j), or any {i, j}. This undamental property o the arithmetic circuit serves as basis o the proposed diagnostics and debugging approach. III. BUG IDENTIFICATION Our debugging method consists o: computing cut signatures by orward rewriting, backward rewriting, and comparing the pairs o signatures or each cut to identiy and ix the bugs. A. Forward (PI-PO) rewriting The orward (PI-PO) rewriting starts by dividing the initial polynomial, Sig in, by the polynomials describing the logic gates connected to the PI signals. The goal is to replace the input variables associated with the PI gates with an expression involving the corresponding gate outputs. This produces an expression in the new set o variables, moving away rom PI. While in principle this can be done one gate at a time, one can eliminate several gates at once to speed up the process. To do this division eiciently, knowledge o the signal coeicients (weights) is needed. We explain how to calculate the required coeicients o the newly introduced variables using the structures shown in Figure. Fig.. Two-bit adder circuit with topological cuts. Figure (a) shows a hal-adder (HA) circuit, consisting o a pair (XOR, AND) with common variables. Using the notation in the igure and the algebraic representation o the logic gates given in Eq.(), the computation o the output coeicients o the hal-adder circuit with inputs (a,b) and outputs (m,n) is perormed as ollows: Sig in(ha) = c a+c b Sig out(ha) = c m+ c n = c (a+b-ab) + c ab Since Sig in(ha) = Sig out(ha), we have: c a+c b c (a+b ab) c ab =. By regrouping the variables as ollows a(c - c ) + b(c - c ) + ab(c c ) = and solving the above equation or c and c, we obtain: c = c and c = c. The second structure shown in Fig. (b) consists o an XOR gate and an OR gate. Using similar approach, we obtain: c = c and c =c. Similarly, the structure in Fig. (c), consisting o an OR and an AND gate, produces the coeicients: c = c and c = c. = =-4ecd =-4eg =-4eg

3 Coeicients o the individual gates can be derived similarly. It can be shown that the inputs to an OR or XOR gate must have the same coeicients, c = c, otherwise the algebraic equation or this gate will not be satisied; the coeicient c o the output is equal to those o the input. In contrast, the input coeicients c, c o an AND gate can be dierent, and the output coeicient c = c c. c = c c = c c = -c c = c c = c c = c (a) (b) (c) Fig.. Calculation o signal coeicients. Computing cut signatures: The pseudo code o the algorithm or orward rewriting equation or each cut is shown in Algorithm. The input to this algorithm is the circuit with its input signature, and its output is a set o cut equations. Equation o the irst cut is the same as the speciication, i.e., (cut ) = Sig in. Obtaining cut i rom cut i- works as ollows. Let x j be an output signal o gate g j in cut i and poly(g j) be the polynomial expression describing its logic unction (c.. Eq.()), so that x j = poly(g j). For each gate g j in cut i we add variable x j to the current cut and subtract the algebraic expression poly(g j) representing this gate, without changing the arithmetic unction o the cut. Equation () shows the computation o (cut i) rom (cut i-). ( ) gates cut ( ) ( ) i i = i + j j ( j ) cut cut c x poly g () j = Here, i is the index o the cut, and c j is the coeicient o gate j o cut i. Lines -7 o Algorithm describe the computation o each cut. For simplicity, we write i instead o (cut i). Each i is initialized with i-; using the structure in Fig., or each gate j o cut i, the gate coeicient is calculated so as to eliminate the gate inputs (line 6); inally, equation o cut i is computed (line 7), based on Eq. (). Algorithm Forward (PI-PO) rewriting (Sigin, Circuit) Compute all cuts o the Circuit; = Sigin; or i = to # o cuts 4 i = i-; 5 or j= to #o gates o cuti 6 cj = compute coeicient o gj; 7 i = i + cj(xj - poly(gj)); Algorithm. Forward (PI-PO) rewriting Example : Consider again the circuit in Fig.. By applying the orward (PI-PO) rewriting algorithm, we obtain the ollowing equations or each cut: = b+ a+ b + a = b+ a + b + a + 4( e ab ) + ( d ( a+ b ab )) + ( c ab ) + ( r ( a + b ab )) = 4e+ d + c+ r = 4e+ d + c+ r + 4( g dc) + ( r ( d + c dc)) = 4e+ 4g + r+ r = 4e + 4g + r + r + 4( r ( e + g eg)) = 4r + r+ r + 4eg Note that such computed is dierent than the expected output signature, 4r +r +r. Speciically, it contains the term 4eg, associated with variables o cut. We call such a term a Residual Expression (RE). In a correct circuit, RE should be zero. This can be proved by a straightorward rewriting o 4eg up to the PI variables: 4eg = 4(a b )(dc) = 4(a b )(a +b -a b )(a b ) = Then, = 4r +r +r, indicating that the circuit is correct. The reason or the existence o a residual expression in a correct circuit is that the polynomial division used by orward rewriting does not take into account the Boolean nature o the circuit signals. To avoid RE one would need to divide the polynomials by a set o polynomials <x -x>, called ideals, or each signal x in the circuit, to guarantee that x=,. This method, oten employed by symbolic algebra approach, is too costly and ineicient or this work. B. Backward (PO-PI) rewriting The backward (PO-PI) rewriting is conceptually simpler, basically a reversed symbolic simulation. Starting at the PO with Sig out, it creates a new cut signature by replacing an output signal x j o gate g j with its corresponding algebraic expression: x j poly(g j). Here the signal coeicients are known, provided by the binary encoding o the PO signals. Example : The cut expressions or the two-bit adder in Fig. computed in PO-PI ashion are as ollows: = 4r + r+ r = 4( g + e eg ) + r+ r= 4g + 4e 4eg + r+ r = 4e+ 4(cd) 4e( cd) + (c+ d cd) + r = 4e + d + c + r 4ecd = 4e+ d + c+ r 4ecd = 4(a b) + ( a+ b a b) + (a b) + ( a + b a b) 4(a b)(a b)( a + b a b) = a+ b+ a + b The computed signature at the PI matches the expected speciication, Sigin, so the circuit is correct. Note that the backward rewriting will never produce a residual expression. This is because the algebraic model () o Boolean gates correctly represents the binary value o the gate signal. This convenience comes at a cost o a potentially exponential explosion o the signature size during backward rewriting. C. Computing the signature dierence (Δ i) At this point, a pair o expressions is generated or each cut o the circuit: one computed by the orward and the other by the backward rewriting. The dierence Δ i between the two expressions is deined as ollows: Δ i = i,back - i,for; i cuts () Here, i is the index o cut i, i,back is the signature o cut i in the PO-PI direction, and i,for is the signature o cut i computed by

4 the PI-PO rewriting. I the circuit contains no bug, the value o Δ i at each cut is equal to zero; otherwise, the circuit contains a bug. The expression o Δ i will be used to identiy and to correct the bug. Example 4: Consider the adder circuit in Examples and again. The values o parameter Δ i or each cut o the circuit are shown in Fig.. As can be seen, Δ, Δ and Δ are non-zero polynomials. However, as explained in Example, 4eg and 4ecd are zero unctions (expressions that evaluate to zero), so Δ, Δ and Δ also reduce to zero. D. The Debugging Algorithm In this phase, the circuit is analyzed and veriied against the given speciication to either conirm its correctness or to ind and locate the bug. In principle, the circuit is correct (satisies its speciication) i the signature obtained by backward rewriting matches the given input signature (speciication). Alternatively, the signature obtained by the orward rewriting should match the given output signature, provided that the residual expression RE generated during this rewriting is proven to be zero (as explained earlier, this can be done by a local backward rewriting o the RE expression up to PI). In this paper we consider a particular type o a bug, namely gate replacement, i.e., using a wrong gate in the circuit. In practice, in the presence o a bug, the size o the computed signature may become prohibitively large, and the goal is to locate the cut at which the bug (aulty gate) resides. I the bug is located at some cut i, then the value o Δ i or this cut will be nonzero. This is illustrated by the ollowing example. Example 5: Let us intentionally insert a bug into the two-bit adder circuit in Fig., by replacing the AND gate with inputs (c,d) with an OR gate. The resulting buggy circuit is shown in Fig.. The cut equations or this circuit are as ollows. Forward (PI-PO) rewriting: = b+ a+ b + a = 4e+ d + c+ r = 4e + 4g r + r = 4r r+ r+ 4eg Backward (PO-PI) rewriting: = 4r + r+ r = 4e+ 4g 4eg + r+ r = 4e + 6d + 6c 8cd 4ec 4ed + 4ecd + r = 6a + 6b 8a b + a + b + 4a b 8a b a 8a bb+ a b a b The values o parameter Δ i or each cut o the buggy circuit are calculated using Eq. () and shown in Fig.. The type and the location o the bug can be obtained by assessing the value o Δ i or each cut. Assume initially that each cut has only a single bug (the constraint to be removed later). Table I shows the dierence in the signatures between the cut with the correct gate and the cut with the wrong gate. As an example, consider the entry (a+b-ab) in the st row (AND) and nd column (OR) o the table. It relects the dierence between the correct AND gate (ab) and the wrong OR gate (a+b-ab). That is, i in a given cut, an AND gate is replaced with an OR gate, then Δ i = (a+b-ab)- ab =a+b-ab, where a, b are the gate inputs. Conversely, i or some cut computed by the algorithm, Δ i =a+b-ab, this means that it contains an OR gate while it should contain an AND. Fig.. Two-bit adder with a bug: OR instead o AND The remaining entries in the table give expressions or dierent bugs or a single-gate replacement. To detect the location o the bug in a given cut we need to check i Δ i contains any o the expressions in Table I (replaced by the appropriate variable names). I this is the case, the location o the bug is detected and can be corrected as speciied in the table. Otherwise, either the bug originates at a dierent cut, or it has a dierent nature, not considered in this model. TABLE I. EXPRESSIONS CAUSED BY GATE REPLACEMENT ERROR Buggy Correct AND OR XOR AND a+b-ab a+b-ab OR -a-b+ab -ab XOR -a-b+ab ab Table I can be readily extended to other types o logic gates, such as the complex And-Or-Invert gates used in standard cell implementations. The pseudo code o the Debugging Algorithm is shown in Algorithm. The equation o each cut is irst computed in a PI- PO direction (line ) and then by PO-PI rewriting (line ). Then, Δ i is calculated or each cut. I Δ =, the circuit is correct, otherwise Δ i o other cuts are assessed and their expressions are checked against those in Table I (lines -8). The detected bugs at each cut are stored in the set Bug-list, which consists o the potential bug locations. The expression o each Δ i is then modiied by adding to it expression ( i,for - i+,for), where i,for and i+,for are the expressions obtained by orward rewriting o cut i and cut i+, respectively (lines 9-). This is done to account or the residual expression generated during the orward rewriting between cut i and cut i+, since during the orward rewriting, the residual expression that is based on the variables o cut i actually appears in cut i+. Note that only those terms o expression ( i,for - i+,for) that belong to cut i are added to Δ i. The new Δ i is examined again to check or the buggy expressions (lines -). 4

5 Algorithm Debugging Scan orward (PI-PO) and write equation or each cuti: i,for; Scan backward (PO-PI) and write equation or each cuti: i,back; For each cuti 4 compute Δi = i,back- i,for; 5 I (Δ == ) 6 Return "No Bug"; 7 I Δi contains expression in Table I 8 add detected bug to Bug_list; 9 I (bug_list is empty) For each cuti Δi = Δi + (i,for- i+,for); I Δi contains an expression in Table I add detected bug to Bug_list; 4 I (Bug_list is empty) 5 Return "Bug cannot be detected by our method"; 6 For each member o Bug_list 7 Correct the circuit; 8 Compute Δ; 9 I (Δ == ) Return "Bug is detected and corrected"; Algorithm. Pseudo code o the Debugging Algorithm The Bug-list shows all potential bug locations. I ater modiying the Δ i expressions the Bug-list remains empty, this means that our debugging algorithm cannot detect the bug (lines 4-5). To detect the exact location o the bug and correct the circuit, the irst bug o the Bug-list is replaced with the corresponding correct gate rom Table I. Then the circuit is veriied by re-computing Δ. I Δ, we consider the next bug rom the list and to correct it in the buggy circuit (lines 9-). This process is repeated until the circuit becomes correct, i.e., until Δ =. Example 6: Continuing with Example 5, we compute Δ i or all the cuts, trying to match their variables with one o the expressions in Table I. Recall that only the signals rom the given cut must be used in the matching. At cut, with signals {r,r,r }, Δ =4r -4eg; but 4r does not match any o the expressions in the table. At cut, with signals {e,g,r,r }, we have Δ =4r -4eg. Here we ind that -4eg matches an expression in the table (-ab), at the OR/XOR entry o the table. However, cut does not have any XOR gate, so this cannot be the source o the bug. At cut, with signals {e,d,c,r }, we have Δ =4d+4c-8dc- 4ec-4ed+4ecd. Here 4d+4c-8dc matches the buggy expression (a+b-ab) with coeicient 4, indicating that an OR gate was used instead o an AND gate. As shown in Fig. 4, there is an OR gate at cut with inputs {c, d} so a bug is detected. This bug is then corrected by replacing the OR with an AND. The other terms (-4ec, -4ed) match the expression in the table (OR-XOR gate replacement). But at cut there are no gates with inputs {e, c} or {e, d}; hence no additional bug is reported. In a similar ashion, we can veriy that there are no bugs in cut o. Thereore, the only bug detected is at cut, caused by the OR gate in place o an AND. To correct the circuit, we just need to replace the OR gate with inputs (c, d) with an AND gate with the same inputs. IV. EXPERIMENTAL RESULTS The algorithm has been implemented in C#. The experiments were conducted on a PC with Intel.8-GHz Core i7 processor and 6 GB o memory under Windows 8. We tested gate-level circuits o arithmetic unctions: F = A+B and F = A B, with bit-widths ranging rom to 8 bits. Several bugs (erroneous gates) were inserted in the middle o each circuit. Note that the bugs located near PI are easiest to detect (there is no residual expression) and the bugs inserted near POs are most diicult to detect (the signature with backward rewriting may explode in size). Table II and III show the results or the two circuits containing multiple bugs. TABLE II. DEBUGGING OF F = A + B WITH MULTIPLE BUGS Bit-width # Gates # Bugs Memory CPU time (sec) 4. MB MB MB MB MB MB MB 6.7,66 6. MB MB 6.98 Our method can detect and correct every inserted bug in all the instances o the tested circuits in a reasonable time. The table demonstrates a linear CPU time dependence in the number o bugs (or a small number o bugs perormed in this experiment). TABLE III. DEBUGGING OF F = A B WITH MULTIPLE BUGS Bit-width # Gates # Bugs Memory CPU Time (sec) 8.9 MB 8. 8,6 9.5 MB.5 5. MB MB ,5 9 MB MB MB ,7 MB MB 6.86 V. CONCLUSIONS The goal o this work was to provide a proo o concept or identiying and correcting bugs caused by gate replacement in gate-level arithmetic circuits. Despite its preliminary nature, the initial results demonstrate the validity and potential o the proposed approach or solving practical problems. The limitation o the method is generation o cuts as a means to locate the bugs. Determining the best set o cuts to improve the eiciency o the method is the major goal o our uture work. One possibility is to adopt a binary search approach, by sampling the circuit with selected cuts and checking i their signature is correct. This may need to be supported by random backward simulation to help qualiy the cut as correct or incorrect. The next cut in the sequence will then be placed halway between the aulty one and the PO and the search or bugs will continue in this area in a similar ashion. The method is 5

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