Using VCS with the Quartus II Software

Transcription

1 Using VCS with the Quartus II Sotware December 2002, ver. 1.0 Application Note 239 Introduction As the design complexity o FPGAs continues to rise, veriication engineers are inding it increasingly diicult to simulate their system-ona-programmable-chip (SOPC) designs in a timely manner. The veriication process is now the bottleneck in the FPGA design low. Thereore, FPGA designers are turning to high-perormance, highcapacity simulation tools such as the Synopsys VCS sotware to simulate their designs in a more eicient manner. This application note is a getting-started guide to using the VCS sotware to simulate designs targeting Altera FPGAs, and provides a step-by-step explanation on perorming unctional/behavioral and timing simulations with the VCS sotware. Additionally, this document explains how to simulate complex memory types in the VCS sotware. Sotware Requirements This document contains reerences to eatures available in the Altera Quartus II sotware version 2.2. For more inormation on the Quartus II sotware version 2.2, go to the Altera web site at You must irst install the Quartus II sotware beore using it with the VCS sotware. The Quartus II/Synopsys interace is automatically installed when the Quartus II sotware is installed on your computing platorm. Table 1 shows the supported Quartus II-VCS version compatibility. Table 1. Supported Quartus II-VCS Version Compatibility Synopsys Altera VCS sotware version 5.2 Quartus II sotware version 2.0 VCS sotware version 6.0 Quartus II sotware version 2.2 Reer to the Quartus II Installation & Licensing or PCs or the Quartus II Installation & Licensing or UNIX and Linux Workstation manuals or more inormation on installing the sotware, and the directories that are created during the Quartus II installation. Altera Corporation 1 AN

2 Using VCS in the Quartus II Design Flow The VCS sotware supports the ollowing simulation lows: Functional/behavioral HDL simulations Gate-level timing simulations Figure 1 shows the VCS-Quartus II sotware design low. Figure 1. Altera Design Flow with the VCS & Quartus II Sotware Altera IP Design Entry Testbench Functional Simulation Functional Models Synthesis Place-and-Route Verilog Output File (.vo) Standard Delay Format Output File (.sdo) Gate-Level Simulation Gate-Level Models 2 Altera Corporation

3 Functional/Behavioral HDL Simulation Functional/behavioral HDL simulations veriy the unctionality o the design. These simulations are independent o any Altera FPGA architecture implementation. Once the HDL designs are veriied to be unctionally correct, the next step is to synthesize the design and use the Quartus II sotware or place-and-route. To unctionally simulate an Altera FPGA design in the VCS sotware that uses Altera megaunctions or library o parameterized modules (LPM) unctions, you must include certain libraries during the compile. Table 2 summarizes the Verilog library iles that are required to compile LPM unctions and Altera megaunctions. Table 2. Verilog Library Files Library File altera_m.v stratixgx_m.v 220model.v Description Libraries that contain simulation models or Altera-speciic megaunctions. Libraries that contain simulation models or Stratix TM GX devices. Libraries that contain simulation models or Altera LPM unctions version The iles in Table 2 are created during the Quartus II installation. You can ind these iles in the <path to Quartus II installation>\eda\sim_lib directory. The ollowing VCS command describes the command-line syntax to perorm a unctional simulation with a pre-existing library: vcs -R <test bench>.v <design name>.v v <Altera library ile>.v Functional/Behavioral Simulation with Altera Memory Blocks The VCS sotware supports unctional simulation o complex Altera memory blocks such as LPM_RAM_DP and ALTSYCRAM. You can create these memory blocks with the Quartus II MegaWizard Plug-In Manager, which can be initialized with power-up data via a hexidecimal (.hex) or Memory Initialization File (.mi). The LPM_FILE parameter included in the MegaWizard-generated ile points to the path o the HEX ile or MIF that is used to initialize the memory block. You can create a HEX ile or MIF through the Quartus II sotware. Altera Corporation 3

4 However, the VCS sotware cannot read a HEX ile or MIF ormat. Thereore, to allow unctional simulation o Altera memory blocks in the VCS sotware, you must perorm the ollowing steps: 1. Convert a HEX ile or MIF to a RAM Initialization File (.ri) 2. Modiy o the MegaWizard-generated ile 3. Compile the nopli.v ile For more inormation on creating a MIF, reer to Quartus II Help. Converting a HEX File or MIF to a RIF A RIF is an ASCII text ile that you can use with tools rom EDA vendors. You can create a RIF by converting an existing MIF or HEX ile using the Export Current File As command in the Quartus II sotware. This option is available through the Tools menu while the Quartus II memory editor is open. Modiying the MegaWizard-Generated File You must modiy the MegaWizard-generated ile so that it includes the path to the newly created RIF. You must modiy the LPM_FILE parameter. The ollowing example shows the entry that you must change: lpm_ram_dp_component.lpm_outdata = "UNREGISTERED", lpm_ram_dp_component.lpm_ile = "path to RIF" lpm_ram_dp_component.use_eab = "ON", Compiling nopli.v The nopli.v ile is included in the <path to Quartus II installation>\eda\sim_lib directory. This ile simply contains the ollowing deinition: deine NO_PLI 1 This basic deinition instructs the VCS compile to read in the RIF. The ollowing VCS command simulates a design that includes Altera RAM blocks that require memory initialization: vcs -R <path to Quartusinstallation>\eda \sim_lib\nopli.v <test bench>.v <design name>.v v <Altera library ile>.v 4 Altera Corporation

5 Gate-Level Timing Simulation Quartus II place-and-route produces a design netlist, speciically a VO ile and a SDO ile used or gate-level timing simulation in the VCS sotware. The design netlist output ile is a netlist o the design mapped to architecture-speciic primitives. The SDO ile contains delay inormation or each architecture primitive and routing element speciic to the design. Together, these iles provide an accurate simulation o the design or the selected Altera FPGA architecture. To generate the VO and SDO iles, you must speciy the VCS sotware in the EDA tool settings in the Quartus II sotware. The resulting netlist is written to the <location o Quartus II project>\vcs directory. For more inormation on creating a VO and SDO ile, reer to Quartus II Help. To perorm a timing simulation o an Altera FPGA design in the VCS sotware, you must compile the appropriate post-routing libraries with the design. Table 3 summarizes the device amily library iles that are required to perorm a timing simulation in the VCS sotware. Table 3. Device Family Library Files Library Files apex20k_atoms.v apex20ke_atoms.v apexii_atoms.v cyclone_atoms.v lex6000_atoms.v lex10ke_atoms.v Max_atoms.v mercury_atoms.v stratix_atoms.v stratixgx_atoms.v stratixgx_hssi_atoms.v Description Atom libraries or APEX TM 20K designs Atom libraries or APEX 20KE, APEX 20KC, and Excalibur TM designs Atom libraries or APEX II designs Atom libraries or Cyclone TM designs Atom libraries or FLEX 6000 designs Atom libraries or FLEX 10KE and ACEX 1K designs Atom libraries or MAX 3000 and MAX 7000 designs Atom libraries or Mercury TM designs Atom libraries or Stratix designs Atom libraries or Stratix GX designs The ollowing VCS command describes the command-line syntax to perorm a timing simulation with the post-routing library: vcs -R <test bench>.v <design name>.vo -v <path to Quartus II installation>\eda\sim_lib\ <device amily>_atoms.v +compsd Altera Corporation 5

6 Using Quartus II NativeLink with the VCS Sotware The Quartus II sotware provides NativeLink integration and can automatically run the VCS sotware ater a Quartus II compilation. To enable this eature in the Quartus II sotware, turn on the Run this tool automatically ater compilation check box in the EDA Tool Settings dialog box. The VCS sotware will then process the Quartus II generated VO ile. To use this option on UNIX workstations, ensure that you deine the QUARTUS_INIT_PATH and QUARTUS_INIT_LIBPATH environment variables in the.cshrc ile. The QUARTUS_INIT_PATH variable speciies the path o the VCS tools that are launched in the Quartus II sotware. The QUARTUS_INIT_LIBPATH variable speciies the LD_LIBRARY_PATH variable needed by the VCS sotware to correctly run. Common VCS Compile Switches The VCS sotware has a set o switches that enable you to compile the design in a timely and eicient manner. Table 4 lists some o the switches that are available. Table 4. Device Family Library Files Library Description -R Runs the executable ile immediately. -RI Once the compile has completed, instructs the VCS sotware to automatically launch VirSim. -v <library ilename> Speciies a Verilog library ile (i.e., 220model.v or alteram.v). The VCS sotware looks in this ile or module deinitions that are ound in the source code. -y <library directory> Speciies a Verilog library directory. The VCS sotware looks or library iles in this older that contain module deinitions that are instantiated in the source code. +compsd Indicates that the VCS compiler includes the back-annotated SDF ile in the compilation. +cli Ater successul completion o compilation, Command Line Interace (CLI) Mode is entered. +race Speciies that the VCS sotware generate a report that indicates all o the race conditions in the design. Deault report name is race.out. -P Compiles user-deined Programming Language Interace (PLI) table iles. -q Indicates the VCS sotware runs in quiet mode. All messages are suppressed. 6 Altera Corporation

7 Using VirSim: The VCS Graphical Interace VCS Debugging Support VCS Command-Line Interace VirSim is the graphical debugging system or the VCS sotware. This tool is included with the VCS sotware and can be invoked by using the I compile-time switch when compiling a design. The ollowing VCS command describes the command-line syntax or compiling and loading a timing simulation in VirSim: vcs -RI <test bench>.v <design name>.vo -v <path to Quartus II installation>\eda\sim_lib\ <device amily>_atoms.v +compsd For detailed inormation on using VirSim, reer to the VirSim User Manual included in the VCS installation. The VCS sotware has an interactive non-graphical debugging capability which is very similar to other UNIX debuggers such as GDB. The VCS CLI is used to halt simulations at user-deined break points, orce registers with values, and display values o registers. To enable the non-graphical capability, you must use the +cli run-time switch. To use the VCS CLI to debug your Altera FPGA design, use the ollowing command: vcs -R <test bench>.v <design name>.vo -v <path to Quartus II installation>\eda\sim_lib\ <device amily>_atoms.v +compsd +cli The +cli command takes an optional number argument that speciies the level o debug capability. As the optional debug capability is increased, the overhead incurred by the simulation is increased, resulting in an increase in simulation times. Using PLI Routines with the VCS Sotware For detailed inormation on the +cli switches, reer to the VCS User Guide included in the VCS installation. The VCS sotware can interace your custom-deined C code with Verilog source code. This interace is known as PLI. This interace is extremely useul as it allows advanced users to deine their own system tasks that currently may not exist in the Verilog language. Preparing & Linking C Programs to Verilog Code When compiling the source code, the C code must include a reerence to the vcsuser.h ile. This ile deines PLI constants, data structures, and routines that are necessary or the PLI interace. This ile is included with the VCS installation and can be ound in the $VCS_HOME\lib directory. Once the C code is complete, you must create an object ile (.o). Create the object ile by using the ollowing command: gcc -c my_custom_unction.c Altera Corporation 7

8 Next, you must create a PLI table ile (.tab). This ile maps the C program task to the matching task $task in the Verilog source code. You can create the TAB ile using a standard text editor. The ollowing is an example o an entry in the TAB ile: $my_custom_unction call=my_custom_unction acc+=rw* The Verilog code can now include a reerence to the user-deined task. To compile an Altera FPGA design that includes a reerence to a user-deined system task, type the ollowing at the command-line prompt: vcs -R <test bench>.v <design name>.v -v <Altera library ile>.v P <my_tabile.tab> <my_custom_unction.o> Conclusion Using the VCS sotware within an Altera FPGA design low allows veriication engineers to easily and accurately perorm unctional and timing simulations. You can use the VCS sotware to perorm a unctional simulation o an Altera FPGA design (which includes Altera LPM unctions) by compiling the 220model.v ile. Also, you can use the VCS sotware to perorm a unctional simulation o an Altera FPGA design (which includes Alteraspeciic megaunctions) by compiling the altera_m.v ile. You can use the VCS scan to perorm a timing simulation o an Altera FPGA design by compiling the atom ile or that target device amily. The seamless integration between the VCS and Quartus II sotware makes this simulation low an ideal method or ully veriying an FPGA design. 101 Innovation Drive San Jose, CA (408) Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com Copyright 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, speciic device designations, and all other words and logos that are identiied as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks o Altera Corporation in the U.S. and other countries. All other product or service names are the property o their respective holders. Altera products are protected under numerous U.S. and oreign patents and pending applications, maskwork rights, and copyrights. Altera warrants perormance o its semiconductor products to current speciications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out o the application or use o any inormation, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version o device speciications beore relying on any published inormation and beore placing orders or products or services. 8 Altera Corporation Printed on Recycled Paper.