UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD. LG ELECTRONICS, INC. Petitioner

Transcription

1 UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD LG ELECTRONICS, INC. Petitioner v. ADVANCED MICRO DEVICES, INC. Patent Owner Case No.: IPR Patent 5,898,849 PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 5,898,849

2 TABLE OF CONTENTS i Page I. MANDATORY NOTICES... 1 A. Real Parties-In-Interest... 1 B. Related Matters... 1 C. Lead and Backup Counsel under 37 C.F.R. 42.8(b)(3)... 2 D. Service Information... 2 II. PAYMENT OF FEES... 2 III. STANDING... 2 IV. REQUEST FOR INTER PARTES REVIEW OF CLAIMS 1 AND 14 OF THE 849 PATENT... 3 A. Background of the Technology... 4 B. The Alleged Invention of the 849 Patent... 5 C. Prosecution History... 7 V. CLAIM CONSTRUCTION... 7 A. Construction of Terms Used in the Claims... 7 VI. SUMMARY OF PRIOR ART TO THE 849 PATENT FORMING THE BASIS FOR THIS PETITION... 8 A. U.S. Patent No. 5,696,985 ( Crump ) ( Ex )... 9 B. A Split Data Cache for Superscalar Processors, by R. Boleyn, et al., ICCD 93 ( Boleyn ) ( Ex )... 9 C. U.S. Patent No. 5,592,679 ( Yung ) ( Ex )... 9 D. Video DSP Architecture for MPEG2 Codec, by T. Araki, et al., IEEE 94 ( Araki ) ( Ex ) VII. GROUNDS FOR UNPATENTABILITY FOR EACH CLAIM A. Ground 1: Claims 1 and 14 Are Unpatentable Under 35 U.S.C 102(e) As Anticipated By Crump B. Ground 2: Claim 1 Is Unpatentable Under 35 U.S.C. 102(b) As Anticipated By Boleyn C. Ground 3: Claim 1 Is Unpatentable Under 35 U.S.C. 103(a) As Obvious Over Yung in view of Boleyn... 33

3 D. Ground 4: Claims 1 and 14 Are Unpatentable under 35 U.S.C. 103(a) As Obvious Over Araki in view of Cragon VIII. CONCLUSION ii

4 PETITIONER S EXHIBIT LIST Exhibit # Description 1001 U.S. Patent No. 5,898,849 to Tran ( the 849 Patent ) 1002 Prosecution History of U.S. Patent No. 5,898, Declaration of Nader Bagherzadeh, Ph.D. ( Bagherzadeh Decl. ) 1004 U.S. Patent No. 5,696,985 to Crump ( Crump ) 1005 A Split Data Cache for Superscalar Processors, R. Boleyn, et al., ICCD 93 ( Boleyn ) 1006 U.S. Patent No. 5,592,679 to Yung ( Yung ) 1007 Video DSP Architecture for MPEG2 CODEC, by T. Araki, et al. (1994) Curriculum Vitae of Nader Bagherzadeh, Ph.D Complaint filed in Related District Court Case 1010 Computer Architecture, Pipelined and Parallel Processor Design, M. Flynn, iii

5 Pursuant to 35 U.S.C and 37 C.F.R & et seq., Petitioner respectfully requests inter partes review of Claims 1 and 14 of Ex. 1001, U.S. Patent No. 5,898,849 ( the 849 Patent ) ( Ex ), which issued on April 27, See also Ex. 1002, Prosecution History of the 849 Patent. The challenged claims are unpatentable under 35 U.S.C. 102 and 103 over the prior art publications identified and applied in this Petition. I. MANDATORY NOTICES disclosures: Pursuant to 37 C.F.R. 42.8, Petitioner provides the following mandatory A. Real Parties-In-Interest. LG Electronics U.S.A., Inc. and LG Electronics MobileComm U.S.A., Inc. are real parties-in-interest with Petitioner, LG Electronics, Inc. B. Related Matters. Pursuant to 37 C.F.R. 42.8(b)(2), Petitioner submits that the 849 patent is the subject of a patent infringement lawsuit brought by the Patent Owner, Advanced Micro Devices, Inc. against Petitioner in the following case that may affect or be affected by a decision in this proceeding: Advanced Micro Devices, Inc. et al v. LG Electronics, Inc. et al., Case No. 3:14-cv SI. Petitioner is concurrently filing petitions to review U.S. Patent Nos. 6,266,715; 6,784,879; 6,889,332; 6,895,520; 6,897,871; 7,095,945; 7,327,369; and 7,742,053.

6 C. Lead and Backup Counsel under 37 C.F.R. 42.8(b)(3) Lead Counsel Robert G. Pluta Reg. No. : 50,970 Mayer Brown, LLP 71 S. Wacker Drive Chicago, IL Telephone: (312) Fax: (312) Backup Counsel Cody Gillians cgillians@mayerbrown.com Reg. No. : 71,293 Mayer Brown, LLP 1999 K Street, N.W. Washington, D.C Telephone: (202) Fax: (202) D. Service Information Pursuant to 37 C.F.R. 42.8(b)(4), Petitioner identifies the following service information: Please direct all correspondence regarding this proceeding to lead counsel at the address identified above. Petitioner consents to electronic service by rpluta@mayerbrown.com and cgillians@mayerbrown.com with a courtesy copy to AMDIPR@mayerbrown.com. II. PAYMENT OF FEES Pursuant to 37 C.F.R , $23,000 is being paid at the time of filing this petition, charged to Deposit Account Should any further fees be required by the present Petition, the Patent Trial and Appeal Board ( the Board ) is hereby authorized to charge the above referenced Deposit Account. III. STANDING Pursuant to 37 C.F.R (a), Petitioner certifies that (1) the 849 patent is available for inter partes review; and (2) Petitioner is not barred or estopped from Page 2

7 requesting inter partes review of Claims 1 and 14 of the 849 patent on the grounds identified in this Petition. In particular, this Petition is timely filed under 35 U.S.C. 315(b). IV. REQUEST FOR INTER PARTES REVIEW OF CLAIMS 1 AND 14 OF THE 849 PATENT Pursuant to 37 C.F.R (b), Petitioner respectfully requests that the Board find unpatentable Claims 1 and 14 of the 849 Patent. Such relief is justified as the alleged invention of the 849 Patent was described by others prior to the effective filing date of the 849 Patent. 1 1 Inter partes review is limited to evaluating invalidity issues arising from the consideration of certain prior-art issues, i.e., 35 U.S.C ; and, therefore, excludes consideration of indefiniteness, enablement, and numerous other grounds for invalidity. Petitioner thus files this inter partes review without prejudice to its right to challenge the validity of the subject patent in other forums and proceedings on any and all bases recognized by law and equity, including, but not limited to, the basis that wherein said first [second] functional unit, responsive to a first [second] plurality of address operands specified by a first [second] instruction, is configured to generate a first [second] memory address corresponding to a first [second] memory operand of said first [second] instruction and functional unit in claim 1 are indefinite. Page 3

8 A. Background of the Technology The 849 Patent relates generally to microprocessors and specifically to caching mechanisms within microprocessors. Generally, microprocessors are often integrated into computer systems having relatively large, but relatively slow, main memories commonly known as DRAMs. See Ex. 1001, at 1: To counter the main memory s reduced memory bandwidth, microprocessors employ memory caches to store the most recently and frequently accessed data and instructions. Id. at 2:3-7; Ex. 1003, Declaration of Nader Bagherzadeh, Ph.D. ( Bagherzadeh Decl. ), at 38. Caches are smaller and closer physically to the processor than main memory. See Bagherzadeh Decl., at 38. As a result, finding and accessing data stored in a cache takes less time than finding and accessing the identical data stored in the main memory. See Ex. 1001, at 2:7-10. See Bagherzadeh Decl., at 38. Over time, processor designers looked for additional design techniques to increase processor efficiency. See Bagherzadeh Decl., at 33. One technique, superscalar processor architecture, improves processor efficiency through the use of functional units. See Ex. 1001, 1:11-54; Bagherzadeh Decl., at 33. Functional units are the part of a microprocessor that performs a specific set of calculations and operations. Bagherzadeh Decl., at 34. Functional units operate independent of each other and in parallel with each other, resulting in increased processor efficiency. Bagherzadeh Decl., at 34. Although these functional units increase the number of instructions that can be simultaneously executed within a clock cycle, early processors Page 4

9 contained one cache and each functional unit accessed the single cache to retrieve data. Consequently, the increased number of functional units degrades system performance by reducing cache bandwidth and increasing signal wire delay. See Ex. 1001, at 2:11-36; Bagherzadeh Decl., at 40. B. The Alleged Invention of the 849 Patent As shown in Fig. 1 of the 849 Patent, the disclosed microprocessor includes multiple functional units: Ex. 1001, Fig. 1. These functional units include: integer units 18A-18C, a floating point unit 19, and a multimedia unit 20. Id. The disclosed microprocessor also contains a number of local caches 15A-15E connected to the functional units. Id. Page 5

10 An allegedly novel feature of this invention is to provide each functional unit with its own dedicated cache, thereby improving system performance by reducing interconnect delay and processing delays. Id. at 2:55-3:8; see Bagherzadeh Decl., at 42. Also, an allegedly novel method of accessing data within the local caches is claimed. As recited in claim 1, the method includes generating memory addresses specific addresses used to identify data within memory locations from address operands, operands generally used to indicate that data is located in some memory location. See Ex at Claim 1; 9:18-56; Bagherzadeh Decl. at 43. Once the functional unit generates a memory address, the local cache uses the memory addresses to attempt to retrieve memory operands for execution. Id. If the memory address is not located within the local cache, the memory address is used to retrieve the memory operand from another location. Id. at 10: Dependent claim 14 simply discloses that the functional unit may be a multimedia unit configured to process instructions designed for efficient operation upon audio and video data. See id. at Claim 14; 7: As will be shown below, these features are not novel concepts and were known and developed long before the 849 Patent was filed. First, it is not novel to attach smaller memory storage devices directly to units that execute instructions instead of using one large memory storage device connected to multiple units that execute instructions. Second, taking address operands and converting them to memory addresses to retrieve data from storage locations was well known at the time of the invention. Page 6

11 C. Prosecution History U.S. Patent Application No. 08/835,066, filed on April 4, 1997, was issued as the 849 Patent on April 27, During prosecution of the 849 Patent, the U.S. Patent & Trademark Office ( USPTO ) issued a Non-Final Office Action rejecting claims 1-24 as obvious over U.S. Patent No. 5,592,676 to Yung and other references. Ex. 1002, at In particular, the Examiner noted that [w]hile Yung taught the gist of the invention as stated above, Yung did not explicitly call his local buffer [a] local cache. It would have been obvious to one of ordinary skill in the art to recognize that a cache is a memory buffer used to decrease access time to frequently used data. Id. at 103. In response to the Office Action, Applicant cancelled claims 15-19, added new claims 25-33, and amended claims 1-2 and to include the allegedly novel limitations of functional units that generate a first memory address and us[e] said first memory address in order to retrieve a first memory operand from data caches. Id. at The Examiner found that these amendments were enough to distinguish Yung and issued a Notice of Allowance on January 4, Id. at V. CLAIM CONSTRUCTION A. Construction of Terms Used in the Claims A claim subject to inter partes review is given its broadest reasonable construction in light of the specification of the patent in which it appears. 37 C.F.R (b). Petitioner notes that this standard of claim construction differs from the Page 7

12 standard used to interpret claims in a District Court proceeding. Consequently, constructions of the claim terms that the Panel may adopt in this proceeding, and positions Petitioner takes in response of those constructions, are not relevant to or binding upon Petitioner in current or subsequent litigation related to the 849 Patent. See SAP America, Inc. v. Versata Development Group, Inc., CBM , at 6 19 (PTAB June 11, 2013). In particular, Petitioner expressly reserves the right to and may submit constructions for the claims or for individual claim terms in Advanced Micro Devices, Inc., et al., v. LG Electronics, Inc., et al., Case No. 3:14-cv now pending in the Northern District of California, under the legal standard applicable in that proceeding, which are different than those proposed or adopted in this proceeding, including how a person of ordinary skill in the art would understand the claims in light of relevant intrinsic and extrinsic evidence. VI. SUMMARY OF PRIOR ART TO THE 849 PATENT FORMING THE BASIS FOR THIS PETITION The following documents serve as a basis to show that Petitioner has a reasonable likelihood of prevailing with respect to at least one of Claims 1 and 14 of the 849 Patent. Petitioner provides a detailed explanation of the pertinence and manner of applying the cited prior art to Claim 1 and 14 of the 849 Patent in Section VII, infra. In light of the prior art references, the 849 Patent is unpatentable and does not reflect innovation or invention. Page 8

13 A. U.S. Patent No. 5,696,985 ( Crump ) ( Ex ) Crump discloses an invention to improve the performance capability of video processing systems by using a parallel video processor. See Ex. 1004, 1: Crump qualifies as prior art at least under 35 U.S.C. 102(e), because Crump was filed June 7, 1995, before April 4, 1997, the filing date of the 849 Patent. Crump was not cited or considered during prosecution of the application that led to the 849 Patent. B. A Split Data Cache for Superscalar Processors, by R. Boleyn, et al., ICCD 93 ( Boleyn ) ( Ex ) Boleyn discloses an analysis of performance benefits of a split data cache memory design. Ex. 1005, at Abstract. Boleyn was published in October 1993 and qualifies as prior art at least under 35 U.S.C. 102(b), because it was published more than one year prior to April 4, 1997, the filing date of the application that led to the 849 Patent. C. U.S. Patent No. 5,592,679 ( Yung ) ( Ex ) Yung is directed to a multi-level scheduling system for controlling multiple execution pipes of a distributed data flow (DDF) processor. Ex. 1006, at Abstract. Yung qualifies as prior art at least under 35 U.S.C. 102(a) and 102(e), because Yung was filed on Nov. 14, 1994 and issued on January 7, 1997, before April 4, 1997, the filing date of the application that led to the 849 Patent. As discussed earlier, Yung was cited during prosecution of the application that led to the 849 Patent. Page 9

14 D. Video DSP Architecture for MPEG2 Codec, by T. Araki, et al., IEEE 94 ( Araki ) ( Ex ) Araki discloses a video digital signal processor used for MPEG2 video coding and decoding. Ex. 1007, 1. Araki was published in 1994 and qualifies as prior art at least under 35 U.S.C. 102(b), because it was published more than one year prior to April 4, 1997, the filing date on which the application that led to the 849 Patent. Araki was not cited or considered during prosecution of the application that led to the 849 Patent. VII. GROUNDS FOR UNPATENTABILITY FOR EACH CLAIM In light of the disclosures detailed below, the 849 Patent is unpatentable for at least the reasons summarized in the chart below and discussed more in detail herein Ground # Ground Prior Art Exhibit(s) # Claims 1 102(e) Crump , (b) Boleyn (a) Yung in view 1006, of Boleyn 4 103(a) Araki in view 1007, , 14 of Boleyn A. Ground 1: Claims 1 and 14 Are Unpatentable Under 35 U.S.C 102(e) As Anticipated By Crump Crump discloses an invention to improve the performance capability of video processing systems by using a parallel video processor ( PVP ). See Ex. 1004, 1:23-2:52, Abstract. A PVP contains a plurality of processors on a single VLSI device, wherein each [processor] has associated instruction and data caches, which are joined Page 10

15 together by a wide data bus formed on the same substrate as the processors. Id. at 1: Fig. 3 depicts an illustration of the disclosed video processor: The processors 30(a-d) within the PVP 10 are microcoded engines. Id. at 3: These processors are not general purpose processors but have been explicitly designed to process video and graphic type algorithms. Id. at 4:5-7. Additionally, the processors run primarily out of the associated caches. Id. at 3: Crump notes that [t]he beauty of this architecture is the programmability of the processors enabling implementation of a wide variety of computationally intensive tasks. Id. at 3: Crump also discloses that the MPEG2 algorithm can also map onto the PVP to create a special purpose PVP ( the MPEG2 PVP ). See id. at 18: As shown in Fig. 12, each of the microcoded engines within the MPEG2 PVP is dedicated for specific functions. See id. at Fig. 12. Page 11

16 Two of the engines (2 and 3) are dedicated to inverse scanning, inverse quantization and inverse discrete cosine transformations which are a portion of the instructions needed to process MPEG2 signals. Id. at 18: Other engines are dedicated to motion compensations and variable length decoding. Id. at 18: Crump discloses many of the limitations of claim 1. Crump discloses two functional units configured to execute instructions because it discloses two programmable microcoded engines 30a and 30b. Id. at Fig. 3; see Bagherzadeh Decl., at Additionally, it should be noted that the 849 Patent defines functional units as units configured to execute at least a subset of the instructions within the instruction set employed by the microprocessor. Ex. 1001, at 2:24-29 (emphasis added). To the extent the Board does not believe that the microcoded engines are functional units, Crump also discloses a MPEG2 PVP that has two microcoded engines dedicated to inverse scanning, inverse quantization and inverse discrete cosine transform instructions, which are a portion of the operations needed to process Page 12

17 MPEG2 signals. Ex. 1004, at 18:18-37; Bagherzadeh Decl., at Moreover, the PVP microcoded engines and the MPEG2 PVP s microcoded engines are configured to execute instructions because an instruction cache feeds instructions to both engines for execution by the ALUs within the microcoded engines. Ex. 1004, at Figs. 8 and 9; 4:4-9; see Bagherzadeh Decl., at Crump also discloses two local caches connected to each of the functional units because it discloses D-caches 32a and 32b connected to each of the microcoded engines. Ex. 1004, at Figs. 3 and 9; see Bagherzadeh Decl., at 62. Also, the D-cache of unit 2 and the D-cache of unit 3 of the MPEG2 PVP shown in Fig. 12 can be considered the first local cache and the second local cache, respectively. Crump also discloses functional units configured to generate a memory address from an address operand and functional units configured to use the memory address to retrieve a memory operand from a local cache because it discloses a load store unit within the microcoded engines connected to a D-cache. As shown in Fig. 9 below, the load unit 41a is connected to the D cache 32a. Ex. 1004, at Fig. 9. Page 13

18 The load unit within each microcoded engine takes address operands from instructions and converts those operands into a memory address. See Bagherzadeh Decl., at 53-58, Once the load unit generates the memory address, it sends the memory address to the D-cache to retrieve the memory operand. Additionally, Crump notes that [i]t is the programmer s responsibility to calculate any data addresses needed and [t]he programmer can access the relocation register and use it to form effective addresses for data operations as needed. Ex. 1004, 11: Regarding Claim 14, the specification for the 849 patent explicitly states that multimedia instructions are instructions designed for efficient operation upon audio and video data. Ex. 1001, at 7: Accordingly, Crump s processors which have Page 14

19 been explicitly designed to process video and graphic type algorithms satisfy this limitation. See Bagherzadeh Decl., at Additionally, in the MPEG2 PVP, two engines are dedicated to inverse scanning, inverse quantizations, and inverse discrete cosine transforms; one engine is dedicated to the motion compensation algorithm; and one engine is dedicated to variable length decoding, all functional needed to process the MPEG 2 algorithm. Ex. 1004, at 18:18-37; see Bagherzadeh Decl., at In light of the above, the table below demonstrates how each limitation of claims 1 and 14 of the 849 Patent is disclosed by Crump. For all these reasons, claims 1 and 14 are unpatentable in view of Crump and thus, Petitioner has a reasonable likelihood of prevailing with respect to at least one claim. Claim Element Crump (Ex. 1004) [1.a] microprocessor comprising: A A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors. Ex. 1004, at Abstract. Much of the following disclosure will address a particular processor architecture and its embodiment on a single chip device. Id. at 2: Page 15

20 Claim Element Crump (Ex. 1004) [1.b] a first functional unit configured to execute instructions See also Bagherzadeh Decl., at 48-49, 59. Each of a plurality of processors (indicated at 30a, 30b, 30c and 30d in FIG. 3) is a microcoded engine in the form of a Harvard architecture device with an instruction cache (31a, 31b, 31c and 31d) and a data cache (32a, 32b, 32c and 32d). Id. at 3: Page 16

21 Claim Element Crump (Ex. 1004) Id. at Fig. 8. The PVP processors are not designed as general purpose processors or DSPs. Instead, the PVP processors have been explicitly designed to process video and graphic type algorithms. It is for this reason that the PVP is set up to process four element vectors with a limited ALU instruction set that is tuned for video/graphic applications. Id. at 4:4-9. [1.c] wherein said first functional unit, responsive to a first plurality of address operands specified by a first instruction See Bagherzadeh Decl., at See citations to claim element 1.b above. See also Bagherzadeh Decl., at 53-59, 63. Page 17

22 Claim Element Crump (Ex. 1004) [1.d] is configured to generate a first memory address corresponding to a first memory operand of said first instruction; Ex. 1004, at Fig. 9. Each processor in the PVP has an address space register that contains a thirty two bit value that is used as an offset for all code fetches. This address is added to all code fetches in the system and all effective address generation. This allows the code windows for each processor to be moved very easily. All data fetches are absolute and do not have a relocation register. It is the programmer's responsibility to calculate any data addresses needed. The programmer can access the relocation register and use it to form effective addresses for data operations as needed. Ex. 1004, at 11: See citations to claim element 1.b above [1.e] a second functional unit configured to execute See also Bagherzadeh Decl., at 53-59, 64. See citations to claim element 1.b above. Page 18

23 Claim Element Crump (Ex. 1004) instructions, [1.f] wherein said second functional unit, responsive to a second plurality of address operands specified by a second instruction, [1.g] is configured to generate a second memory address corresponding to a second memory operand of said second instruction; [1.h] a first local cache coupled to said first functional unit See citations to claim element 1.c above. See citations to claim element 1.d above. Each of a plurality of processors (indicated at 30a, 30b, 30c and 30d in FIG. 3) is a microcoded engine in the form of a Harvard architecture device with an instruction cache (31a, 31b, 31c and Page 19

24 Claim Element Crump (Ex. 1004) 31d) and a data cache (32a, 32b, 32c and 32d). Ex. 1004, at 2:66-3:16. [1.i] wherein said first functional unit is configured to access said first local cache using said first memory address in order to retrieve said first memory operand corresponding to said first instruction; and See also Bagherzadeh Decl., at 53-59, 62. The fact that all processors are on a common, single substrate allows for higher bandwidth communication between the processors and memory. A single bus 34, here called a line bus, has been chosen as the interconnect mechanism. The bus is very wide, i.e. it can transfer an entire cache line between caches 31, 32 or between a cache 31, 32 and memory interface 39 during each bus cycle. All processors 30 have a unified memory address space. Any processor 30 can access and cache any portion of on or off screen memory. Id. at 3: The local D cache in each processor will attempt to cache the memory/data operation. Id. at 12: Id. at Fig. 9. Page 20

25 Claim Element Crump (Ex. 1004) [1.j] a second local cache coupled to said second functional unit, 1k) wherein said second functional unit is configured to access said second local cache using said second memory address in order to retrieve said second memory operand corresponding to said second instruction. See also Bagherzadeh Decl., at 53-59, 64. See citations to claim element 1.h above. See citations to claim element 1.i above. 14. The microprocessor as recited in claim 1 wherein said first functional unit comprises a multimedia unit configured to execute multimedia instructions. The Parallel Video Processor (PVP) 10 to be described hereinafter is a video processing architecture designed to handle the increasing demand for real time video and image processing. Video conferencing, MPEG decompression, and 3D rendering for scientific and entertainment applications are all examples of video processing that require significant computational power to perform in real time. Ex. 1004, at 2:66-3:5. Page 21

26 Claim Element Crump (Ex. 1004) Id. at Fig. 12. FIG. 12 shows how the MPEG2 algorithm could map onto the PVP. Each of the four engines is assigned a portion of the decompression. Engine 1 is physically attached to the serial input FIFO. Logically therefore, it will perform the variable length decoding and serve as the master controller of the other three. It will assemble the sixty four element arrays that get passed to the inverse scan process. This passing of data is performed via a shared memory buffer. Note however that due to the cache architecture, the data may never actually get written to DRAM. It will stay dirty and move from cache to cache as needed. Two engines (numbers 2 and 3) are dedicated to the inverse scanning, inverse quantization, and inverse discrete cosine transforms of the 8 8 matrices. These two engines should be able to process over 100,000 non zero 8 8 matrices/sec. Motion compensation is performed by the last engine. It receives the output of the IDCT and adds it to the reference block(s) form the current block. The video output subsystem must be configured to display the YCrCb buffers of the previous frame while the current frame is being constructed. Id. at 18: Page 22

27 Claim Element Crump (Ex. 1004) See also Bagherzadeh Decl., at 67. B. Ground 2: Claim 1 Is Unpatentable Under 35 U.S.C. 102(b) As Anticipated By Boleyn Boleyn proposes a method of improving the performance of superscalar microprocessor technology by using a split data cache memory design. Ex. 1005, at Abstract. According to Boleyn, a split data cache allows for floating-point and integer memory accesses to be executed in parallel. See id.; Bagherzadeh Decl., at 70. Figure 2, reproduced below, illustrates a split cache model machine consisting of two functional blocks, the Integer Unit and Floating Point Unit, and two separate caches, the Integer Data Cache and Floating Point Data Cache. Page 23

28 See Ex. 1005, at Fig. 2. The Integer Data Cache ( dcache ) stores data for use by the integer functional units, while the Floating Point Data Cache ( fcache ) stores data for the floating-point units. Id. at 3. Each functional unit has an independent bus that allows the units to access the caches individually. Id. Moreover, Boleyn notes that [c]ache accesses for integer and floating-point data are independent which removes any contention between the integer and floating point units for the data and address Page 24

29 busses. Id. at 3. Additionally, as shown in Figure 2, an Instruction Cache and Instruction Memory provides instructions to the integer and floating point functional units. See id. at Fig. 2. Regarding claim 1, Boleyn discloses a first functional unit configured to execute instructions in the form of an integer unit and a second functional unit configured to execute instructions in the form of a floating-point unit. These are the identical exemplary functional units disclosed within Fig. 2 of the 849 Patent. See Ex. 1001, at Fig. 1. Moreover, the functional units disclosed within Boleyn, like the functional units in the 849 Patent, are configured to execute instructions because an instruction stream is delivered from an instruction cache to each functional unit. See Ex. 1005, at 1, 3. Also, Boleyn discloses a first local cache and a second local cache connected to a first functional unit and a second functional unit, respectively, because it discloses a dcache and a fcache. Fig. 2 of Boleyn shows that the dcache is coupled to the integer unit and the fcache is coupled to the floating point unit. See Ex. 1005, Fig. 2. Additionally, Boleyn discloses functional units configured to generate a memory address from an address operand and functional units configured to use that memory address to retrieve memory operands from local caches because Boleyn discloses a load unit within the integer unit and a float load unit within the floatingpoint unit used to generate a memory address and retrieve data from the data caches using the generated memory address. Id. at 3. As discussed earlier, a load unit takes Page 25

30 address operands from instructions and converts those operands into a memory address. See Bagherzadeh Decl., at Here, once the load unit or the float load unit converts the operand into a memory address, it sends the address to the dcache or the fcache, respectively, as shown in Fig. 2. See Bagherzadeh Decl., at 55-56, 75; Ex. 1005, at Fig. 2. In light of the above, the table below demonstrates how each limitation of claim 1 of the 849 Patent is disclosed by Boleyn. For all these reasons, claim 1 is unpatentable in view of Boleyn and thus, Petitioner has a reasonable likelihood of prevailing with respect to at least one claim. Claim Element Boleyn (Ex. 1005) [1.a] A microprocessor comprising: [1.b] a first functional unit configured to execute instructions Superscalar implementations of RISC architectures are emerging as the dominant high-performance microprocessor technology for the mid-1990 s. This paper proposes and evaluates a split data cache memory design, a new memory system enhancement for superscalar processor architectures. Ex. 1005, at Abstract. See also Bagherzadeh Decl., at The base machine model is shown in Figure 1. This processor model is divided into two main operational units, the integer unit and the floating point unit, each with its own register file. Ex at 3. A single instruction stream supplied by the instruction memory through the instruction cache controls the integer and floating point units. Page 26

31 Claim Element Boleyn (Ex. 1005) Id. Id. [1.c] wherein said first functional unit, responsive to a first plurality of address operands specified by a first instruction See also Bagherzadeh Decl., at Although superscalar implementations can improve the performance of almost all types of application programs to some degree, simple superscalar implementations are particularly effective at improving the performance of numerically oriented scientific applications. Many of the first generation of commercial superscalar processors use a dual-issue model, allowing one floating point operation and one integer operation to begin execution each cycle. The Hewlett Packard PA-RISC 7100 processor [DeLano92] is typical of this class of implementation. Floating-point instructions are Page 27

32 Claim Element Boleyn (Ex. 1005) identified early in the decoding process and issued in parallel with integer instructions. Ex at 1. Integer data is almost always accessed by specific integer instructions and floating-point data is almost always accessed by specific floating-point instructions. Id. at 2. See citations to claim element 1.b. [1.d] is configured to generate a first memory address corresponding to a first memory operand of said first instruction; See also Bagherzadeh Decl., at Although superscalar implementations can improve the performance of almost all types of application programs to some degree, simple superscalar implementations are particularly effective at improving the performance of numerically oriented scientific applications. Many of the first generation of commercial superscalar processors use a dual-issue model, allowing one floating point operation and one integer operation to begin execution each cycle. The Hewlett Packard PA-RISC 7100 processor [DeLano92] is typical of this class of implementation. Floating-point instructions are identified early in the decoding process and issued in parallel with integer instructions. Ex. 1005, at 1. Integer data is almost always accessed by specific integer instructions and floating-point data is almost always accessed by specific floating-point instructions. Id. at 2. The only difference between the base machine and the subject architecture is the presence of a split data cache. This consists of two separate caches, with a single cache Page 28

33 Claim Element Boleyn (Ex. 1005) controller or two tightly-coupled cache controllers that implement a simple cache-coherency mechanism. One cache stores data for use by the integer functional units (the integer data cache, or dcache), and the other cache stores data for the floating -point units (the floating - point data cache, or fcache). Both the dcache and the fcache contain 32KB of data in 32-byte blocks with 8- way-set associativity; implement random replacement policy when no empty block is available; and have a miss penalty of 16 cycles. The interface to main memory is shared by the two caches. The base machine s common data and address busses between the integer and floating-point units have been replaced by separate busses which access the caches individually. This machine is illustrated in Figure 2. Cache accesses for integer and floating -point data are independent. There is no longer any contention between the integer and floating point units for the data and address busses. Both operational units contain load/store units. For comparison purposes, the floating-point and integer load/store units are chosen to have a reservation station depth of 16. Id. at 3. This can be explained by the fact that the integer operations are primarily used for address generation and rely on few variables. Id. at 5. See Id. at Fig. 2. [1.e] a second functional unit configured to execute See also Bagherzadeh Decl., at 55-56, 70-75, 78. See citations to claim element 1.b. Page 29

34 Claim Element Boleyn (Ex. 1005) instructions, [1.f] wherein said second functional unit, responsive to a second plurality of address operands specified by a second instruction, [1.g] is configured to generate a second memory address corresponding to a second memory operand of said second instruction; [1.h] a first local cache coupled to said first functional unit See citations to claim element 1.c. See citations to claim element 1.d. The only difference between the base machine and the subject architecture is the presence of a split data cache. This consists of two separate caches, with a single cache controller or two tightly-coupled cache controllers that implement a simple cache-coherency mechanism. One cache stores data for use by the integer functional units (the integer data cache, or dcache), and the other cache stores data for the floating-point units (the floatingpoint data cache, or fcache). Both the dcache and the fcache contain 32KB of data in 32-byte blocks with 8- way-set associativity; implement random replacement policy when no empty block is available; and have a miss penalty of 16 cycles. The interface to main memory is shared by the two caches. The base machine's common data and address busses between the integer and floating-point units have been replaced by separate busses which access the caches individually. This machine is illustrated in Figure 2. Cache accesses for integer and floating-point data are independent. There is no longer any contention between the integer and floating point units for the data and address busses. Both operational units contain load/store units. For comparison purposes, the floating-point and integer load/store units are chosen to have a reservation station Page 30

35 Claim Element Boleyn (Ex. 1005) depth of 16. Ex. 1005, at 3. Id. at 3. [1.i] wherein said first functional unit is configured to access said first local cache using said first memory address in order to retrieve said first memory operand corresponding to said first instruction; and See Bagherzadeh Decl., at 70-75, 77. The limited access to operands in memory is a much greater challenge in processor design. Access to operands is increased through the use of high -speed registers and data caches in a memory hierarchy. Blockoriented algorithms and optimizing compilers reduce the number of main memory references, however for floating-point intensive applications, memory bandwidth is still a limiting factor. Increasing the effective memory bandwidth is quite difficult, especially within the sequential memory models that dominate current programming methods. Multi-ported memories Page 31

36 Claim Element Boleyn (Ex. 1005) that can service more than one simultaneous memory access are expensive and slower than comparable single-ported memories. A simple form of multiple access data cache, the split data cache, is proposed in this paper. The data cache is comprised of two separate single-ported memories, one for storage of integer data and one for storage of floating-point data. Id. at 1. Integer data is almost always accessed by specific integer instructions and floating -point data is almost always accessed by specific floating-point instructions. Using a separate integer data cache and floating-point data cache provides twice as much memory bandwidth to a superscalar RISC processor as a single data cache. Id. at 2. The only difference between the base machine and the subject architecture is the presence of a split data cache. This consists of two separate caches, with a single cache controller or two tightly-coupled cache controllers that implement a simple cache-coherency mechanism. One cache stores data for use by the integer functional units (the integer data cache, or dcache), and the other cache stores data for the floating-point units (the floatingpoint data cache, or fcache). Both the dcache and the fcache contain 32KB of data in 32-byte blocks with 8- way-set-associativity; implement random replacement policy when no empty block is available; and have a miss penalty of 16 cycles. The interface to main memory is shared by the two caches. The base machine's common data and address busses between the integer and floating -point units have been replaced by separate busses which access the caches individually. This machine is illustrated in Figure 2. Cache accesses for integer and floating-point data are independent. There is no longer any contention between the integer Page 32

37 Claim Element Boleyn (Ex. 1005) and floating point units for the data and address busses. Both operational units contain load/store units. For comparison purposes, the floating-point and integer load/store units are chosen to have a reservation station depth of 16. Id. at 3. [1.j] a second local cache coupled to said second functional unit, [1.k] wherein said second functional unit is configured to access said second local cache using said second memory address in order to retrieve said second memory operand corresponding to said second instruction. See also Bagherzadeh Decl., at 70-75, 78. See citations to claim element 1.h. See citations to claim element 1.i. C. Ground 3: Claim 1 Is Unpatentable Under 35 U.S.C. 103(a) As Obvious Over Yung in view of Boleyn Yung discloses a method to increase the ability of processors to execute instructions in parallel by using multi-level instruction scheduling systems for controlling multiple execution pipes of distributed data flow (DDF) processors. See Ex. 1006, at 1:13-22; 2: To accomplish this, Yung discloses a system that Page 33

38 includes a global instruction scheduler responsible for distributing instructions among multiple execution pipes. Id. at Abstract. Figure 2 is a block diagram illustrating the invention of Yung: Execution pipe 241 contains the following: local instruction buffer 241a, local instruction scheduler 241b, execution units 241c, and local register buffer 241d. Id. at 4:66-5:2. To process instructions, the global instruction scheduler 230 first receives instructions from instruction cache 210 and then distributes the instructions to the local instruction buffer 241a within execution pipe 241. See id. at 5: The global instruction scheduler can be configured to distribute instructions to a particular Page 34

39 execution pipe depending on the type of instruction and operands within the instruction in a manner very similar to the decode unit of the 849 Patent. See Ex. 1006, at 5:32-43; Ex. 1001, at 7:18-20; Fig. 1; Bagherzadeh Decl., at Once instructions have been distributed to an execution pipe and prepared for execution, the execution unit 241c executes the instructions. See Ex. 1006, at 5:44-5:56; Bagherzadeh Decl., at 84. To speed up operation, each execution pipe contains a local register buffer that can be used to store operand values. See Ex. 1006, at 6:3-8; 8:42-46; Bagherzadeh Decl., at Similar to the benefits described in the 849 Patent, Yung notes that, by dedicating a small number of fast register buffers located close to a small subset of execution units[,] faster access times to the most frequently accessed operands are possible. Ex. 1006, at 6:28-33; see Bagherzadeh Decl., at 85-87; Ex. 1001, at 2:55-3:16. If the operand from the instruction is located within the register buffer, the operand is transferred to the execution unit to be operated upon. See Ex. 1006, at 5:56-6:18. Yung discloses many of the limitations of claim 1. Yung discloses two functional units configured to execute instructions because Yung discloses execution units 241c and 242c. Although Yung does not explicitly disclose two caches as required by claim 1, one of ordinary skill in the art would have understood that a cache and a register buffer are two forms of smaller localized storage. Bagherzadeh Decl., at 89; see also Ex. 1002, at Thus, it would have been obvious to one of ordinary skill in the art to replace Yung s register buffers 241d and 242d with caches Page 35

40 because caches usually hold more data compared to buffers. Bagherzadeh Decl., at 89. Additionally, to the extent Yung does not explicitly disclose functional units configured to generate a memory address from an address operand and local caches configured to use the memory address to retrieve memory operands, Boleyn discloses these limitations. Bagherzadeh Decl., at 90. As stated earlier, Boleyn discloses a load unit used to generate memory addresses from address operands specified in instructions and retrieve memory operands using the memory address. Bagherzadeh Decl., at 56, 90. It would have been obvious to one of ordinary skill in the art to combine Yung with Boleyn because both references discuss accessing forms of memory to retrieve desired information. Bagherzadeh Decl., at One of ordinary skill in the art would see that Yung doesn t clearly show how to access the register buffers to retrieve data and would be motivated to find a way to retrieve data from the buffers, a form of storage. Bagherzadeh Decl., at One of ordinary skill in the art would look to Boleyn to solve that problem, because Boleyn discusses a way to retrieve desired data from caches, another form of storage. Bagherzadeh Decl., at 56, In light of the above, the table below demonstrates how each limitation of claim 1 of the 849 Patent is disclosed by Yung and Boleyn. For all these reasons, claim 1 is unpatentable in view of Yung and Boleyn and thus, Petitioner has a reasonable likelihood of prevailing with respect to at least one claim. Page 36

41 Claim Element Yung (Ex. 1006) and Boleyn (Ex. 1005) [1.a] A microprocessor comprising: Yung The present invention provides a multi-level instruction scheduling system for controlling multiple execution pipes of a distributed data flow (DDF) processor. Ex. 1006, at Abstract. FIG. 2 is a block diagram illustrating the DDF processor architecture in accordance with one embodiment of the present invention. DDF processor 200 includes an instruction cache memory 210, a plurality of prefetch buffers 221, 222, , a global instruction scheduler 230, a plurality of execution pipes 241, 242, , one or more inter-pipe bypass(es) 251, , an arbiter 260, and a global register file/memory 290. Each instruction pipe includes its own local instruction buffer, local instruction scheduler, execution unit(s) and temporary local register buffer. For example, instruction pipe 241 includes a local instruction buffer 241a, a local instruction scheduler 241b, execution unit(s) 241c and a local register buffer 241d. Similarly, instruction pipe 242 includes a local instruction buffer 242a, a local instruction scheduler 242b, execution unit(s) 242c and a local register buffer 242d. Hence a description of the operation of execution pipe 241 is equally applicable the other execution pipes 242, Ex. 1006, at 4:57-5:7. [1.b] a first functional unit configured to execute instructions See also Bagherzadeh Decl., at Yung The present invention provides a multi-level instruction scheduling system for controlling multiple execution Page 37

42 pipes of a distributed data flow (DDF) processor. The multi-level scheduling system includes a simple global instruction scheduler and multiple local instruction schedulers corresponding to the number of execution pipes. The global instruction scheduler is responsible for distributing instructions among the execution pipes. Each local instruction scheduler is only responsible for scheduling its share of distributed instructions and matching the reduced number of instructions with the execution units of the corresponding execution pipe when all its source operands are available. Source operands are garnered in one of three ways. First, the local instruction scheduler ensures that locally generated register operand values are stored in a local register buffer and made available quickly to younger instructions distributed to the execution pipe. Second, when source operand values of the instruction are not available in the local register buffer, an inter-pipe operand request is made to an arbiter. If the operand value(s) is available from another execution pipe, a transfer of the source operand(s) is initiated via an inter-pipe bypass coupling the first and second execution pipes. Third, if the source register operand value(s) cannot be found in any of the other execution pipes, the register operand value(s) is retrieved from a global register file via an inter-pipe bypass. This multiple execution pipe architecture advantageously lends itself to software optimizing techniques such as multi-tasking, system exception/trap handling and speculative execution, e.g., instruction branch prediction techniques. Ex. 1006, at Abstract FIG. 2 is a block diagram illustrating the DDF processor architecture in accordance with one embodiment of the present invention. DDF processor 200 includes an instruction cache memory 210, a plurality of prefetch buffers 221, 222, , a global instruction scheduler 230, a plurality of execution pipes 241, 242, , one or more inter-pipe bypass(es) 251, , an arbiter 260, and a global register Page 38

43 file/memory 290. Each instruction pipe includes its own local instruction buffer, local instruction scheduler, execution unit(s) and temporary local register buffer. For example, instruction pipe 241 includes a local instruction buffer 241a, a local instruction scheduler 241b, execution unit(s) 241c and a local register buffer 241d. Similarly, instruction pipe 242 includes a local instruction buffer 242a, a local instruction scheduler 242b, execution unit(s) 242c and a local register buffer 242d. Hence a description of the operation of execution pipe 241 is equally applicable the other execution pipes 242, Ex. 1006, at 4:57-5:7. Ex. 1006, Fig. 2. Page 39

44 See also Ex. 1006, Claim 1. [1.c] wherein said first functional unit, responsive to a first plurality of address operands specified by a first instruction See also Bagherzadeh Decl., at Yung Abstract The present invention provides a multi-level instruction scheduling system for controlling multiple execution pipes of a distributed data flow (DDF) processor. The multi-level scheduling system includes a simple global instruction scheduler and multiple local instruction schedulers corresponding to the number of execution pipes. The global instruction scheduler is responsible for distributing instructions among the execution pipes. Each local instruction scheduler is only responsible for scheduling its share of distributed instructions and matching the reduced number of instructions with the execution units of the corresponding execution pipe when all its source operands are available. Source operands are garnered in one of three ways. First, the local instruction scheduler ensures that locally generated register operand values are stored in a local register buffer and made available quickly to younger instructions distributed to the execution pipe. Second, when source operand values of the instruction are not available in the local register buffer, an inter-pipe operand request is made to an arbiter. If the operand value(s) is available from another execution pipe, a transfer of the source operand(s) is initiated via an inter-pipe bypass coupling the first and second execution pipes. Third, if the source register operand value(s) cannot be found in any of the other execution pipes, the register operand value(s) is retrieved from a global register file via an inter-pipe bypass. This multiple execution pipe architecture advantageously lends itself to software optimizing techniques such as multi-tasking, system exception/trap handling and speculative execution, e.g., instruction branch prediction techniques. Page 40

45 [1.d] is configured to generate a first memory address corresponding to a first memory operand of said first instruction; Ex. 1006, at Abstract. See also Bagherzadeh Decl., at 83-87, 90. Boleyn Although superscalar implementations can improve the performance of almost all types of application programs to some degree, simple superscalar implementations are particularly effective at improving the performance of numerically oriented scientific applications. Many of the first generation of commercial superscalar processors use a dual-issue model, allowing one floating point operation and one integer operation to begin execution each cycle. The Hewlett Packard PA-RISC 7100 processor [DeLano92] is typical of this class of implementation. Floating-point instructions are identified early in the decoding process and issued in parallel with integer instructions. Ex. 1005, at 1. Integer data is almost always accessed by specific integer instructions and floating-point data is almost always accessed by specific floating-point instructions. Id. at 2. The only difference between the base machine and the subject architecture is the presence of a split data cache. This consists of two separate caches, with a single cache controller or two tightly-coupled cache controllers that implement a simple cache-coherency mechanism. One cache stores data for use by the integer functional units (the integer data cache, or dcache), and the other cache stores data for the floating -point units (the floating - point data cache, or fcache). Both the dcache and the fcache contain 32KB of data in 32-byte blocks with 8- way-set associativity; implement random replacement policy when no empty block is available; and have a miss penalty of 16 cycles. The interface to main memory is shared by the two caches. The base Page 41

46 machine s common data and address busses between the integer and floating-point units have been replaced by separate busses which access the caches individually. This machine is illustrated in Figure 2. Cache accesses for integer and floating -point data are independent. There is no longer any contention between the integer and floating point units for the data and address busses. Both operational units contain load/store units. For comparison purposes, the floating-point and integer load/store units are chosen to have a reservation station depth of 16. Id. at 3. This can be explained by the fact that the integer operations are primarily used for address generation and rely on few variables. Id. at 5. See id. at Fig. 2. See also Bagherzadeh Decl., at 70-75, 78. Yung The present invention provides a multi-level instruction scheduling system for controlling multiple execution pipes of a distributed data flow (DDF) processor. The multi-level scheduling system includes a simple global instruction scheduler and multiple local instruction schedulers corresponding to the number of execution pipes. The global instruction scheduler is responsible for distributing instructions among the execution pipes. Each local instruction scheduler is only responsible for scheduling its share of distributed instructions and matching the reduced number of instructions with the execution units of the corresponding execution pipe when all its source Page 42

47 operands are available. Source operands are garnered in one of three ways. First, the local instruction scheduler ensures that locally generated register operand values are stored in a local register buffer and made available quickly to younger instructions distributed to the execution pipe. Second, when source operand values of the instruction are not available in the local register buffer, an inter-pipe operand request is made to an arbiter. If the operand value(s) is available from another execution pipe, a transfer of the source operand(s) is initiated via an inter-pipe bypass coupling the first and second execution pipes. Third, if the source register operand value(s) cannot be found in any of the other execution pipes, the register operand value(s) is retrieved from a global register file via an inter-pipe bypass. This multiple execution pipe architecture advantageously lends itself to software optimizing techniques such as multi-tasking, system exception/trap handling and speculative execution, e.g., instruction branch prediction techniques. Ex. 1006, at Abstract. See also Bagherzadeh Decl., at [1.e] a second functional unit configured to execute instructions, [1.f] wherein said second functional unit, responsive to a second plurality of address operands specified by a second instruction, [1.g] is configured to generate a second memory address corresponding to a second memory operand of said second See citations to claim element 1.b above See citations to claim element 1.c above See citations to claim element 1.d above Page 43

48 instruction; [1.h] a first local cache coupled to said first functional unit Yung Once all the source operands of each instruction in execution pipe 241 has been retrieved either from within the same pipe 241, from one of the other execution pipes 242, via inter-pipe bypass 251, and/or from global register file 290, local instruction scheduler 241b matches and dispatches the instruction to a free execution unit of execution unit(s) 241c. Local register buffer 241d of execution pipe 241 advantageously allows faster local access to register values produced within execution pipe 241. Eventually, the instruction completes execution in execution pipe 241 and is retired. The result operand value generated by execution pipe 241 is then written into global register file 290. In addition, local instruction scheduler 241b communicates the completion of execution to global instruction scheduler 230, thereby completing the processing of the instruction. Ex. 1006, at 7: The method of claim 4 wherein said providing step includes the step of retrieving said first source operand value from a local register buffer of said first execution pipe. 8. The method of claim 4 wherein said garnering step includes the step of retrieving said second source operand value from a local register buffer of said second execution pipe. Ex. 1006, at 10: Page 44

49 Ex. 1006, at Fig. 2. [1.i] wherein said first functional unit is configured to access said first local cache using said first memory address in order to retrieve said first memory operand corresponding to said first instruction; and See Bagherzadeh Decl., at Yung (Ex. 1006) Once all the source operands of each instruction in execution pipe 241 has been retrieved either from within the same pipe 241, from one of the other execution pipes 242, via inter-pipe bypass 251, and/or from global register file 290, local instruction scheduler 241b matches and dispatches the instruction to a free execution unit of execution unit(s) 241c. Local register buffer 241d of execution pipe 241 advantageously allows faster local access to register values produced within execution pipe 241. Eventually, the instruction completes execution in execution pipe 241 and is retired. The result operand value generated Page 45

50 by execution pipe 241 is then written into global register file 290. In addition, local instruction scheduler 241b communicates the completion of execution to global instruction scheduler 230, thereby completing the processing of the instruction. Ex. 1006, at 7: The method of claim 4 wherein said providing step includes the step of retrieving said first source operand value from a local register buffer of said first execution pipe. 8. The method of claim 4 wherein said garnering step includes the step of retrieving said second source operand value from a local register buffer of said second execution pipe. Ex. 1006, at 10: Boleyn The limited access to operands in memory is a much greater challenge in processor design. Access to operands is increased through the use of high -speed registers and data caches in a memory hierarchy. Blockoriented algorithms and optimizing compilers reduce the number of main memory references, however for floating-point intensive applications, memory bandwidth is still a limiting factor. Increasing the effective memory bandwidth is quite difficult, especially within the sequential memory models that dominate current programming methods. Multi-ported memories that can service more than one simultaneous memory access are expensive and slower than comparable single-ported memories. A simple form of multiple access data cache, the split data cache, is proposed in this paper. The data cache is comprised of two separate single-ported memories, one for storage of integer data and one for storage of Page 46

51 floating-point data. Ex. 1005, at 1. Integer data is almost always accessed by specific integer instructions and floating -point data is almost always accessed by specific floating-point instructions. Using a separate integer data cache and floating-point data cache provides twice as much memory bandwidth to a superscalar RISC processor as a single data cache. Ex. 1005, at 2. The only difference between the base machine and the subject architecture is the presence of a split data cache. This consists of two separate caches, with a single cache controller or two tightly-coupled cache controllers that implement a simple cache-coherency mechanism. One cache stores data for use by the integer functional units (the integer data cache, or dcache), and the other cache stores data for the floating-point units (the floatingpoint data cache, or fcache). Both the dcache and the fcache contain 32KB of data in 32-byte blocks with 8- way-set-associativity; implement random replacement policy when no empty block is available; and have a miss penalty of 16 cycles. The interface to main memory is shared by the two caches. The base machine's common data and address busses between the integer and floating -point units have been replaced by separate busses which access the caches individually. This machine is illustrated in Figure 2. Cache accesses for integer and floating-point data are independent. There is no longer any contention between the integer and floating point units for the data and address busses. Both operational units contain load/store units. For comparison purposes, the floating-point and integer load/store units are chosen to have a reservation station depth of 16. Ex. 1005, at 3. Page 47

52 [1.j] a second local cache coupled to said second functional unit, [1.k] wherein said second functional unit is configured to access said second local cache using said second memory address in order to retrieve said second memory operand corresponding to said second instruction. See also Bagherzadeh Decl., at 70-75, 78, See citations to claim element 1.h above. See citations to claim element 1.i above. D. Ground 4: Claims 1 and 14 Are Unpatentable under 35 U.S.C. 103(a) As Obvious Over Araki in view of Boleyn Araki discloses a digital signal processor named VDSP2 (Video Digital Signal Processor version 2), which employs a parallel processing scheme for decoding and encoding MPEG2 codecs in multimedia applications. Ex. 1007, at 1. As diagrammed in Figure 2 below, the VDSP contains a DSP core, which consists of one programmable control unit (DPCU) which executes scalar-type instructions and four vector processing units (VPU0-3) which executes the parallel vector operation. Id. at 2. Page 48

53 As shown in Fig. 3 below, each VPU contains an enhanced ALU, a multiplier, an accumulator, shifters and memories. See id. at 2-3, Fig 3. Finally, instruction sets used by the DSP core are optimized to compression algorithm[s], especially, MPEG2. Id. at 3. Page 49