Hardware Verification 2IMF20
|
|
|
- Bryan Davidson
- 5 years ago
- Views:
Transcription
1 Hardware Verification 2IMF20 Julien Schmaltz Lecture 01: Introduction to Hardware (Formal) Verification
2 Lectures» Two blocks every week (w36 to w43)» Tue 13:45-15:30 Room LUNA 1.056» Thu 08:45-10:30 Room LUNA 1.056» Exam on (week 34)» 3-hour written exam 2
3 Lecturer» Julien Schmaltz» Room MF6.071b / j.schmaltz@tue.nl / 8691» Drop by any time, but might not be available» PhD 2006 from Univ. Grenoble (NoC Verification)» Postdoc Saarbruecken, Germany» 2007-present Working in the NL at different universities Radboud University, ESI, Open Universiteit TU/e since February
4 Round table - Quick check» Short introduction about yourself. Where are you from?» CSE/ES/AT/BIS? Which stream are you in? Pre-master?» 1st/2nd year?» Background hardware design or formal methods? 4
5 Grading» 50 % grade of the written exam» 50% practical assignments» groups of 2 students allowed» Types of assignments» make your own circuit equality checker» verify a (simple) design using a commercial or academic tool» current plan (warning: subject to modifications!)» 1st exercise, easy, 20%» 2nd exercise, medium, 30%» 3nd exercise, small project 50%» (alternative might also be 20,40,40) 5
6 New 2017: Verify your own design» Assignments 2 and 3 about using Jasper Gold from Cadence to verify hardware designs» simple communication network» simple execution unit of a micro-processor» Possible alternative:» verify your own design!» something you made for another course, for instance» Verilog, SystemVerilog, or VHDL» must be synthesizable» interested?» check with me / show me your design 6
7 Lecture materials» Slides» Papers» Demo s» Notes from the lecturer» Invited lecture from Industry (Dialog Semiconductors)» Everything available from course website Check website for updates! 7
8 A possible definition of FV Formal Verification: is the use of tools that mathematically analyse the space of possible behaviours of a design, rather than computing results for particular values. Seligman, Schubert, Kumar 8
9 Formal verification: A short historical perspective present Birth of AI Automated reasoning Early applications FDIV bug (1994) Industrial routine Formal SignOff (Oski) block level with 100% FV
10 Formal verification: A short historical perspective present Birth of AI Automated reasoning Early applications FDIV bug (1994) Industrial routine Formal SignOff (Oski) block level with 100% FV 1956: - Logic Theorist, Newell Simon and Shaw - McCarthy coined the term Artificial Intelligence 1959: A proof of a large routine by A. Turing
11 Formal verification: A short historical perspective present Birth of AI Automated reasoning Early applications FDIV bug (1994) Industrial routine Formal SignOff (Oski) block level with 100% FV 1960 s: - Floyd and Hoare - notion of partial and total correctness
12 Formal verification: A short historical perspective present Birth of AI Automated reasoning Early applications FDIV bug (1994) Industrial routine Formal SignOff (Oski) block level with 100% FV 1970 s: - Boyer-Moore theorem prover (Nqthm, later ACL2) - Introduction of Temporal Logics by Pnueli
13 Formal verification: A short historical perspective present Birth of AI Automated reasoning Early applications FDIV bug (1994) Industrial routine Formal SignOff (Oski) block level with 100% FV 1980 s: - Model checking Emerson, Clarke, and Sifakis - Automatic proofs of temporal properties - BDD from Bryant
14 Formal verification: A short historical perspective present Birth of AI Automated reasoning Early applications FDIV bug (1994) Industrial routine Formal SignOff (Oski) block level with 100% FV 1990 s: - Symbolic model checking (SMV) McMillan - FDIV bug at Intel - First EDA solutions for equivalence checking
15 Formal verification: A short historical perspective present Birth of AI Automated reasoning Early applications FDIV bug (1994) Industrial routine Formal SignOff (Oski) block level with 100% FV 2000 s: - Standards for writing assertions (PSL and System Verilog) - Efficient SAT solvers - Bounded-model checking (Biere et al.)
16 Formal verification: A short historical perspective present Birth of AI Automated reasoning Early applications FDIV bug (1994) Industrial routine Formal SignOff (Oski) block level with 100% FV 2010 s: - IC3 algorithm (Bradley) - Formal Sign-Off (Oski Technologies)
17 Formal verification: A short historical perspective present Birth of AI Automated reasoning Early applications FDIV bug (1994) Industrial routine Formal SignOff (Oski) block level with 100% FV Future: system level formal verification
18 System Level (Formal) Verification Challenges - Interconnects (can be seen as small systems) - Component interactions (Power Management, Cache Coherence, NoC, ) - Producer-Consumer relations (e.g. peripheral and DMAC) - Liveness, livelock, deadlock, performance, 18
19 Limitations and challenges (1) Kurt Goedel Alan Turing ( ) ( ) Incompleteness & Undecidability This sentence is not provable (liar paradox) Halting problem 19
20 Limitations and challenges (2) Boolean SAT is NP-Complete Stephen Cook ( ) 20
21 Combatting limitations» State matching» Bounded proofs» Decomposition» Targeted verification» Size reduction» Case splitting» Design abstractions» Data abstractions Some will be covered in this course, not all of them. 21
22 Hardware Design Flow Overview No formal equivalences All steps proven functionally equivalent to RTL This is changing. C to RTL equivalence today feasible 22
23 Hardware Formal Verification Domain Properties Formal Tools RTL Code Formal Model OK! NOK! Witness and counter-examples 23
24 Current practice 24
25 Why formal?» Intel FDIV bug (1995)» estimated cost about USD 475,000,000» Similar bug today» probable cost about USD 12,000,000,000» FYI: net income in 2014 was USD 11.7 billion» Also, using formal is cheaper and faster than simulation» (sometimes, but more and more often) 25
26 Oski decoding formal club Video from Oski web page link is the following: 26
27 Notes from the video» Formal is replacing simulation» 100% formal, no testing on some blocks» Ever growing communities» C to RTL equivalence checking» Fully automatic solutions, even without writing any properties!» Hiding formal was a key aspect» From academic to practical solutions 27
28 Impact of have a look at the following keynote video» confid=139&filter=keynote&id= &#video» ARM CTO about scaling to 2020 solutions» A few points» Formal as a side salad» 1.5 millions of hours to simulate M0 chip» (note this is about 170 years!)» Need to hide formal and integrate at design phase 28
29 Moore s law still applies - More cores! #transistors clock speed #cores (on-chip processor) 2004 How do we build bug-free multi-core industrial systems? 29
30 Scalability Issue atoms in the universe. more than states in a 5x5 network. 30
31 This course and our research Foundations Technological Advances General Theory of On-Chip Network Architectures Languages & Verification Technologies Real World Applications Integration & Tools Intel ARM STMicroelectronics Prototype Environment 31
32 Link with other courses (1)» System Validation (2IMF30)» mu-calculus & process algebra (2IMF10)» high-level models» Automated Reasoning (2IMF25)» Details about SAT/SMT» Model-checking with NuSMV and BDDs» Seminar Formal System Analysis (Q6, next quartile)» Algorithms for model checking (2IMF35)» Proving with computer assistance (2IMF15)» Program verification techniques (2IMP10) 32
33 Link with other courses (2)» 5SIB0: Electronic Design Automation» Synthesis, technology mapping, etc.» 5LIH0: Digital integrated circuit design» Design oriented (low level)» 5LIF0: Advanced digital circuit design» Design at low level» 2IMN35: VLSI Programming» Higher level system layers (e.g. data flows) 33
34 Course content - Domain & RTL Domain Properties Processors Networks Formal Tools Cache coherence RTL Code Formal Model OK! NOK! Witness and counter-examples 34
35 Course content - Properties Domain Properties Temporal Logics (LTL, CTL) System Verilog Assertions Processors Networks Formal Tools Cache coherence RTL Code Formal Model OK! NOK! Witness and counter-examples 35
36 Course content - Formal models Temporal Logics (LTL, CTL) Domain Properties System Verilog Assertions Processors Networks Cache coherence Sum-of-Products (SoP) Conjunctive Normal Form (CNF) Binary Decision Diagrams (BDDs) And-Inverter Graphs (AIGs) Formal Tools RTL Code Formal Model OK! NOK! Witness and counter-examples 36
37 Course content - Formal tools Temporal Logics (LTL, CTL) Domain Properties System Verilog Assertions Academic or Industrials Processors Networks Cache coherence Sum-of-Products (SoP) Conjunctive Normal Form (CNF) Binary Decision Diagrams (BDDs) And-Inverter Graphs (AIGs) Formal Tools RTL Code Formal Model OK! NOK! Witness and counter-examples 37
38 Course practical assignments» During the course you will work on several practical assignments» The goal is» to practice with concrete verification issues» (for example, the verification of a processor using Jasper)» or to write your own verification tool» (for example, writing a circuit comparator)» You will get some help! 38
39 Learning Goals At the end of the course, a student:» understands the challenges related to hardware verification at levels of abstractions ranging from high-level functional specifications down to bits;» understands the basic principles of key verification techniques: SAT solving, model checking, equivalence checking;» can use academic or industrial verification tools on small and moderate-size problems;» understands and applies abstractions and over-approximations when necessary;» has a basic knowledge about issues and techniques related to concurrency and multi-core architectures. 39
40 Program for today» Basic Verilog & Hardware» Reminder about basic UNIX» you need UNIX on your machine (Linux and OSX have it)» you will need to connect to our server» you need to ssh from a terminal with graphic export» you will need to use the UNIX file system in command line» (mkdir, rm, mv, etc)» you also need to use simple text editors from our server» vi, vim, emacs» evince to read pdf» You need make and gcc» If you have no idea what I am talking about, please speak up! 40
41 CMOS Transistors These are CMOS (Complementary Metal-Oxide Semiconductor). The PMOS transistor is on when the gate low. The NMOS transistor is on when the gate is high. 41
42 CMOS Gates (1) CMOS transistors are combined to create logic gates. What logical (Boolean) function is implemented here? Remember: Vdd is a logical 1, Vss is a logical 0. 42
43 CMOS Gates (2) What logical (Boolean) function is implemented here? Remember: Vdd is a logical 1, Vss is a logical 0. Do you see where the complementary is coming from? 43
44 CMOS Gates (3) What logical (Boolean) function is implemented here? Remember: Vdd is a logical 1, Vss is a logical 0. Do you see where the complementary is coming from? 44
45 CMOS Gates (4) How would you build an AND gate? an OR gate? 45
46 Abstracting away from transistors We will not work at the level of transistors. We will first abstract to 4-valued logic as follows: - logical 0 (or False ) will be a 0 voltage (0 Volt) - logical 1 (or True ) will be a 1 voltage (say about 1 Volt) - X or unknown, e.g. signals need time to propagate. Values cannot be determined yet - Z for high-impedance or un-driven, for instance when transistors are all blocks then output is not driven (used in practice in a bus with multiple drivers) We will then quickly go to Boolean logic with only True and False. 46
47 4 valued logic» 0: false or low voltage» 1: true or high voltage» X: unknown, don t care» Z: un-driven, high impedance Verilog standard Input Output 0 1 X Z Input Gate Output X X X X X 0 X X X 1 0 Z Z X Z 0 X X X 0 0 Z 47
48 Quizz: What is this? 48
49 Quizz: What is this? A 2-to-1 multiplexer described at a structural level. 49
50 Levels of abstractions We can describe hardware at the structural level by connecting gates. Thanks to Logic Synthesis we can describe hardware at the behavioural level. module mux( input [7:0] i0, input [7:0] i1, input sel, output [7:0] o); assign o = sel? i1 : i0; endmodule This is our 2-to-1 multiplexer written using the Verilog Hardware Description Language (HDL). Another popular language is VHDL. We will only use Verilog and its extension System Verilog. 50
51 Combinatorial vs. Sequential A circuit is said to be combinatorial when its outputs only depend on its current inputs. The circuit has no memory, no state. In contrast, a circuit is said to be sequential when it has memory, that is, state. Its outputs depend on previous computations. This defines what is commonly known as a Finite State Machine (FSM). The basic state holding element in this course is a register. An FSM is a Moore machine when the outputs only depend on the current state. An FSM is a Mealy machine when the outputs depend on the current state and the current inputs. 51
52 Verilog HDL - Simple module module sreg4 (clk,rst,ie,in,clr,flags); input clk, rst,ie; input [3:0] clr; // clear vector // clear all flags marked with a 0 in the vector. output[3:0] flags; input [3:0] in; reg [3:0] content; clk) content <= rst? 4'b0 : ( ie? in & clr: content & clr); // content is masked with the clear vector. // All positions marked with a 0 in clr will also be zero in content. assign flags = content; endmodule 52
53 Verilog HDL - Module instantiation // SREG // Status register wire SREG$ie; wire [3:0] sreg$out, clrf; sreg4 sreg (.clk(clk),.rst(rst),.ie(sreg$ie),.in(flg),.clr(clrf),.flags(sreg$out)); 53
54 Verilog - Some references» System verilog standard» Verilog Language Reference Guide» Use Verilog to describe some simple designs» Later in the course» System Verilog Assertions» Writing properties for Assertion Based Verification (ABV) 54
55 Verilog - some more references» [1] FSM.pdf» [2] [3] [4] Teaching/HDL-Design/14x/Nexys3/Verilog/docs-pdf/lab10.pdf» [5] (with test bench example)» [6] 07-SeqLogicIIIx2.pdf» [7] Machine-Examples.pdf 55
56 Verilog - in this course» You will need to read simple Verilog / System Verilog. We will use design examples for applying verification techniques. You need to read and understand (a bit) these examples.» You will need to write System Verilog Assertions. To do this, you need to be able to write some very basic Verilog code. Notions like clocks and assignments are important.» You are NOT expected to become advanced Verilog or System Verilog experts at the end of this course!!» In general, Verilog syntax close to C.» At the end, Verilog is just another programming language» but be aware that it describes hardware! 56
57 Homework before next lecture» Read papers mentioned in the course website» paper about Intel s experience with formal» some papers about hardware verification using ACL2» Check on-line documentation about Verilog and UNIX-like OS» (make sure you have a UNIX-like system on your machine)» Install ONE SAT solver to start with assignment 1» Glucose ( Lingeling ( Z3 ( Next lecture will be about» representations of Boolean expressions» combinational equivalence checking» start with assignment 1 57
58 Thanks! 58
Hardware Design Verification: Simulation and Formal Method-Based Approaches William K Lam Prentice Hall Modern Semiconductor Design Series
Design Verification An Introduction Main References Hardware Design Verification: Simulation and Formal Method-Based Approaches William K Lam Prentice Hall Modern Semiconductor Design Series A Roadmap
ECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog
ECE 2300 Digital Logic & Computer Organization Spring 2018 More Sequential Logic Verilog Lecture 7: 1 Announcements HW3 will be posted tonight Prelim 1 Thursday March 1, in class Coverage: Lectures 1~7
Lab. Course Goals. Topics. What is VLSI design? What is an integrated circuit? VLSI Design Cycle. VLSI Design Automation
Course Goals Lab Understand key components in VLSI designs Become familiar with design tools (Cadence) Understand design flows Understand behavioral, structural, and physical specifications Be able to
Hardware Modeling using Verilog Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Hardware Modeling using Verilog Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture 01 Introduction Welcome to the course on Hardware
ECE 595Z Digital Systems Design Automation
ECE 595Z Digital Systems Design Automation Anand Raghunathan, raghunathan@purdue.edu How do you design chips with over 1 Billion transistors? Human designer capability grows far slower than Moore s law!
structure syntax different levels of abstraction
This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital
Here is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this
This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital
Introduction to Verilog HDL
Introduction to Verilog HDL Ben Abdallah Abderazek National University of Electro-communications, Tokyo, Graduate School of information Systems May 2004 04/09/08 1 What you will understand after having
Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University
Hardware Design Environments Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Outline Welcome to COE 405 Digital System Design Design Domains and Levels of Abstractions Synthesis
CS/ECE 5780/6780: Embedded System Design
CS/ECE 5780/6780: Embedded System Design John Regehr Lecture 18: Introduction to Verification What is verification? Verification: A process that determines if the design conforms to the specification.
Verilog. What is Verilog? VHDL vs. Verilog. Hardware description language: Two major languages. Many EDA tools support HDL-based design
Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two major languages Verilog (IEEE 1364), latest version is
Administrivia. ECE/CS 5780/6780: Embedded System Design. Acknowledgements. What is verification?
Administrivia ECE/CS 5780/6780: Embedded System Design Scott R. Little Lab 8 status report. Set SCIBD = 52; (The Mclk rate is 16 MHz.) Lecture 18: Introduction to Hardware Verification Scott R. Little
Design Verification Lecture 01
M. Hsiao 1 Design Verification Lecture 01 Course Title: Verification of Digital Systems Professor: Michael Hsiao (355 Durham) Prerequisites: Digital Logic Design, C/C++ Programming, Data Structures, Computer
Synthesizable Verilog
Synthesizable Verilog Courtesy of Dr. Edwards@Columbia, and Dr. Franzon@NCSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Design Methodology Structure and Function (Behavior) of a Design HDL
Fundamentals of Digital System Design ECE 3700, CPSC 3700
Fundamentals of Digital System Design ECE 3700, CPSC 3700 Instructor: Priyank Kalla (kalla@ece.utah.edu) 4 Credits Tue, Thu 1:25-1:45pm, WEB 1230 Office Hours: Tue, Thu: 2:30-4pm, or by appointment Office:
Computer Architecture (TT 2012)
Computer Architecture (TT 2012) The Register Transfer Level Daniel Kroening Oxford University, Computer Science Department Version 1.0, 2011 Outline Reminders Gates Implementations of Gates Latches, Flip-flops
EE 4755 Digital Design Using Hardware Description Languages
EE 4755 Digital Design Using Hardware Description Languages Basic Information URL: http://www.ece.lsu.edu/v Offered by: David M. Koppelman, Room 345 ERAD Building 578-5482. koppel@ece.lsu.edu, http://www.ece.lsu.edu/koppel/koppel.html
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital
Research Collection. Formal background and algorithms. Other Conference Item. ETH Library. Author(s): Biere, Armin. Publication Date: 2001
Research Collection Other Conference Item Formal background and algorithms Author(s): Biere, Armin Publication Date: 2001 Permanent Link: https://doi.org/10.3929/ethz-a-004239730 Rights / License: In Copyright
The QR code here provides a shortcut to go to the course webpage.
Welcome to this MSc Lab Experiment. All my teaching materials for this Lab-based module are also available on the webpage: www.ee.ic.ac.uk/pcheung/teaching/msc_experiment/ The QR code here provides a shortcut
CHAPTER 1 INTRODUCTION
CHAPTER 1 INTRODUCTION Rapid advances in integrated circuit technology have made it possible to fabricate digital circuits with large number of devices on a single chip. The advantages of integrated circuits
FPGA Based Digital Design Using Verilog HDL
FPGA Based Digital Design Using Course Designed by: IRFAN FAISAL MIR ( Verilog / FPGA Designer ) irfanfaisalmir@yahoo.com * Organized by Electronics Division Integrated Circuits Uses for digital IC technology
Outline. EECS Components and Design Techniques for Digital Systems. Lec 11 Putting it all together Where are we now?
Outline EECS 5 - Components and Design Techniques for Digital Systems Lec Putting it all together -5-4 David Culler Electrical Engineering and Computer Sciences University of California Berkeley Top-to-bottom
Model Checking. Automatic Verification Model Checking. Process A Process B. when not possible (not AI).
Sérgio Campos scampos@dcc.ufmg.br Why? Imagine the implementation of a complex hardware or software system: A 100K gate ASIC perhaps 100 concurrent modules; A flight control system dozens of concurrent
DIGITAL DESIGN TECHNOLOGY & TECHNIQUES
DIGITAL DESIGN TECHNOLOGY & TECHNIQUES CAD for ASIC Design 1 INTEGRATED CIRCUITS (IC) An integrated circuit (IC) consists complex electronic circuitries and their interconnections. William Shockley et
This Lecture. Some components (useful for the homework) Verilog HDL (will continue next lecture)
Last Lecture The basic component of a digital circuit is the MOS transistor Transistor have instrinsic resistance and capacitance, so voltage values in the circuit take some time to change ( delay ) There
System Debugging and Verification : A New Challenge. Center for Embedded Computer Systems University of California, Irvine
System Debugging and Verification : A New Challenge Daniel Gajski Samar Abdi Center for Embedded Computer Systems http://www.cecs.uci.edu University of California, Irvine Overview Simulation and debugging
EECS 219C: Formal Methods Binary Decision Diagrams (BDDs) Sanjit A. Seshia EECS, UC Berkeley
EECS 219C: Formal Methods Binary Decision Diagrams (BDDs) Sanjit A. Seshia EECS, UC Berkeley Boolean Function Representations Syntactic: e.g.: CNF, DNF (SOP), Circuit Semantic: e.g.: Truth table, Binary
EE 4755 Digital Design Using Hardware Description Languages
EE 4755 Digital Design Using Hardware Description Languages Basic Information URL: http://www.ece.lsu.edu/v Offered by: David M. Koppelman, Room 3316R P. F. Taylor Hall 578-5482. koppel@ece.lsu.edu, http://www.ece.lsu.edu/koppel/koppel.html
Verilog Module 1 Introduction and Combinational Logic
Verilog Module 1 Introduction and Combinational Logic Jim Duckworth ECE Department, WPI 1 Module 1 Verilog background 1983: Gateway Design Automation released Verilog HDL Verilog and simulator 1985: Verilog
ECE 551 Digital System Design and Synthesis. Instructor: Kewal K. Saluja. Midterm Exam
Last (family) name: First (given) name: Student I.D. #: Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE 551 Digital System Design and Synthesis Instructor: Kewal
Design Process. Design : specify and enter the design intent. Verify: Implement: verify the correctness of design and implementation
Design Verification 1 Design Process Design : specify and enter the design intent Verify: verify the correctness of design and implementation Implement: refine the design through all phases Kurt Keutzer
Testing & Verification of Digital Circuits ECE/CS 5745/6745. Hardware Verification using Symbolic Computation
Testing & Verification of Digital Circuits ECE/CS 5745/6745 Hardware Verification using Symbolic Computation Instructor: Priyank Kalla (kalla@ece.utah.edu) 3 Credits Mon, Wed 1:25-2:45pm, WEB 2250 Office
ECE 459/559 Secure & Trustworthy Computer Hardware Design
ECE 459/559 Secure & Trustworthy Computer Hardware Design VLSI Design Basics Garrett S. Rose Spring 2016 Recap Brief overview of VHDL Behavioral VHDL Structural VHDL Simple examples with VHDL Some VHDL
Computer Systems. Binary Representation. Binary Representation. Logical Computation: Boolean Algebra
Binary Representation Computer Systems Information is represented as a sequence of binary digits: Bits What the actual bits represent depends on the context: Seminar 3 Numerical value (integer, floating
CS 250 VLSI Design Lecture 11 Design Verification
CS 250 VLSI Design Lecture 11 Design Verification 2012-9-27 John Wawrzynek Jonathan Bachrach Krste Asanović John Lazzaro TA: Rimas Avizienis www-inst.eecs.berkeley.edu/~cs250/ IBM Power 4 174 Million Transistors
VHDL. VHDL History. Why VHDL? Introduction to Structured VLSI Design. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language
VHDL Introduction to Structured VLSI Design VHDL I Very High Speed Integrated Circuit (VHSIC) Hardware Description Language Joachim Rodrigues A Technology Independent, Standard Hardware description Language
Advanced Digital Design Using FPGA. Dr. Shahrokh Abadi
Advanced Digital Design Using FPGA Dr. Shahrokh Abadi 1 Venue Computer Lab: Tuesdays 10 12 am (Fixed) Computer Lab: Wednesday 10-12 am (Every other odd weeks) Note: Due to some unpredicted problems with
Specifying circuit properties in PSL
Specifying circuit properties in PSL Formal methods Mathematical and logical methods used in system development Aim to increase confidence in riktighet of system Apply to both hardware and software 1 Formal
Lecture 15: System Modeling and Verilog
Lecture 15: System Modeling and Verilog Slides courtesy of Deming Chen Intro. VLSI System Design Outline Outline Modeling Digital Systems Introduction to Verilog HDL Use of Verilog HDL in Synthesis Reading
תכן חומרה בשפת VERILOG הפקולטה להנדסה
תכן חומרה בשפת VERILOG סמסטר ב' תשע"ג משה דורון מרצה: מתרגלים: אריאל בורג, חג'ג' חן הפקולטה להנדסה 1 Course Topics - Outline Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types
(ii) Simplify and implement the following SOP function using NOR gates:
DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES PART A 1. How can an OR gate be
Advanced VLSI Design Prof. Virendra K. Singh Department of Electrical Engineering Indian Institute of Technology Bombay
Advanced VLSI Design Prof. Virendra K. Singh Department of Electrical Engineering Indian Institute of Technology Bombay Lecture 40 VLSI Design Verification: An Introduction Hello. Welcome to the advance
Verilog Coding Guideline
Verilog Coding Guideline Digital Circuit Lab TA: Po-Chen Wu Outline Introduction to Verilog HDL Verilog Syntax Combinational and Sequential Logics Module Hierarchy Write Your Design Finite State Machine
Property-based design with HORUS / SYNTHORUS
Property-based design with HORUS / SYNTHORUS Dominique Borrione, Negin Javaheri, Katell Morin-Allory, Yann Oddos, Alexandre Porcher Radboud University, Nijmegen 1 March 27, 2013 Functional specifications
ON THE EFFECTIVENESS OF ASSERTION-BASED VERIFICATION
ON THE EFFECTIVENESS OF ASSERTION-BASED VERIFICATION IN AN INDUSTRIAL CONTEXT L.Pierre, F.Pancher, R.Suescun, J.Quévremont TIMA Laboratory, Grenoble, France Dolphin Integration, Meylan, France Thales Communications
A Brief Introduction to Verilog Hardware Definition Language (HDL)
www.realdigital.org A Brief Introduction to Verilog Hardware Definition Language (HDL) Forward Verilog is a Hardware Description language (HDL) that is used to define the structure and/or behavior of digital
Two HDLs used today VHDL. Why VHDL? Introduction to Structured VLSI Design
Two HDLs used today Introduction to Structured VLSI Design VHDL I VHDL and Verilog Syntax and ``appearance'' of the two languages are very different Capabilities and scopes are quite similar Both are industrial
COE 561 Digital System Design & Synthesis Introduction
1 COE 561 Digital System Design & Synthesis Introduction Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Outline Course Topics Microelectronics Design
ECE 4514 Digital Design II. Spring Lecture 13: Logic Synthesis
ECE 4514 Digital Design II A Tools/Methods Lecture Second half of Digital Design II 9 10-Mar-08 L13 (T) Logic Synthesis PJ2 13-Mar-08 L14 (D) FPGA Technology 10 18-Mar-08 No Class (Instructor on Conference)
Introduction to Verilog/System Verilog
NTUEE DCLAB Feb. 27, 2018 Introduction to Verilog/System Verilog Presenter: Yao-Pin Wang 王耀斌 Advisor: Prof. Chia-Hsiang Yang 楊家驤 Dept. of Electrical Engineering, NTU National Taiwan University What is
Specifying circuit properties in PSL. (Some of this material is due to Cindy Eisner and Dana Fisman, with thanks) See also the Jasper PSL Quick Ref.
Specifying circuit properties in PSL (Some of this material is due to Cindy Eisner and Dana Fisman, with thanks) See also the Jasper PSL Quick Ref. Background: Model Checking property G(p -> F q) yes MC
Lecture #1: Introduction
Lecture #1: Introduction Kunle Olukotun Stanford EE183 January 8, 20023 What is EE183? EE183 is continuation of EE121 Digital Logic Design is a a minute to learn, a lifetime to master Programmable logic
ECE 156A - Syllabus. Description
ECE 156A - Syllabus Lecture 0 ECE 156A 1 Description Introduction to HDL (Hardware Description Language) basic elements, HDL simulation concepts, HDL concurrent statements with examples and applications,
Synthesis of Combinational and Sequential Circuits with Verilog
Synthesis of Combinational and Sequential Circuits with Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two
Digital Design with FPGAs. By Neeraj Kulkarni
Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic
Functional Programming in Hardware Design
Functional Programming in Hardware Design Tomasz Wegrzanowski Saarland University Tomasz.Wegrzanowski@gmail.com 1 Introduction According to the Moore s law, hardware complexity grows exponentially, doubling
System Correctness. EEC 421/521: Software Engineering. System Correctness. The Problem at Hand. A system is correct when it meets its requirements
System Correctness EEC 421/521: Software Engineering A Whirlwind Intro to Software Model Checking A system is correct when it meets its requirements a design without requirements cannot be right or wrong,
Lecture 32: SystemVerilog
Lecture 32: SystemVerilog Outline SystemVerilog module adder(input logic [31:0] a, input logic [31:0] b, output logic [31:0] y); assign y = a + b; Note that the inputs and outputs are 32-bit busses. 17:
An Industrially Useful Prover
An Industrially Useful Prover J Strother Moore Department of Computer Science University of Texas at Austin July, 2017 1 Recap Yesterday s Talk: ACL2 is used routinely in the microprocessor industry to
Digital System Design
Digital System Design Analog time varying signals that can take on any value across a continuous range of voltage, current or other metric Digital signals are modeled with two states, 0 or 1 underneath
CSE140L: Components and Design Techniques for Digital Systems Lab
CSE140L: Components and Design Techniques for Digital Systems Lab Tajana Simunic Rosing Source: Vahid, Katz, Culler 1 Announcements & Outline Lab 4 due; demo signup times listed on the cse140l site Check
EDA: Electronic Design Automation
EDA: Electronic Design Automation Luis Mateu Contents What is EDA The Phases of IC design Opportunities for parallelism 2006 Synopsys, Inc. (2) Electronic Design Automation? The software tools engineers
INDUSTRIAL TRAINING: 6 MONTHS PROGRAM TEVATRON TECHNOLOGIES PVT LTD
6 Month Industrial Internship in VLSI Design & Verification" with Industry Level Projects. CURRICULUM Key features of VLSI-Design + Verification Module: ASIC & FPGA design Methodology Training and Internship
Contemporary Design. Traditional Hardware Design. Traditional Hardware Design. HDL Based Hardware Design User Inputs. Requirements.
Contemporary Design We have been talking about design process Let s now take next steps into examining in some detail Increasing complexities of contemporary systems Demand the use of increasingly powerful
Introduction to CS 270 Math Foundations of CS
Introduction to CS 270 Math Foundations of CS Verification of Computer Systems Jeremy Johnson Drexel University Course Description Emphasizes analytic problem-solving and introduction of mathematical material
Boolean Algebra and Logic Gates
Boolean Algebra and Logic Gates Binary logic is used in all of today's digital computers and devices Cost of the circuits is an important factor Finding simpler and cheaper but equivalent circuits can
Tutorial on Model Checking Modelling and Verification in Computer Science
Tutorial on Model Checking Modelling and Verification in Computer Science Armin Biere Institute for Formal Models and Verification Johannes Kepler University, Linz, Austria Abstract. This paper serves
What is Verilog HDL? Lecture 1: Verilog HDL Introduction. Basic Design Methodology. What is VHDL? Requirements
What is Verilog HDL? Lecture 1: Verilog HDL Introduction Verilog Hardware Description Language(HDL)? A high-level computer language can model, represent and simulate digital design Hardware concurrency
Chapter 10. case studies in sequential logic design
Chapter. case studies in sequential logic design This is the last chapter of this course. So far, we have designed several sequential systems. What is the general procedure? The most difficult part would
ECE 353 Lab 3 (Verilog Design Approach)
ECE 353 Lab 3 (Verilog Design Approach) Prof Daniel Holcomb Recall What You Will Do Design and implement a serial MIDI receiver Hardware in an Altera Complex Programmable Logic Device (CPLD) MAX 7000S
VERILOG. Deepjyoti Borah, Diwahar Jawahar
VERILOG Deepjyoti Borah, Diwahar Jawahar Outline 1. Motivation 2. Basic Syntax 3. Sequential and Parallel Blocks 4. Conditions and Loops in Verilog 5. Procedural Assignment 6. Timing controls 7. Combinatorial
101-1 Under-Graduate Project Digital IC Design Flow
101-1 Under-Graduate Project Digital IC Design Flow Speaker: Ming-Chun Hsiao Adviser: Prof. An-Yeu Wu Date: 2012/9/25 ACCESS IC LAB Outline Introduction to Integrated Circuit IC Design Flow Verilog HDL
Digital System Design Lecture 2: Design. Amir Masoud Gharehbaghi
Digital System Design Lecture 2: Design Amir Masoud Gharehbaghi amgh@mehr.sharif.edu Table of Contents Design Methodologies Overview of IC Design Flow Hardware Description Languages Brief History of HDLs
Announcements. Midterm 2 next Thursday, 6-7:30pm, 277 Cory Review session on Tuesday, 6-7:30pm, 277 Cory Homework 8 due next Tuesday Labs: project
- Fall 2002 Lecture 20 Synthesis Sequential Logic Announcements Midterm 2 next Thursday, 6-7:30pm, 277 Cory Review session on Tuesday, 6-7:30pm, 277 Cory Homework 8 due next Tuesday Labs: project» Teams
Computer Aided Design Basic Syntax Gate Level Modeling Behavioral Modeling. Verilog
Verilog Radek Pelánek and Šimon Řeřucha Contents 1 Computer Aided Design 2 Basic Syntax 3 Gate Level Modeling 4 Behavioral Modeling Computer Aided Design Hardware Description Languages (HDL) Verilog C
Academic Course Description. VL2001 Digital System Design using Verilog First Semester, (Odd semester)
Academic Course Description SRM University Faculty of Engineering and Technology Department of Electronics and Communication Engineering VL2001 Digital System Design using Verilog First Semester, 2015-16(Odd
Logic Synthesis and Verification
Logic Synthesis and Verification Jie-Hong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 2013 Course Info Instructor Jie-Hong Roland Jiang email: jhjiang@cc.ee.ntu.edu.tw
Network Verification: Reflections from Electronic Design Automation (EDA)
Network Verification: Reflections from Electronic Design Automation (EDA) Sharad Malik Princeton University MSR Faculty Summit: 7/8/2015 $4 Billion EDA industry EDA Consortium $350 Billion Semiconductor
VERILOG HDL. (and C) 1 ENGN3213: Digital Systems and Microprocessors L#5-6
VERILOG HDL (and C) 1 ENGN3213: Digital Systems and Microprocessors L#5-6 Some Reference Material The following are suggested reading.. http://engnet.anu.edu.au/decourses/engn3213/documents/verilog/ VerilogIntro.pdf
Chapter 2. Boolean Algebra and Logic Gates
Chapter 2. Boolean Algebra and Logic Gates Tong In Oh 1 Basic Definitions 2 3 2.3 Axiomatic Definition of Boolean Algebra Boolean algebra: Algebraic structure defined by a set of elements, B, together
VLSI II E. Özgür ATES
VERILOG TUTORIAL VLSI II E. Özgür ATES Outline Introduction Language elements Gate-level modeling Data-flow modeling Behavioral modeling Modeling examples Simulation and test bench Hardware Description
VHDL VS VERILOG.
1 VHDL VS VERILOG http://www.cse.cuhk.edu.hk/~mcyang/teaching.html 2 VHDL & Verilog They are both hardware description languages for modeling hardware. They are each a notation to describe the behavioral
In the previous lecture, we examined how to analyse a FSM using state table, state diagram and waveforms. In this lecture we will learn how to design
1 In the previous lecture, we examined how to analyse a FSM using state table, state diagram and waveforms. In this lecture we will learn how to design a fininte state machine in order to produce the desired
In the previous lecture, we examined how to analyse a FSM using state table, state diagram and waveforms. In this lecture we will learn how to design
In the previous lecture, we examined how to analyse a FSM using state table, state diagram and waveforms. In this lecture we will learn how to design a fininte state machine in order to produce the desired
Nikhil Gupta. FPGA Challenge Takneek 2012
Nikhil Gupta FPGA Challenge Takneek 2012 RECAP FPGA Field Programmable Gate Array Matrix of logic gates Can be configured in any way by the user Codes for FPGA are executed in parallel Configured using
EECS150 - Digital Design Lecture 20 - Finite State Machines Revisited
EECS150 - Digital Design Lecture 20 - Finite State Machines Revisited April 2, 2009 John Wawrzynek Spring 2009 EECS150 - Lec20-fsm Page 1 Finite State Machines (FSMs) FSM circuits are a type of sequential
Boolean Algebra. BME208 Logic Circuits Yalçın İŞLER
Boolean Algebra BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com 5 Boolean Algebra /2 A set of elements B There exist at least two elements x, y B s. t. x y Binary operators: +
EE3032 Introduction to VLSI Design
EE3032 Introduction to VLSI Design Jin-Fu Li Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering National Central University Jhongli, Taiwan Contents Syllabus Introduction to CMOS
Introduction to synthesis. Logic Synthesis
Introduction to synthesis Lecture 5 Logic Synthesis Logic synthesis operates on boolean equations and produce optimized combinational logic Logic Minimization Two-level logic minimization Two-level logic
Verilog. Verilog for Synthesis
Verilog Verilog for Synthesis 1 Verilog background 1983: Gateway Design Automation released Verilog HDL Verilog and simulator 1985: Verilog enhanced version Verilog-XL 1987: Verilog-XL becoming more popular
HECTOR: Formal System-Level to RTL Equivalence Checking
ATG SoC HECTOR: Formal System-Level to RTL Equivalence Checking Alfred Koelbl, Sergey Berezin, Reily Jacoby, Jerry Burch, William Nicholls, Carl Pixley Advanced Technology Group Synopsys, Inc. June 2008
Boolean Representations and Combinatorial Equivalence
Chapter 2 Boolean Representations and Combinatorial Equivalence This chapter introduces different representations of Boolean functions. It then discusses the applications of these representations for proving
EECS 3201: Digital Logic Design Lecture 4. Ihab Amer, PhD, SMIEEE, P.Eng.
EECS 32: Digital Logic Design Lecture 4 Ihab Amer, PhD, SMIEEE, P.Eng. What is a HDL? A high-level computer language that can describe digital systems in tetual form Two applications of HDL processing:
Combinational Logic II
Combinational Logic II Ranga Rodrigo July 26, 2009 1 Binary Adder-Subtractor Digital computers perform variety of information processing tasks. Among the functions encountered are the various arithmetic
EE 4755 Digital Design Using Hardware Description Languages
EE 4755 Digital Design Using Hardware Description Languages Midterm Exam Review When / Where Monday, 16 October 2017, 9:30-10:20 CDT 225 Tureaud Hall (Here) Conditions Closed Book, Closed Notes Bring one
CS61C Machine Structures. Lecture 1 Introduction. 8/27/2006 John Wawrzynek (Warzneck)
CS61C Machine Structures Lecture 1 Introduction 8/27/2006 John Wawrzynek (Warzneck) (http://www.cs.berkeley.edu/~johnw/) http://www-inst.eecs.berkeley.edu/~cs61c/ CS 61C L01 Introduction (1) What are Machine
EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013
EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013 Print Here Student ID Signature This is a closed book exam. The exam is to be completed in one-hundred ten (110) minutes. Don t use scratch
WELCOME TO. ENGR 303 Introduction to Logic Design. Hello my name is Dr. Chuck Brown
Chapter 1 WELCOME TO Introduction to Logic Design Hello my name is Dr. Chuck Brown Please sign in and then find a seat. The person next to you will be your lab partner for the course so choose wisely and
KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT
KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:00-11:50AM Class