Verilog. What is Verilog? VHDL vs. Verilog. Hardware description language: Two major languages. Many EDA tools support HDL-based design

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1 Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two major languages Verilog (IEEE 1364), latest version is Verilog 2001 VHDL Many EDA tools support HDL-based design VHDL vs. Verilog Both recognised standards, widely used Allow flexibility, multiple targets, reuse Similar capabilities VHDL has Ada based syntax Verilog has C based syntax

2 Requirements of HDLs Must support modeling, simulation, synthesis, verification and testability Support various levels of abstraction: switch, gate, behavioural, algorithmic Model gate delays, concurrency, Should support practical aspects such as testability analysis Structural and behavioural modelling Verilog supports both Structural models: declaration of components (e.g. gates) and their interconnections (e.g. wires) Not well suited for modelling-based simulation and verification Behavioural models: Abstract models of the function and sequence Well matched to simulation for testing Compilation/ Synthesis Libraries/ IP Test/ Verification Compilation/Synthesis: Automates exploration and insertion of implementation details for lower level. System specification System synthesis Hw/Sw/ OS Model simulat./ checkers Behavioral specification Behavior synthesis Cores Hw-Sw cosimulators Libraries/IP: Incorporates pre-designed implementation from lower abstraction level into higher level. RT specification RT synthesis RT components HDL simulators Test/Verification: Ensures correct functionality at each level, thus reducing costly iterations between levels. Logic specification Logic synthesis Gates/ Cells Gate simulators To final implementation

3 Uses of Verilog in the design process System design and architecture: At a high level, Verilog can model aspects of the complete system Other tools may be better suited for system level modelling Verilog supports abstract behavioural modeling for system analysis and partitioning. Uses of Verilog in the design process Design and synthesis Given an overall system architecture and partitioning is stable one can capture the design Work at many level typically at the register transfer level. Synthesis tools convert RTL to gate level circuits. Large designs require working at high level automation to minimise time to market -> RTL should be synthesizable Uses of Verilog in the design process Simulation and verification Design needs to be simulated and verified Especially true for ASIC designs where implementation in hardware is expensive and requires significant time to convert to H/W Verilog can describe test benches (test vectors and expected results) and support results comparison and analysis.

4 Uses of Verilog in the design process Test cases must have sufficient coverage Generation of test benches is difficult and time consuming Simulation is used to verify that design meets specifications. Typically two levels Functional simulation tests RTL logic. This is fast and can allow for rapid and extensive testing of function. Gate level timing simulation verifies timing specifications but is time intensive Verilog for design synthesis Verilog originally designed for event-driven logic simulation and support high level behavioural and structural modelling Models can be synthesised or transformed in to gate or transistor level logic circuits; HDL based synthesis is widely used in modern design But for automated synthesis only a subset of the language is currently used Not all Verilog constructs are synthesizable (can be automatically or efficiently converted to hardware) Code style for synthesis differs from coding style in computer software programs

5 Typically design at the RTL level of abstraction as lowest level of abstraction is used for functional simulation Synthesised to gate level for use by the CAD tools Levels of abstraction for design entry Switch level (typically too detailed) Gate level entry (used for detailed design) Truth table entry (not common) Boolean equations or register transfer level Most common with current technology Higher level behavioural and algorithmic modelling for abstract design and verification increasingly supported for synthesis. Verilog Language

6 Structural models Basic building block is the module Modules can declare instances of other modules and connect them together Structural elements can be A number of primitive elements (n-input and, nand, or, nor, xor, xnor gates plus tristate variants) Library modules User defined modules e.g. structural modeling with primitives Module Add_half(sum, c_out, a, b) input a,b; output c_out, sum; xor(sum, a, b); and(c_out,a,b); Endmodule; Add_half a(s,c,x,y); // use Modules define functionality of a component and ports 3 types of ports input output bi-directional (inout) Begins with keyword module ends with endmodule

7 When instantiating the module, ports must be consistent with order in the declaration Option use formal names explicitly Add_half(.b (x),.a (y),.sum (s),.c_out (co)); Verilog names and parameters are case sensitive Indentifiers are alphanumeric, can t start with $ or a digit. There is a set of reserved words. // a single line comment /* multiline comment */ Data types for synthesis Wire a connection or bus between ports Module inputs are typically wires Tri is similar to wire (a net) but tri-state Reg Used for data that must be stored Module outputs are usually reg Results of procedural statements

8 Vectors e.g. sum[3:0] lowest four bits of sum Declararations input [7:0] x, y; reg [7:0] x, y; // array reg s; // single bit wire [7:0] my_bus; // a bus Literals Format <SIZE><BASE><VALUE> Size is number of bits Base is binary ( b), octal ( o), decimal ( d) and hex ( h) e.g. 2 b10 4 hf (4 b1111) 4 b11xx 4 valued logic. Verilog supports four different values for signals 0 1 x don t care, initial state of registers in simulation z high-impedance Also support for open-collector and emitter follower outputs

9 Operators Arithmetic: +, -, /, *, % Comparative: >, <, >=, <= Logical:!, &&,, = =,!=, = = =,! = = Bitwise: ~, &,, ^ Shift: >>, << Conditional:? Concatenation { } A = 1; B =0; Then {A, B} is 10 Verilog hardware design is usually a combination of behavioural modelling with some structural elements Other modules can be instantiated and connected with nets (wire, tri ) Behavioural modeling based on concurrent, event-triggered processes Always blocks Based on triggering event Change state of reg variables

10 Assign statement associates a net with registers and other nets All assign statements are executed concurrently (with each other and with any always statements) Useful for datapath operations assign data = a & b; Procedural (or sequential) statements Always statement contains procedural statements conditioned on an event Can be used for combinational and sequential logic clk or clr) begin end or B) Part after known as sensitivity list, specify a signal or transition) Assignments inside a always statement (or initial for simulations) are known as procedural assignments. LHS of procedural assignment must be a register variable (not wire) Two types blocking and non-blocking

11 Blocking Each statement is evaluated in order using current values of the RHS variables B =!A; C = B; If A and B both are 0 at start of assign statement then both B and C will be 1 after this statement Non-blocking Executes sequentially but using values of the RHS variable that existed at the start of the always block Effectively executed concurrently B <=!A; C <= B; If A and B both are 0 at start of assign statement then B will be 1 and C will be 0 Non-blocking statements typically used for sequential circuits where all flip-flops change state synchronously Blocking statements for combinational circuits

12 Procedural constructs if-then-else if (C == 1) begin statements.. end else begin statements.. end Be careful, spurious latches can be synthesised. Make sure you specify else part. Can be nested or paired as else if case case (X) begin 2 b00: A = 2 b10; 2 b10: A = 2 b11; default: A = 2 b00; endcase Be careful, spurious latches can be synthesised. Make sure you specify default or all options. casex and casez allow for don t care and tristate Lots of other constructs fork, join, initial, for useful for modeling but not usually supported for synthesis