Hardware Design Verification: Simulation and Formal Method-Based Approaches William K Lam Prentice Hall Modern Semiconductor Design Series

Transcription

1 Design Verification An Introduction

2 Main References Hardware Design Verification: Simulation and Formal Method-Based Approaches William K Lam Prentice Hall Modern Semiconductor Design Series A Roadmap for Formal Property Verification Pallab Dasgupta Springer Course Web: and follow link to courses Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 2

3 Design, Validation and Testing Specification Pre-silicon Post-silicon Implementation Prototyping Manufacturing Design synthesis and validation Manufacturing and testing Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 3

4 Design and Verification Design Specification Implementation Equivalent? Verification Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 4

5 Digital Design: Abstraction Levels Exponential growth in circuit size (Moore s Law) Gate Level Register Transfer Level posedge clk ) begin if (!rst) begin a1 <= a2; a2 <= ~a1; end; end Formalisms introduced at the Entry-Level Restricted semantics of Programming Languages, Communicating Concurrent State Machines (CSM) Boolean Logic Finite State Machines Transistor Level Schematic Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 5

6 Design Example: 2-bit Gray Counter Gray Counter: Successive values should differ only in one bit. Reset signal resets the counter to zero. rst rst rst s 0 s 1 00!rst 01 clk rst!rst rst!rst 10 11!rst State m/c Representation Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 6

7 Design Example: 2-bit Gray Counter rst s 0 s 1 State Transition Table (s 0 s 1 ) rst (n 0 n 1 ) rst 00 clk rst!rst rst!rst rst!rst !rst State m/c Representation Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 7

8 Design Example: 2-bit Gray Counter State Transition Table (s 0 s 1 ) rst (n 0 n 1 ) State Transition Functions: n 0 = s 0 s 1 r + s 0 s 1 r n 1 = s 0 s 1 r + s 0 s 1 r After Logic Minimization: n 0 = s 1 r n 1 = s 0 r Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 8

9 Design Example: 2-bit Gray Counter State Transition Functions: n 0 = s 1 r n 1 = s 0 r Verilog Code (RTL): module GrayCounter(s0, s1, rst) input rst; reg s0, s1; rst s 0 (posedge clk) begin s0 <= s1 & ~rst; s1 <= ~s0 & ~rst; end endmodule Synthesis clk s 1 Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 9

10 Abstractions in Design Flow higher Functional Specification less Algorithmic Description abstraction RTL Gate Netlist details Transistor Netlist lower Physical Layout more Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 10

11 Design and Verification design specifications does it meet the specs? micro-architecture does it implement the -arch? RTL are they equivalent? property checking verification gate netlist layout are they equivalent? equivalence checking Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 11

12 Design Flows: Digital versus Analog Design Concept Design Entry Verilog / VHDL Behavioral Simulation Synthesis Place & Route Post-Layout Simulation Schematic Entry Spice Simulation Custom Layout DRC Extract netlist Post-Layout Simulation SDL Full Chip Assembly Full Chip DRC Full Chip Simulation Tape Out DRC: Design Rule Checking SDL: Schematic Driven Layout Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 12

13 Design Cycle: Implementation Specs Document RTL implementation Verilog, VHDL Equivalence checking English documents Design integration Synthesis Gate Level Netlist Implementation validation (Spec vs RTL) Technology mapping Layout Transistor Level (Schematic) Mask Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 13

14 Verification Dominates Design Emulation 15% Structural 12% Synthesis Timing analysis Equivalence checking DFT Simulation 46% Behavioral modeling Architecture level simulation System level simulation Design 27% High-level design RTL coding Block-level simulation Source: 0-In Design Automation Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 14

15 Pieces of the verification puzzle Architecture validation Timing validation Unit validation Microcode validation Cluster validation Debugging validation Full-chip validation Protocol validation Power validation Picture source:skulladay.com Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 15

16 Design and Verification design specifications does it meet the specs? micro-architecture does it implement the -arch? RTL are they equivalent? property checking verification gate netlist layout are they equivalent? equivalence checking Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 16

17 Functional Verification Challenge Is the implementation correct? How do we define correct? Classical: Simulation result matches with golden output Formal: Equivalence with respect to a golden model Property verification: Correctness properties (assertions) expressed in a formal language Formal: Model checking Semi-formal: Assertion-based verification Trade-off between computational complexity and exhaustiveness Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 17

18 Simulation Design Test Plan Test Bench Stimulus Generation Simulation Coverage Metrics Debug Bug Tracking Advances: Test bench languages are richer (such as SystemVerilog) Coverage monitors and assertions Layered test benches and Transaction Level Modelling Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 18

19 Advent of Formal Methods in EDA Goal: Exhaustive verification of the design intent within feasible time limits Philosophy: Extraction of formal models of the design intent and the implementation and comparing them using mathematical / logical methods Formal Properties posedge clk ) begin if (!rst) begin a1 <= a2; a2 <= ~a1; end; end Design Intent Register Transfer Level Gate Level Model Checking Logical Equivalence Checking Temporal Logics (Turing Award: Amir Pnueli) Adopted by Accelera / IEEE Integrated into SystemVerilog Tools: Academia: NuSMV, VIS Industry: Magellan (Synopsys) IFV (Cadence) 2008: Clarke & Emerson get Turing Award Transistor Level Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 19

20 Toy example: Priority Arbiter r1 r2 g1 g2 Either g1 or g2 is always false (mutual exclusion) G[ g1 g2] Whenever r1 is asserted, g1 is given in the next cycle G[ r1 Xg1 ] When r2 is the sole request, g2 comes in the next cycle G[ ( r1 r2) Xg2 ] When none are requesting, the arbiter parks the grant on g2 G[ ( r1 r2) Xg2 ] Violation!! Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 20

21 Dynamic Property Verification (DPV) [Source: A Roadmap for Formal Property Verification, Springer, 2006] Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 21

22 Formal Property Verification (FPV) always!g1!g2 always r2 &&!r1 next g2 Formal Properties Temporal Logics (Timed / Untimed, Linear Time / Branching Time): LTL, CTL Early Languages: Forspec (Intel), Sugar (IBM), Open Vera Assertions (Synopsys) Current IEEE Standards: SystemVerilog Assertions (SVA), Property Specification Language (PSL) Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 22

23 Assertion Based Verification Flow Refine the model or assertions Modify assumptions NO Spurious YES Decompose, Abstract, Over Constrain cex YES NO Model + Properties Model Checker Indeterminate Results PASS NO YES Stuck? None of the Abstractions working Bug Hunting (Directed Simulation assisted MC) Closure? [Source: Raj Mitra, TI] Pallab Dasgupta, Dept. of Computer Sc & Engg, IIT Kharagpur 23