FPGA Based Antilog Computation Unit with Novel Shifter

Transcription

1 International Journal of Engineering Trends and Technology (IJETT) Volume 3 Number 3- January 6 FPGA Based Antilog Computation nit with Novel Shifter Swapna Kalyani P #, Lakshmi Priyanka S *, Santhosh S Kiran K #3, urali Krishna P * #.Tech Scholar & VLSI ES & KIETW, India * # Asst.Professor & Dept. of ECE & KIETW, India Abstract- Technology demands improvements in area, speed and power day by day. odern FPGAs are the best-suited devices for implementing complex applications that provides optimized design with minimal cost when compared to ASICs. This project presents an efficient architecture for fixed point binary antilogarithmic computation that uses a piecewise linear approximation method to generates the approximation coefficients that works for both positive and negative real numbers. Logarithmic Number System (LNS) based implementation is less complex, has small gate counts and high operational speed. In the proposed design, a novel shifter is used to perform required number of shifts either in left or right direction and generates integer and fractional part separately IP cores are utilized to serve various tasks. Error analysis shows that the proposed design provides highest accuracy for both positive and negative numbers with least percentage error of. and.3 respectively. The design is implemented on ilinx Virtex-5 xc5vfxt device and the maximum operational frequency of 39.58Hz is achieved. Keywords FPGAs, ASICs, LNS, Antilogarithm, Piecewise linear, IP Cores I. INTRODCTION Present day embedded applications like signal, image, video processing demand implementations with less area and high accuracy. Implementing complex arithmetic functions such as power, square root, division, etc in VHDL using floating-point number format is area and power consuming, and works very slow [-3], whereas a fixed point format, which has simple datapath, is best-suited for such applications because of its remarkable fractional accuracy. Fixed point datapath circuits also perform fast with less area and power consumption [-3]. LNS is best suited for such implementations [3-6]. FPGAs overtake ASICs because of its minimal design time and less time to market, which is costeffective. Latest FPGAs have built-in components such as multipliers, adders, memories, communication and networking devices, mathematical models etc. With fixed-point number format, implementing complex arithmetic functions become easy using logarithmic number system. []... [6] [5]... [] To perform simple arithmetic operations, the input numbers are first converted into their log equivalents. The result is then converted back to its original form using antilogarithmic conversion. Input data Fig. Arithmetic Computations using LNS Output data Arithmetic simplicity can be achieved at the cost of overhead for conversion, which is very small for many embedded applications. [-8] presents antilog approximation without any hardware implementation. A 6-bit COS based antilog converter architecture is discussed in [9], that works only for positive numbers. A -bit antilog converter was presented in [] that uses less regions for approximation. In [], architecture generates the antilog of given number in a single output of size bits that include both integer part and fraction part with an error percentage of.6 for positive and.8 for negative numbers. The proposed design uses piecewise linear approximation to calculate the approximation coefficients by using curve fitting method. The architecture for generating antilog of fraction part is quite similar with that of [], but uses a new shifter design that generates two separate outputs one for integer part and one for fraction part in contrast with the barrel shifter that generates a mixed output for integer and fraction. As a result of separate outputs, bits needed for representing them have increased. Hence, error is reduced by more than 5%. The design is implemented on ilinx Virtex-5 xc5vfxt device. The architecture uses off-the shelf components like multipliers and adders. II. APPROIATION APPROACH Fixed point number format is used to represent the antilogarithmic approximation coefficients. Piecewise linear approximation method is used to approximate the coefficients. A. Fixed point Number Format Architecture for fixed point arithmetic is less complex when compared to floating point. Hence, it occupies less area and consumes less power. The proposed architecture uses a Q..6 format as shown in the figure. In that format,, and 6 denotes number of bits allotted for sign, integer part and fraction part respectively. SSN: Page 6

2 FPA SHIFTER International Journal of Engineering Trends and Technology (IJETT) Volume 3 Number 3- January 6 Sign bit integer part 6 bit fraction part Fig. Fixed point number format B. Computation of Approximation Coefficients Piecewise linear approximation is best suited to achieve area efficient implementation. Let be a bit binary number([:]) with a Q notation of..6 in fixed point format, in the range 6. Any number can be expressed as integer part and fraction part. (e.g. 8.56= 8+.56). Let integer part is denoted with k and fraction part with f. If SB []=, input number is positive, else negative. Based on the fixed-point number format, the computation of antilogarithmic value is as given in (): Antilog () = = k. f () The fractional data (f) is approximated in the range of f <. k and f values depend on sign bit of the given number. For positive number, sign bit is, k and f values remain unchanged. For a negative number, sign bit is, f goes out of range. Hence, k is decremented by and f is subtracted from as shown in (). () Antilog of a given input number is calculated from (), theoretically. Designing an architecture for computing the same requires some approximation method such that its output will be as close as possible with the theoretical value. III. ARCHITECTRE FOR ANTILOG NIT Fig shows the complete architecture of the antilogarithmic computation unit. ultiplexers supply select values of integer part and fraction part to the succeeding blocks, depending on the sign bit. In fig, Sel ux () and Sel ux (L) selects k ([9:6]) and f ([5:]) if [] = and k- and -f if []= respectively. The output of sel mux () is given to shifter and sel mux (L) to fractional part approximation unit (FPA). The output of FPA is then fed to shifter. This block generates two outputs, one for integer and one for fraction. Hence, the approximation is termed piecewise linear. This is used to approximate the f vs f curve. f = m i.f + c i (3) Fig. 3 Architecture for Antilog Approximation nit where i that represents eight piecewise linear regions. m i and c i are approximation coefficients to be computed for all values of i. Hence, eight sets of m and c values (m & c to m & c ) are obtained. These coefficients may be generated in many ways. In this design, curve fitting tool box (cftool) in matlab is used to generate the approximation coefficients. Therefore, obtained values are very accurate. Each set of m (Q.) & c (Q.) values are combined into a 9-bit data and stored in eight locations of a 9 8 RO. The RO content is as shown below. Location - + SEL () SEL (L) TABLE I: RO CONTENT RO Address m Coefficients These m and c values are then converted into hexadecimal equivalents and written in a.coe file and loaded into RO IP Core, which supplies the same to fixed point multiplier and fixed point adder for the computation of fractional part. The architecture for FPA unit is shown in fig. c SSN: Page 65

3 International Journal of Engineering Trends and Technology (IJETT) Volume 3 Number 3- January 6 Selection Lines TABLE II: SHIFTER ROTING DATA Integer ux Fraction ux K[3:] []= []= []= []= int shr appends necessary number of zeroes in the least significant positions in order to convert it into a bit value. This is applied as one input to ex-or gate and second input is the FPA output. int int int 3 shr shr 3 shr Int Int Int int int 5 int 6 int int 8 int 9 int int int int 3 int shr 5 shr 6 shr shr 8 shr 9 shr shr shr shr 3 shr shr 5 Int 3 Int Int5 Int6 Int Int8 Int 9 Int Int Int Int3 Int Int m p Fp Leading s Detector EOR CONCAT BLOCK s (6:) INT Int_out A. Shifter int 5 F>>5 The output of FPA block consists of final output but with mixed integer and fraction parts which are difficult to distinguish because decimal point can t be denoted in the output. This task is handled by the shifter block. In the proposed design, shifter block [5:] FP ul FP Add + m (8 bit) 9 c R O Shr Shr Shr3 Shr Shr5 Shr6 Shr Shr8 Shr9 Shr Shr Shr Shr3 Shr Shr5 Shr F(6:) q Fp F [:] F_out FPA_OT Fig. Fractional Part Approximation nit generates two outputs integer and fraction separately. 6 possible integer values ( to 5) are made ready at the input of mux chain that selects the corresponding integer value depending on output of sel mux (). The selected integer is then fed to a leading detector so that the unwanted bits in the most significant position may be neglected and also K3 K K K Fig. 5 Architecture for Proposed Shifter Block SSN: Page 66

4 International Journal of Engineering Trends and Technology (IJETT) Volume 3 Number 3- January 6 The result of FPA is again appended with 5 zeroes to make the result bit. This -bit representation improves the fractional part accuracy a lot when compared with that in []. Inputs int to int 5 of mux and Shr to Shr 5 of mux are signals of size -bits and -bits generated after appropriate left and right shifting of FPA output respectively. Fig and fig 8 shows the simulation results with the obtained values for positive and negative numbers in binary form, respectively. IV. IPLEENTATION RESLTS Fig 6 shows technology schematic of the antilog approximation unit. It uses very less FPGA resources. Table III shows the data corresponding to both positive and negative numbers. It is evident that difference between expected and obtained results is very less. The expected values are calculated from [-3]. TABLE III: COPARISON OF RESLTS Decimal Number Q..6 notation Antilog of input Expected Obtained Fig. Simulation Result of Antilog block for a positive number input Fig. 8 Simulation Result of Antilog block for a negative number input. This difference in terms of error percentage is shown in table IV. The values prove that proposed design is far better than the existing design. Fig. 6 Technology Schematic of the proposed architecture Input Number TABLE IV: ERROR ANALYSIS Percentage of Error Existing Proposed +ve.6. -ve.8. SSN: Page 6

5 International Journal of Engineering Trends and Technology (IJETT) Volume 3 Number 3- January 6 Table V shows the resource utilization summary of the ilinx Virtex-5 5vfxt FPGA device. The detail states that the architecture uses.66% of the available LTs on virtex-5 device. It also uses IP Cores, multiplier and adder. TABLE V: DEVICE TILIZATION SARY Elements Slice LTs External IO Blocks IP Cores sed V. CONCLSIONS An FPGA-based architecture for binary antilog approximation unit is proposed. The design is implemented in ilinx Virtex- 5 xc5vfxt FPGA. FPA unit utilizes a built-in adder and a mutliplier to design fixed-point datapath. The characteristic portion of the binary number shifts the mantissa using a novel shifter that uses multiplexers and extra logic to generate the required outputs, which are the final results and are closest approximations to the original value. The error can be further reduced by using quadratic polynomial to approximate the antilog curve and also by increasing number of bits allocated for fraction part in the Q notation of input number. REFERENCES Proposed Architecture 9/8 (.66%) /6 (%) ultiplier- Adder- [] J. R. Parker, Algorithms for Image Processing and Computer Vision, nd ed. Wiley Publishing Inc.,. [] J. H. Sohn, R. Woo, and H. J. Yoo, A programmable vertex shader with fixed-point SID datapath for lo w power wireless applications, in Proceedings of the AC SIGGRAPH/EROGRAPHICS conference on Graphics hardware, Sarajevo, Bosnia-Herzegovina,, p.. [3] J. G. Pandey, A. Karmakar, and C. G. S. Shekhar, An FPGA-based fixed-point architecture for binary logarithmic computation, nd IEEE International Conference in Image Information Processing (ICIIP), Shimla, India, 9- Dec. 3. [] H. Kim, B. G. Nam, J. H. Sohn, J. H. Woo, and H. J. Yoo, A 3-Hz,.8-mW -bit logarithmic arithmetic unit for fixed-point 3-D graphics system, IEEE Journal of Solid-State Circuits, vol., no., pp , 6, DOI:.9/JSSC [5] H. Tian, T. Srikanthan, and K. V. Asari, Automatic segmentation algorithm for the extraction of lum n region and boundary from endoscopic images, edical and Biological Engineering and Computing, vol. 39, no., pp. 8-,, DOI:./BF356. [6] H. Kim, B. G. Nam, J. H. Sohn, J. H. Woo, and H. J. Yoo, A 3-Hz,.8-mW -bit logarithmic arithmetic unit for fixed-point 3-D graphics system, IEEE Journal of Solid-State Circuits, vol., no., pp , 6, DOI:.9/JSSC [] J. N. itchell, Computer multiplication and division using binary logarithm, IRE Trans. Computer, vol. EC-, pp. 5-5, 96 [8]. Combet, H. Zonneveld, and L. Verbeek, Computation of the base two logarithm of binary numbers, IEEE Transactions on Electronic Computers, vol. EC-, no. 6, pp , Dec. 965, DOI:.9/PGEC [9] K. H. Abed and R. E. Siferd, COS VLSI implementation of 6-Bit logarithm and anti-logarithm converters, in Proceedings of the 3rd IEEE idwest Symposium on Circuits and Systems, vol., Lansing, I, SA,, pp. 6-9 [] K. H. Abed and R. E. Siferd, VLSI implementation of a low-power antilogarithmic converter, IEEE Transactions on Computers, vol. 5, no. 9, pp. -8, 3, DOI:.9/TC [] J. G. Pandey, A. Karmakar, C. Shekhar and S. Gurunarayanan, An FPGA based Novel Architecture for fixed point binary antilogarithmic computation, International Conference on Electronic Systems, Signal Processing and Computing Technologies(ICESC),. [] [3] Google Calculator [Online] SSN: Page 68