Binary Counter v8.0. Features. Functional Description. Pinout. DS215 April 28, Product Specification

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1 0 Binary Counter v8.0 DS215 April 28, Features Drop-in module for Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Spartan -II, Spartan-IIE, Spartan-3, and Spartan-3E FPGAs Generates Up, Down and Up/Down Counters Supports counters ranging from 2 to 30 bits wide Optional load capability Optional user programmable threshold outputs Optional clock enable and asynchronous and synchronous controls Counter increment value can be user defined User-programmable count limit For use with CORE Generator system v7.1i Service Pack 2 or higher Incorporates Xilinx Smart-IP technology for utmost parameterization and optimum implementation Functional Description The binary counter is used to create up counters, down counters, and up/down counters with outputs of up to 30 bits wide. Support is provided for one threshold signal that can be programmed to become active when the counter reaches a user defined count. The upper limit of the count is user programmable and the counter s increment value can be user defined. Options are provided for Clock Enable, Asynchronous Set, Clear, and Init, and Synchronous Set, Clear and Init. An optional Load capability is also provided which can load the value on the Load port directly into the output register. When the counter reaches terminal count or the count to value the next count will be zero. Pinout Figure 1: Core Schematic Symbol Signal names for the schematic symbol are shown in and described in Table1. Table 1: Core Signal Pinout Signal Direction Description CLK Input Clock - rising edge clock signal UP Input Controls the count direction on an up/down counter. Counts Up when High, Down when Low CE Input Clock Enable IV[N:0] Input Unused; for backwards compatibility only L[N:0] Input Load data port LOAD Input Load Control signal ACLR Input Asynchronous Clear - forces outputs to a Low state when driven 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. DS215 April 28,

2 Table 1: Core Signal Pinout (Continued) Signal Direction Description SCLR Input Synchronous Clear - forces the registered output to a Low state on next concurrent clock edge ASET Input Asynchronous Set - forces the registered output to a High state when driven SSET Input Synchronous Set - forces the registered output to a High state on next concurrent clock edge AINIT Input Asynchronous Initialize - forces the registered outputs to a user defined state when driven SINIT Input Synchronous Initialize - forces the registered outputs to a user defined state on next concurrent clock edge THRESH0 Output User programmable threshold signal Q_THRESH0 Output Registered user programmable threshold signal THRESH1 Output Unused; This feature has been deprecated. It remains on the port map for backwards compatibility only Q_THRESH1 Output Unused; as for THRESH1 Q[N:0] Output Output Notes: All control inputs are Active High. Should an Active Low input be required for a particular control pin an inverter must be placed in the path to the pin. The inverter will be absorbed appropriately during mapping. XCO and VHDL Generic Parameters XCO parameters and VHDL generics are broadly equivalent. Table2 describes the parameters, legal values and meaning of each. The descriptions below refer to the VHDL generic parameters. The main generic parameters are as follows: c_width(integer): Specifies the width of the counter. The valid range is 2 to 30. The default value is 16. c_restrict_count(integer): When this generic is 1 the counter will only count up (or down) to the value specified in the c_count_to generic. When it is 0 the counter will count up to the maximum value that can be represented using the specified output width.the default is for no count restriction. This option is mutually exclusive with the up/down counter option, and with asynchronous or synchronous set controls. c_count_to(string): When c_restrict_count = 1, this generic specifies the binary representation of the upper limit of the counter. The valid range for values is 1 to 2 c_width - 2. c_count_by(string): Specifies in binary the increment value of the counter. When c_restrict_count is 0 the valid range is 1 to 2 c_width - 1. When c_restrict_count is 1 the valid settings for c_count_by are governed by the equation: c_count_to / c_count_by = Integer for up counters, and: 2 c_width - c_count_to / c_count_by = Integer for down counters. The default value is 1. c_count_mode(integer): This generic specifies whether the counter will count up, down, or will have its direction specified on the UP pin (up/down). The valid values are c_up, c_down, or c_updown. c_has_up(integer): This generic specifies if an UP pin is to be present. It should equal 1 for up/down counters, and 0 for other counters. c_has_iv(integer): The counter used to support variable increment but this facility is deprecated. This generic should equal 0. For an alternative to allow for variable increment, see the Accumulator baseblock data sheet. Asynchronous Settings: All asynchronous controls are implemented using the dedicated inputs on the flip-flop primitives. The relevant generics are: - c_has_aclr (integer): Specifies if an ACLR pin is to be included. Valid values are 1 or 0, default is 0. - c_has_aset(integer): Specifies if an ASET pin is to be included. ASET is not allowed with restricted counters. If both ACLR and ASET are present, ACLR takes precedence. Valid values are 1 or 0, default is 0. - c_has_ainit(integer): Specifies if an AINIT pin is to be included which, when asserted, will asynchronously set the counter value to the value defined by c_ainit_val. Note that if AINIT is present, then neither ASET nor ACLR may be present. Valid values are 1 or 0, default is 0. - c_ainit_val(string): Specifies in binary the value the counter will initialize to when AINIT is asserted. Valid values are 0 up to 2 c_width - 1 for unrestricted counters, and 0 up to c_count_to for restricted counters. C_ainit_val is used as the power on value if the counter has no reset controls or only 2 DS215 April 28, 2005

3 ainit. Otherwise, c_ainit_val is ignored if c_has_ainit = 0. Synchronous Settings: Synchronous settings are whenever possible implemented using the dedicated inputs on the flip-flop primitives. The relevant generics are: - c_has_sclr (integer): Specifies if an SCLR pin is to be included. - c_has_sset(integer): Specifies if an SSET pin is to be included. SSET is not allowed with restricted counters. See below for SCLR/SSET priorities. Valid values are 1 or 0, default is 0. - c_has_sinit(integer): Specifies if an SINIT pin is to be included which, when asserted, will synchronously set the counter value to the value defined by c_sinit_val. Note that if SINIT is present, then neither SSET nor SCLR may be present. Valid values are 1 or 0, default is 0. - c_sinit_val(string): Specifies in binary the value the counter will initialize to when SINIT is asserted. Valid values are 0 up to 2 c_width - 1 for unrestricted counters, and 0 up to c_count_to for restricted counters. Ignored if c_has_sinit = 0. - c_sync_enable(integer): This parameter controls whether or not the SSET, SCLR, and SINIT inputs are qualified by CE. When c_sync_enable = 0, these synchronous controls override the CE signal. When c_sync_enable = 1, they have effect only when CE is high. This parameter is ignored unless c_has_ce = 1. Note that on the primitives, the SCLR and SSET controls override CE, so choosing c_sync_enable =1 will generally result in extra logic. The default is c_sync_enable = 0, - c_sync_priority(integer): Controls the relative priority of SCLR and SSET. When c_sync_priority = 1, SCLR overrides SSET. When c_sync_priority = 0, SSET overrides SCLR. The default is 1, since this is also the way the primitives behave, hence results in no extra logic. Threshold outputs: The behavior of the threshold outputs depends on the state of the c_thresh_early generic. If c_thresh_early = 1, a registered threshold output (Q_THRESH0) will become active on the same clock edge that sets the output of the counter to c_thresh0_value. A nonregistered threshold output (THRESH0) will become active one clock cycle before the threshold value is reached on the counter outputs. This allows more setup time for ripple operations that utilize the nonregistered threshold output prior to the clock edge that sets the counter outputs to the threshold value. If c_thresh_early = 0, a nonregistered output will become active when the threshold value is reached on the counter outputs and a registered output will become active on the next clock edge. This allows implementation of a combinatorial terminal count signal. The timing of threshold outputs is shown in Figure2. Note that any initialization signal (ACLR, ASET, AINIT, SCLR, SSET, SINIT) will cause the registered threshold output to reset to 0. - c_has_thresh0(integer): When this generic equals 1, the THRESH0 combinatorial output will be generated. The default is to not generate a THRESH0 output. - c_has_q_thresh0(integer): When this generic equals 1, the Q_THRESH0 registered output will be generated. The default is to not generate a Q_THRESH0 output. - c_thresh0_value(string): Specifies the value at which the THRESH0 value will be activated as a binary value. The valid range is 0 to c_count_to for restricted counters, and 0 to 2 c_width - 1 for unrestricted counters. Note that when c_restrict_count = 1, c_thresh0_value must be less than or equal to c_count_to. - c_has_thresh1, c_has_q_thresh1(both integer): These generics are remnants from earlier versions of the counter and are no longer supported. They will produce an error if any value other than 0 is supplied. - c_thresh1_value(string): Ignored. c_has_load(integer): Activating the LOAD pin (c_has_load = 1) allows the value on the L[N:0] input port to pass through the logic and be loaded into the output register on the next active clock edge. The default is for no LOAD pin to be generated (c_has_load = 0). If any synchronous options are selected (see c_has_sclr, c_has_sset, and c_has_sinit), they take precedence over LOAD. See later for more complex precedence issues. c_has_l(integer): Specifies whether the L[N:0] bus is present. Technically redundant - c_has_l should equal c_has_load. c_load_enable(integer): This generic controls whether or not the LOAD input is qualified by CE. When c_load_enable = 0, the activation of the LOAD signal will also enable the output register. When c_load_enable = 1, the register needs to have CE active in order to load the L port data. By default this generic equals 0 c_load_low(integer): Earlier versions allowed you to specify an active-low LOAD pin. This functionality has been removed. Any value other than 0 passed to the generic will cause an error. c_has_ce(integer): When this generic equals 1, the module is generated with a clock enable input. The DS215 April 28,

4 default setting is 0. c_pipe_stages(integer): Present for backwards compatibility. Ignored. c_enable_rlocs(integer): Present for backwards compatibility. Ignored. Table 2: XCO and VHDL Generic parameters XCO Parameter XCO Values Generic Parameter Generic Values Description OutputWidth (Integer) 2 to 30 c_width 2 to 30 The output width in bits RestrictCount (Bool) false, true c_restrict_count 0,1 0 (false)= no restriction (will wrap after 2^OutputWidth-1) 1 (true) = Will return to 0 after CountToValue has been reached. Operation UP, DOWN, UP/DOWN c_count_mode 0,1,2 0 (UP) = Up counter 1 (DOWN) = Down counter 2 (UP/DOWN) = Up/Down counter c_has_up 0,1 0 (UP, DOWN)= does not have up port 1 (UP/DOWN) = has up port CountToValue (Hex String) 0 to 2^OutputWidth-1 c_count_to (String) 0 to 2^c_width - 2 Sets the final count value CountStyle Constant, Variable c_has_iv 0 Variable count feature has been deprecated. If you require this feature use an accumulator CountByValue (Hex String)0 to c_count_by (string) 0 to Constant increment/decrement value. AsyncThreshold (Bool) false, true c_has_thresh0 0,1 0 (false) = no thresh0 output 1 (true) = has thresh0 output SyncThreshold0 (Bool) false, true c_has_q_thresh 0 0,1 0 (false) = no q_thresh0 output 1 (true) = has q_thresh0 output Threshold_early (Bool) false, true c_thresh_early 0,1 0 (false) = threshold output appears after the threshold is reached. 1 (true) = threshold output is brought forward one cycle. ThresholdValue0 (Hex String)0 to c_thresh0_value (String)0 to Threshold value. Load (Bool) false, true c_has_load 0,1 0 (false) = no load port 1 (true)= has load port c_has_l 0,1 0 = no l (value to load) port 1 = has l (value to load) port LoadSense "Active High", "Active Low" c_load_low 0,1 0 = Active High load 1 = Active low load 4 DS215 April 28, 2005

5 Table 2: XCO and VHDL Generic parameters XCO Parameter XCO Values Generic Parameter Generic Values Description CE_Override_for _Load (Bool) false, true c_load_enable 0,1 0 (false) = load overrides ce 1 (true) = ce overrides load Clock_Enable (Bool) false, true c_has_ce 0,1 0 (false) = no ce ACLR (Bool) false, true c_has_aclr 0,1 0 (false) = no ce ASET (Bool) false, true c_has_aset 0,1 0 (false) = no ce AINIT (Bool) false, true c_has_ainit 0,1 0 (false) = no ce AINIT_VAL (Hex String) 0 to 2^OutputWidth -1 c_ainit_val (Binary String) 0 to The output value set when ainit = 1 SCLR (Bool) false, true c_has_sclr 0,1 0 (false) = no ce SSET (Bool) false, true c_has_sset 0,1 0 (false) = no ce SINIT (Bool) false, true c_has_sinit 0,1 0 (false) = no ce SINIT_VAL (Hex String) 0 to 2^OutputWidth -1 c_sinit_val (Binary String) 0 to The output value set when sinit = 1 Clock Q Thresh-1 Thresh Thresh+1 Count_to 0 Thresh0 Q_thresh0 Thresh0 (c_thresh_early = 1) Q_thresh0 (c_thresh_early = 1) Figure 2: Threshold Output Timing DS215 April 28,

6 Power-On Conditions See the FD-based Register datasheet for information on the power-up values for the counter. Note that if the user requests Restrict Count functionality, the final register has an internally used synchronous clear, which may affect the power-up value. Priorities of Input Signals ACLR/ASET: ACLR takes priority over ASET. If a different arrangement is required, it will have to be created in external logic. SCLR/SSET: The priority of SCLR versus SSET can be configured using the c_sync_priority generic as described above. LOAD: The synchronous controls (SCLR, SSET, SINIT) take priority over LOAD. Note that if SCLR, SSET, SINIT or LOAD are affected by CE (specified in the c_sync_enable and c_load_enable generics), then a low CE value will cause these signals to be completely ignored. For example, if SCLR is affected by CE but LOAD is not, then with a low CE, LOAD appears to override SCLR, contrary to what was said above. However, this is precisely as it should be, because SCLR has no effect when CE is low. Discussion of Restricted Counters The restricted counter option is implemented using an equality test rather than a greater-than-or-equal-to test. This means that if the counter somehow manages to skip past the c_count_to value it will keep going. As such, there are restrictions on allowable generics for restricted counters: c_has_iv must be 0. Variable increment is not possible with restricted counters. If this functionality is desired, it must be implemented in external logic. c_count_mode cannot be c_updown. c_has_sset and c_has_aset must be 0. Additionally, there are further restrictions which differ for up counters and down counters. Up counters Restricted up counters count up by c_count_by until Q = c_count_to. The clock cycle after Q = c_count_to, the counter resets to 0. There are two basic restrictions: c_count_to must be an integer multiple of c_count_by c_count_by must be less than or equal to c_count_to In addition, the values listed below must satisfy the following formulae: c_ainit_val, if AINIT is used c_sinit_val, if SINIT is used The power-on reset value (see Power-on Conditions) Any value loaded on the L data port. Down Counters Restricted down counters count down by c_count_by until Q = c_count_to. The clock cycle after Q = c_count_to, the counter resets to 0, and the counter continues counting down (wrapping around). There are two basic restrictions: must be an integer multiple of c_count_by c_count_by must be less than or equal to In addition, the values listed below must satisfy the following formulae: either c_ainit_val, if AINIT is used c_sinit_val, if SINIT is used? c_count_to or <value> = 0 The power-on reset value (see Power-on Conditions) Any value loaded on the L data port. Use of LOAD <value>? c_count_by = Integer 2 c_width c_count_to 2 c_width c_count_to <value>? c_count_to? 2 c_width <value>?? c_count_by = Integer <value> The counter BaseBlock can check on instantiation for sensible c_ainit_val, c_sinit_val and power-on reset value, but it cannot check the data loaded on the L data port. Because of this, erroneous values loaded will cause unexpected behavior in the counter. For example, if a counter is given c_count_to = 8 and c_count_by = 2, loading in 3 will cause it to count the odd numbers and completely miss the limit value. It is strongly recommended that LOAD is not used with restricted counters; if such functionality is required, use external logic to create a greater-than-or-equal-to test rather than an equal-to test, or make sure the counter is simple (count by 1) and that a value is never loaded beyond c_count_to. 6 DS215 April 28, 2005

7 Applications There are two methods to include a counter BaseBlock in your design. Method 1: GUI The CORE Generator system will produce several files when a core is generated. Instructions on how to instantiate a core generated by this method are automatically produced in the.vho file. Here is an example of a section of a.vho file -- The following code must appear in the VHDL architecture header: Begin Cut here for COMPONENT Declaration COMP_TAG component counter port ( clk: IN std_logic; q: OUT std_logic_vector(15 downto 0)); end component; -- COMP_TAG_END End COMPONENT Declaration -- The following code must appear in the VHDL architecture -- body. Substitute your own instance name and net names Begin Cut here for INSTANTIATION Template INST_TAG your_instance_name : counter port map ( clk => clk, q => q); -- INST_TAG_END End INSTANTIATION Template Method 2: Direct Instantiation Coregen now allows cores to be directly instantiated into user code. To do this, add the following lines to the head of your VHDL file Library Xilinxcorelib; Use Xilinxcorelib.c_counter_binary_v8_0_comp.all; and instantiate the counter with appropriate values for the generics and your local signals thus: i_my_counter: c_counter_binary_v8_0 generic map( ); c_width => 16, c_has_sclr => 1 port map( ); clk => clk, sclr => sclr, q => counter_output Note that generics do not need to be specified if the default value suits your application. Ordering Information This core may be downloaded from the Xilinx IP Center for use with the Xilinx CORE Generator system v7.1i and later. The CORE Generator system is bundled with the ISE Foundation software at no additional charge. -- You must compile the wrapper file counter.vhd when simulating -- the core, counter. When compiling the wrapper file, be -- sure to reference the XilinxCoreLib VHDL simulation -- library. For detailed -- instructions, please refer to the "CORE Generator Guide". DS215 April 28,