TUTORIAL: USING THE COREGEN APPLICATION TO GENERATIE VHDL CODE

Transcription

1 EECS:6660:0xxField Programmable Gate Arrays tut_coregen - 1 TUTORIAL: USING THE COREGEN APPLICATION TO GENERATIE VHDL CODE 1. INTRODUCTION The Xilinx Integrated Software Environment (ISE) provides an application for facilitating the process of preparing the HDL source codes of commonly used modules. The currently available version of ISE is i. This tutorial briefly shows how to generate a VHDL code for an adder/subtractor module using the CoreGen application. 2. INVOKING THE COREGEN APPLICATION Having been logged on to any station in NE-1026, - source the file which sets various environment variables source /eng/applications/mentor/s1026_06.csh - set the working directory to ~/fpga/hwk mkdir coregen_tut cd coregen_tut Invoke Coregen by executing the command coregen The coregen window opens up as shown in the Figure 1 Figure 1 View of the CORE Generator widow with the Getting Started dialog box superimposed. 3. CREATING A PROJECT ENVIRONMENT From the menu bar select: Project New... Which opens a New Project dialog box shown in Figure 2.

2 EECS:6660:0xxField Programmable Gate Arrays tut_coregen - 2 Figure 2 View of the New Project dialog box. In the New Project window click the browse button and browse to the directory coregen_tut and double click it. This will return control to the New Project dialog box. In the New Project Window select: Target architecture: Virtex2 (by clicking the select button) Output Options: Flow Vendor Design Entry: VHDL, Exemplar OK which opens Xilinx CORE Generator window shown in Figure 3

3 EECS:6660:0xxField Programmable Gate Arrays tut_coregen - 3 Figure 3 View of the Xilinx CORE Generator window. In this window select Basic elements Counters This will bring up in the right hand side pane the line Binary Counter, as shown in Figure 3; double clicking the line to open the Binary Counter dialog box which is shown in Figure 4

4 EECS:6660:0xxField Programmable Gate Arrays tut_coregen - 4 Figure 4 View of the Binary Counter dialog box. In the Binary Count dialog box select: - component Name count_bin - Output Width 8 - Operation up/down - Next> Then, click Register Options... which opens the register options dialog box as shown in the Figure 5 In the register options dialog box select: - Asynchronous Settings Init - OK

5 EECS:6660:0xxField Programmable Gate Arrays tut_coregen - 5 Figure 5: Register Options window. which returns controk to the Binary Counter dialog box shown in the Figure 4. In this dialog box select: Generate After the CoreGenerator indicates that it has completed successfully, exit the Binary Counter by selecting Dismiss This process will create a number of files, including the counter.edn and counter.vhd files. All these files are stored in the coregen_tut directory. The counter.edn file can be used to generate the bit file. To open an AcrobatReader view of the data sheet for the binary counter, select from the Binary Counter dialog box Core Overview Data Sheet and browse the data sheet. To quit the CoreGen application, select File Exit.