Sequential Logic - Module 5

Size: px

Start display at page:

Download "Sequential Logic - Module 5"

Tyrone Stanley
5 years ago
Views:

1 Sequential Logic Module 5 Jim Duckworth, WPI 1

2 Latches and Flip-Flops Implemented by using signals in IF statements that are not completely specified Necessary latches or registers are inferred by the synthesis tool. Transparent Latch Edge-triggered flip-flop Reset Asynchronous Synchronous Counters Shift Registers Finite State Machines Jim Duckworth, WPI 2

3 Combinational Logic - review All input signals specified in sensitivity list All conditions evaluated PROCESS (a, b, sel) IF sel = 1 THEN y <= a ; ELSE y <= b ; END PROCESS; a b sel y Jim Duckworth, WPI 3

4 Transparent (Flow-Through) Latch IF statement not completely specified - missing ELSE part Output follows input when enable high but stores old value when enable goes low PROCESS (enable, d) IF enable = 1 THEN q <= d; END PROCESS; d enable q enable d q Jim Duckworth, WPI 4

5 Edge-Triggered Flip-Flop Positive edge-triggered flip flop PROCESS (clk) IF clk EVENT AND clk = 1 THEN q <= d; END PROCESS; d clk q d clk q Jim Duckworth, WPI 5

6 Flip-flop (cont d) clk EVENT is an example of a function signal attribute returns TRUE if event (change in value) occurred on signal can be used to detect an edge when combined with a further test (AND clk = 1 ) we can determine that it was a rising edge Note: not strictly necessary in this example but good practice makes VHDL description easier to read may be required if additional signals added later Jim Duckworth, WPI 6

7 Clocked Process - general format ARCHITECTURE behav OF flip-flop IS PROCESS (clock signal, [asynchronous signals]) IF asynchronous conditions THEN sequential statements for reset or preset; ELSIF clock_edge THEN sequential statements for clock_edge; END PROCESS; END behav; Sensitivity list includes clk and asynchronous signals All signal assignments in process result in flip-flops Jim Duckworth, WPI 8

8 Adding asynchronous clear and preset signals ENTITY dtype IS PORT(clk, d, clr, pre : IN std_logic; q, n_q : OUT std_logic); END dtype; ARCHITECTURE behav OF dtype IS SIGNAL temp_q : std_logic; -- internal signal PROCESS (clk, clr, pre) IF clr = 1 THEN -- clear operation temp_q <= 0 ; ELSIF pre = 1 THEN -- preset operation temp_q <= 1 ; ELSIF clk EVENT AND clk = 1 THEN -- clock temp_q <= d; END PROCESS; q <= temp_q; n_q <= NOT temp_q; END behav; Jim Duckworth, WPI 9

9 Flip-flop (cont d) Variations can be easily achieved negative-triggered clock synchronous clear ARCHITECTURE behav OF flip-flop IS PROCESS (clk) IF clk EVENT AND clk = 0 THEN IF n_clr = 0 THEN q <= 0 ELSE q <= d; END PROCESS; END behav; Jim Duckworth, WPI 12

10 Counter Five-bit counter with asynchronous reset Using integer type (could also use std_logic_vector with unsigned library) LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY count17 IS PORT(clk, reset : IN std_logic; q : OUT integer RANGE 0 TO 17); END count17; Jim Duckworth, WPI 13

11 Counter (cont d) ARCHITECTURE behav OF count17 is SIGNAL count : integer RANGE 0 TO 17; PROCESS(clk, reset) IF reset = 1 THEN count <= 0; ELSIF clk EVENT AND clk = 1 THEN IF count = 17 THEN count <= 0; ELSE count <= count + 1; END PROCESS; q <= count; -- concurrent statement END behav; -- internal signal -- sensitivity list -- asynch reset -- positive edge -- terminal count Jim Duckworth, WPI 14

12 5-bit Counter Synthesis Jim Duckworth, WPI 15

13 5-Bit Counter Schematic Jim Duckworth, WPI 16

14 Counter with Preset (Synchronous Clear) ENTITY cnt4pre IS PORT(clk, pre, n_clr : IN std_logic; d : IN integer RANGE 0 TO 12; q : OUT integer RANGE 0 TO 12); END cnt4pre; ARCHITECTURE behav OF cnt4pre IS SIGNAL count : integer RANGE 0 TO 12; PROCESS (clk) IF clk EVENT AND clk = 1 THEN IF n_clr = 0 THEN -- synchronous clear count <= 0; ELSIF pre = 1 THEN count <= d; ELSE IF count = 12 THEN count <= 0; ELSE count <= count + 1; END PROCESS; q <= count; END behav; Jim Duckworth, WPI 17

15 Schematic Jim Duckworth, WPI 19

16 Behavioral Simulation Results (ISE) Jim Duckworth, WPI 22

17 Shift Registers Example of 4-bit shift register with parallel load shift left and shift right capability LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY shift IS PORT(load, clk, left_right : IN std_logic; d : IN std_logic_vector(3 DOWNTO 0); q : OUT std_logic_vector(3 DOWNTO 0)); END shift; Jim Duckworth, WPI 25

18 Shift Register (cont d) ARCHITECTURE behav OF shift IS SIGNAL temp : std_logic_vector(3 DOWNTO 0); PROCESS(clk) -- all operations synchronous IF clk'event AND clk = '1' THEN IF load = '1' THEN temp <= d; ELSIF left_right = '0' THEN -- shift left; temp <= temp(2 DOWNTO 0) & '0'; ELSE temp <= '0' & temp(3 DOWNTO 1); -- right END PROCESS; q <= temp; END behav; Jim Duckworth, WPI 26

19 Synthesis Results Jim Duckworth, WPI 27

20 Shift Register - Behavioral Simulation Jim Duckworth, WPI 29

21 State Machines Module 6 Jim Duckworth, WPI 1 State Machines - Module 6

22 State Machines Block Diagram - Moore Machine Outputs determined by current state Inputs Next State Logic State Memory Output Logic Outputs Clock Reset Current State Jim Duckworth, WPI 3 State Machines - Module 6

23 State Machine (cont d) Current state determined by state memory (flip-flops) Outputs are decoded from the value of the current state combinational logic Next state is determined by current state and inputs at time of next triggering clock edge. Jim Duckworth, WPI 4 State Machines - Module 6

24 Simple State Machine Example RESET=1 EN=0 EN=1 S0 C=0 EN=1 S3 C=1 S1 C=0 EN=0 EN=0 EN=1 S2 C=0 EN=1 EN=0 Jim Duckworth, WPI 5 State Machines - Module 6

25 State Machine Coding Style ENTITY sm1 IS PORT(clk, reset, en c END sm1; : IN std_logic; : OUT std_logic); ARCHITECTURE behav OF sm1 IS TYPE state_type IS (s0, s1, s2, s3); -- enumerated type SIGNAL current_state, next_state : state_type; state_memory: PROCESS(clk, reset) -- see next slides for detail END PROCESS state_memory; next_state_logic: PROCESS(en, current_state) END PROCESS next_state_logic; END behav; Jim Duckworth, WPI 7 State Machines - Module 6

26 state_memory Process state_memory: PROCESS(clk, reset) IF reset = '1' THEN current_state <= s0; ELSIF clk'event AND clk = '1' THEN -- triggering edge current_state <= next_state; END PROCESS state_memory; Jim Duckworth, WPI 8 State Machines - Module 6

27 next_state Process next_state_logic: PROCESS(en, current_state) CASE current_state IS WHEN s0 => IF en = '1' THEN next_state <= s1; ELSE next_state <= s0; c <= 0 ; WHEN s1 => IF en = '1' THEN next_state <= s2; ELSE next_state <= s1; c <= 0 ; WHEN s2 => IF en = '1' THEN next_state <= s3; ELSE next_state <= s2; c <= 0 ; WHEN s3 => IF en = '1' THEN next_state <= s0; ELSE next_state <= s3; c <= 1 ; END CASE; END PROCESS next_state_logic; Jim Duckworth, WPI 9 State Machines - Module 6

28 SM1 VHDL Code Jim Duckworth, WPI 10 State Machines - Module 6

29 SM1- Schematic Jim Duckworth, WPI 13 State Machines - Module 6

30 Behavioral Simulation Jim Duckworth, WPI 14 State Machines - Module 6

31 State Machine - alternative coding style -- one process with one state signal ARCHITECTURE behav OF sm2 IS TYPE state_type IS (s0, s1, s2, s3); -- enumerated type SIGNAL state : state_type; PROCESS(clk, reset) IF reset = '1' THEN state <= s0; ELSIF clk'event AND clk = '1' THEN -- triggering edge CASE state IS WHEN s0 => IF en = '1' THEN state <= s1; ELSE state <= s0; c <= '0'; WHEN s1 => IF en = '1' THEN state <= s2; Jim Duckworth, WPI 28 State Machines - Module 6

32 State Machine (cont d) END PROCESS; END behav; END CASE; ELSE state <= s1; c <= '0'; WHEN s2 => IF en = '1' THEN state <= s3; ELSE state <= s2; c <= '0'; WHEN s3 => IF en = '1' THEN state <= s0; ELSE state <= s3; c <= '1'; Jim Duckworth, WPI 29 State Machines - Module 6

33 SM2 - Synthesis Results Jim Duckworth, WPI 30 State Machines - Module 6

34 Registered Outputs Output signal assignments within state machine process No glitches on registered outputs Outputs are registered in parallel with state registers Register introduces a one cycle delay Jim Duckworth, WPI 31 State Machines - Module 6

35 Block Diagram (registered outputs) Inputs Next State Logic State Memory Current State Clock Output Logic Output Register Outputs Jim Duckworth, WPI 32 State Machines - Module 6

36 Functional Simulation Jim Duckworth, WPI 33 State Machines - Module 6

37 Block Diagram (using next state logic) Inputs Next State Logic State Memory Current State Clock Output Logic Output Register Outputs Jim Duckworth, WPI 34 State Machines - Module 6

38 Three processes: Registered Outputs (no delay) state_memory PROCESS (clk, reset) ELSIF clk EVENT AND clk = 1 THEN current_state <= next_state; next_state_logic PROCESS (en, current_state) CASE current_state IS WHEN s0 => next_state <= s1; registered_output_logic (uses next state to determine outputs) PROCESS (clk, reset) ELSIF clk EVENT AND clk = 1 THEN CASE next_state IS WHEN s3 => c <= 1 ; WHEN OTHERS => c <= 0 ; Jim Duckworth, WPI 35 State Machines - Module 6

DESCRIPTION OF DIGITAL CIRCUITS USING VHDL

DESCRIPTION OF DIGITAL CIRCUITS USING VHDL Combinatinal circuits Sequential circuits Design organization. Generic design Iterative operations Authors: Luis Entrena Arrontes, Celia López, Mario García,