Improvement of Compiled Instruction Set Simulator by Increasing Flexibility and Reducing Compile Time

Transcription

1 Improvement of Compiled Instruction Set Simulator by Increasing Flexibility and Reducing Compile Time Moo-Kyoung Chung, Chung-Min Kyung, Department of EECS, KAIST 1 Moo-Kyoung Chung

2 Outline Previous works Introduction to Instruction Set Simulator (ISS) Native code execution Interpretive ISS Compiled ISS Improvement of compiled ISS New approaches Reducing compile time Increasing flexibility Experimental result Conclusion 2 Moo-Kyoung Chung

3 Instruction Set Simulator (ISS) Used for processor design and software design Instruction set simulation/ architecture exploration Early system verification Pre-silicon software development Essential for hardware/software co-simulation For embedded system, SoC design Connected with HDL simulator or emulator ISS S/W H/W HDL simulator or SystemC Host ISS S/W Host H/W Emulator or H/W Prototype 3 Moo-Kyoung Chung

4 Instruction Set Simulator Native code execution Interpretive ISS Compiled ISS Static compiled ISS Dynamic compiled ISS 4 Moo-Kyoung Chung

5 Native Code Execution Target application code is compiled for host machine, executed on the host machine Fastest Inaccurate Only for functionality verification Only support high-level language Cannot support hardware dependent instruction Cannot support assembly language Cannot support library or OS which does not available source code. Difficult to measure performance Target processor instructions may different from the host processor instructions Difficult to handle I/O access Trap-based method 5 Moo-Kyoung Chung

6 Interpretive ISS Simulation loop ( fetch, decode, execute ) for( ; ; ){ inst = fetch( pc ); opcode = decode( inst ); switch( opcode ){ case ADD: break; } } Flexible & Accurate Working in the similar way to the processor behavior Easy to implement, easy to estimate performance Almost commercial available simulators Slow Several millions of simulated instruction per second (MIPS) 6 Moo-Kyoung Chung

7 Static Compiled ISS Target Application Code Target Compiler Binary Translation Host Executable (ISS) No comaptibility for host machine Target Executable Binary (A) Using Binary Translation C Code Generation Simulation C code Host C Compiler Host Executable (ISS) (B) Using C intermediate code 7 Moo-Kyoung Chung

8 Static Compiled ISS Advantage Fast Faster than the corresponding interpretive simulator Move instruction fetch and decode step into compile process Host C compiler optimizes the simulation C code. Powerful optimization effect of host C compiler Unnecessary activities of the processor hardware are not simulated. e.g.) Carry flag does not always need to be updated for all the data processing instructions, if the next instructions do not use and overwrite it. Accurate Easy to estimate performance 8 Moo-Kyoung Chung

9 Static Compiled ISS Disadvantage Cannot support dynamic program code All the target instructions should be compiled in the static time. Self-modifying code External code (loading) Dynamic linking library Multiple instruction set (ARM:Thumb) Enormous compile time overhead for the software designer Indirect branch instruction C compiler is hard to optimize the code Performance (simulation speed) drop Large application Enormous memory usage Generated binary is much larger then original binary. Low locality of binary Basic block is larger in that scale 9 Moo-Kyoung Chung

10 Dynamic Compiled ISS Dynamic compilation Moving compilation step into simulation run-time. Using binary translation Cannot use intermediate C code Problems on the run-time C chuck code compilation Using translation cache No Cache hit? Yes Target Executable Instruction Fetch Relatively slow Binary Translation Run-time compilation (binary translation) overhead Flexible and Relatively accurate Translation Cache Execution 10 Moo-Kyoung Chung

11 ISS Accuracy Static compile ISS = Interpretive ISS > Dynamic Compiled ISS > Native code execution Simulation Speed Native code execution > Static compiled ISS > Dynamic compiled ISS > Interpreted ISS Simplicity Native code execution > Interpretive ISS > Static compiled ISS > Dynamic Compiled ISS Compilation Speed Native code execution = Interpreted ISS = Dynamic compiled ISS > Static compiled ISS Flexibility Interpretive ISS = Dynamic Compiled ISS > Native code execution > Static compile ISS 11 Moo-Kyoung Chung

12 Objective How to reduce compile time (startup cost) of the static compiled ISS? How to increase flexibility of the static compiled ISS? 12 Moo-Kyoung Chung

13 Improvement of Compiled-ISS New approach Using the object files (relocatable format, ELF) as input files instead of binary executable file Making the generated simulation program have the same data and control flow as the target program has. Making the static compiled ISS have built-in interpreter. Advantages Reducing the compile time recompiled time Increasing flexibility Supporting indirect branch efficiently Supporting dynamic code Fast speed Taking all the advantages of the static compiled-iss 13 Moo-Kyoung Chung

14 ISS Generation Flow Source 1 Source 2 Source 3 Target Source Files Having same structure Cross Compile Object 1 Object 2 Object 3 Compile, Excluding Link C Code Generation Simulation Code Generation C 1 C 2 C 3 Target Simulation C Code Host Compile Simulator Host Executable ISS Relocatable files Library files Relocatable file. After COMPILE, before LINK of C compilation 14 Moo-Kyoung Chung

15 C Code Generation ELF (Executable and Linkable Format) is the most widely used file format for object, executable and library file. Object 1 Extracting the CFG, DFG using Symbol table and decoded information Symbol Code Analyzer CFG, DFG ELF Loader Text Decoded Info. Decoder Decoded Data Code Analysis C Code Generation Simulation C Code 1 Identical structure to the target source file Simulation Code Generation 15 Moo-Kyoung Chung

16 Generating Constructed C Code int result; void cfunction( int number ) { if( number >= 5 ) result = number - 5; } (A) Target C Source... 14:[e51b3010] ldr r3,[r11,#0x10] 18:[e ] cmps r3,#0x4 1c:[da000003] ble #0xc 20:[e59f300c] ldr r3,#0xc 24:[e51b2010] ldr r2,[r11,#0x10] 28:[e ] sub r2,r2,#0x5 2c:[e ] str r2,[r3,#0x0]... (B) Object File (Disassemble) 1 int T_result; 2 void T_cfunction() 3 { LDType=W;Rd=3;Rn=11;LDDir=PRE_DOWN;Imm=0x10;LDWBack=0; LDR_L_I(); 6 Rn=3;Imm=0x4;SType=SHT_LSL;SAmt=0x0; CMP_I(); 7 WR_COND(); 8 Imm=0xc;Cond=0x000d; B(); 9 if( conpass ) goto T newsym_30; 10 LDType=W;Rd=3;Rn=15;LDDir=PRE_UP;Imm=0xc;LDWBack=0; LDR_L_I(); 11 R[3] = &T_result; 12 LDType=W;Rd=2;Rn=11;LDDir=PRE_DOWN;Imm=0x10;LDWBack=0; LDR_L_I(); 13 Rd=2;Rn=2;Imm=0x5;SType=SHT_LSL;SAmt=0x0; SUB_I(); 14 LDType=W;Rd=2;Rn=3;LDDir=PRE_UP;Imm=0x0;LDWBack=0; STR_L_I(); 15 *(R[3]+0) = R[2]; 16 T_newsym_30: } (C) Simulation C Code 16 Moo-Kyoung Chung

17 Reducing Compile Time Previous static compiled ISS The simulation C code has a large function that contains all of the generated simulation code from the target binary. Increasing the function size, the C code compilation time is more increased because of the host compiler optimization. Even a slight change of the source code causes the timeconsuming compilation process. How to reduce compile time The simulation C code is composed of many of small functions. Generated C file has the same structure with target C code The same CFG/DFG It speeds up compiler optimization and reduce compile time Selective Compilation Compiling only the files that are changed Using make utility It speeds up regeneration of ISS 17 Moo-Kyoung Chung

18 Reducing Compile Time Target Program A.c B.c C.c D.c A.c B.c C.c D.c Compile Compile a.o B.o C.o D.o A.o B.o C.o D.o Link Code Gen Generated C code Appl.exe Code Gen A_G.c B_G.c C_G.c D_G.c Compile Gen.c A_G.o B_G.o C_G.o D_G.o Timeconsuming because it handles the large single function. Gen.o Simulator Previous Simulator Generation Process Compile link Re-compilation should have all the time-consuming compilation steps Simulator Only the modified files goes through these steps New Simulator Generation Process Link It is fast because it handles many of small C files 18 Moo-Kyoung Chung

19 Supporting Indirect Branch Supporting Indirect Branch Could not determine the branch target address at compile time Previous Static Compiled-ISS To support the indirect branch, it is necessary to insert labels into every start line of the instruction simulation code in the simulation C file. Those labels take basic block apart. It makes interference with the compiler optimization. Runtime Branch Target Search There should be a symbol (label) at a possible branch target address in target C code according to the normal usage of C language Since the simulation C code has the same CFG with the target code, It also has the corresponding symbols. I made so-called Dynamic Branch Handler which finds the destination symbol (label) and jumps to the address We can handle the indirect branch without adding labels. 19 Moo-Kyoung Chung

20 Supporting Indirect Branch Target_code(){ Label_250:... Label_700:... Label_1000: Inst.1 simulation code label_1001: Inst.2 simulation code label_1002: Inst.3 simulation code label_1003: Inst.4 simulation code label_1004: // Bx R1 goto addr2(r1)... } ISS does not know which address will be the destination at compile time. Unnecessary labels make interference with the optimization and make simulation slow. Generated C Code of Previous Compiled-ISS Function_A(){...} Function_B(){...} Function_C(){ Inst.1 simulation code } Inst.2 simulation code Inst.3 simulation code Inst.4 simulation code //Bx R1 target = DynamicBH( R1 ) *(target)()... ISS knows the possible branch destination address where should be a lable No redundant labels. Taking better optimization effect of host C compiler Generated C Code of New Approach 20 Moo-Kyoung Chung

21 Supporting Dynamic Code Static Compiled ISS Cannot support run-time change of the execution code. Self-modifying code External memory code Downloaded code Dynamic Code Handler Built-in Interpreter Handles the dynamic code. Fetch, Decode, Dispatch Cache Target processor resources are shared between the two ISS s It is necessary to check the modification of binary to be executed. The code executed by the interpretive block runs without speed improvement of the compiled ISS. 21 Moo-Kyoung Chung

22 Supporting Dynamic Code Compiled ISS shares the target processor resource data The next instruction was not compiled at static time Next PC Compiled ISS Execute Instruction Simulation Code Target Processor Resource No Self-modifying Code TEXT Range? External Code Could not get speedup of compiled ISS Only for the dynamic code. Dynamic Code Handler Yes Modified Code? Yes No Modified? Yes Decode No Store to TEXT Addr/Data Self-Modifying Code Table Dispatch Cache Manager Dispatch Cache Built-in in Interpreter Execute Simulation Flow Data Access 22 Moo-Kyoung Chung

23 Experimental Result Performance of Compiled ISS Platform CPU : Intel Xeon CPU 2GHz, 512K Cache OS : Linux Redhat 7.2 Target Processor ARM 7 Target Application IDCT Matrix multiply FIR JPEG Decoder MP3 Decoder 23 Moo-Kyoung Chung

24 Simulation Speed Benchmarks (Target Program) Executed Instruction Count Native Execution (sec.) GNU(GDB) ISS (sec.) Interpretive ISS Commercial ISS (sec.) OBSIM (sec.) Matrix Multiply 1,601 M 0.97 x x x X35 IDCT 1,812 M 1.51 x x x x44 FIR 1,140 M 0.81 x1 137 x x X38 24 Moo-Kyoung Chung

25 Compile Time Benchmarks (Target Program) Source Existing Method Total Compile Time (sec.) Recompile Time (sec.) Total Compile Time (sec.) OBSIM Recompile Time (sec.) JPEG Decoder 12 C Files 137,875 Lines MP3 Decoder 18 C Files 199,220 Lines Moo-Kyoung Chung

26 Summary New approach Keeping speed of static compiled ISS Reducing the compile time Increasing the flexibility Supporting indirect branch without speed losses Supporting dynamic code Practical use Co-simulation for embedded system exploration Fast simulation speed Fast compilation/recompilation speed Easy to estimate performance Powerful semi-hosting features 26 Moo-Kyoung Chung

27 Reference [1] Reshadi M., Mishra P., Dutt N., Instruction set compiled simulation: a technique for fast and flexible instruction set simulation, 38th DAC, Proceedings of, 2003 [2] Jianwen Zhu, Gajski D.D., An ultra-fast instruction set simulator, VLSI Systems, IEEE Transactions on, June 2002, Volume: 10, Issue: 3 [3] Reshadi M., Dutt N., Reducing compilation time overhead in compiled simulators, 21st ICCD, Proceedings of, 2003 [4] Amicel R., Bodin F., Mastering startup costs in assembler-based compiled instruction-set simulation, sixth Annual Workshop on Interaction between Compilers and Computer Architectures, Proceedings of, 2002 [5] Nohl A., Braun G., Schliebusch O., Leupers R., Meyr H., Hoffmann A., A universal technique for fast and flexible instruction-set architecture simulation, 39th DAC, Proceedings of, 2002 [6] Zivojnvic V., Tjiang S., Meyr H., Compiled simulation of programmable DSP architectures, IEEE Workshop VLSI Signal Processing, Proceedings of, [7] Emmett Witchel, Mendel Rosenblum, Embra: fast and flexible machine simulation, ACM SIGMETRICS, Proceedings of, May 1996, Volume 24 Issue 1 27 Moo-Kyoung Chung

28 Reference [8] R. F. Cmelik, D. Keppel Shade, A fast instruction-set simulator for execution profiling, ACM SIGMETRICS, Proceedings of, 1994 [9] ARM9 User Manual manual. Available at [10] Zivojnovic V., Meyr H., Compiled HW/SW co-simulation, 33rd DAC, Proceedings of, 1996 [11] Hoffmann A., Kogel T., Nohl A., Braun G., Schliebusch O., Wahlen O., Wieferink A., Meyr H., A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Nov. 2001, Volume: 20, Issue: 11 [12] Eric C. Schnarr, Mark D. Hill, James R. Larus, Facile: a language and compiler for high-performance processor simulators, Programming language design and implementation, Proceedings of, 2001 [13] Jong-Yeol Lee, In-Cheol Park, Timed compiled-code simulation of embedded software for performance analysis of SOC design, 39th DAC, Proceedings of, 2002 [14] Bammi J.R., Harcourt E., Kruitzer W., Lavagno L., Lazarescu M.T., Software performance estimation strategies in a system-level design tool, Eighth CODES, Proceedings of, 2000 [15] Nagendra G.D., Kumar V.G.P., Sheshadri B.S., Simulation Bridge: a framework for multi-processor simulation, Tenth CODES, Proceedings of, Moo-Kyoung Chung