ECE 111 ECE 111. Advanced Digital Design. Advanced Digital Design Winter, Sujit Dey. Sujit Dey. ECE Department UC San Diego
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1 Advanced Digital Winter, 2009 ECE Department UC San Diego Winter 2009 Advanced Digital Objective: of a hardware-software embedded system using advanced design methodologies and tools URL: Lectures: TuTh 9:30-10:50am, WLH 2115 Instructor: Professor Office Hours: TuTh: 11am-noon Lab Hours (TA): MWF: 6-6:50pm Office: EBU dey@ece.ucsd.edu `
2 Assistants Teaching Assistant: Shaoxuan Wang TA Lab hrs: MWF: 6-6:50pm Lab: EBU1-3327,3329; Lab Assigned ACS labs EBU1-3327,3329; EBU hour/day access with combination TA Lab hrs: MWF: 6-6:50pm Forms, Accounts Toolset: Mentor Graphics, Synopsys, Altera Hardware Simulators and Synthesis Tools Embedded Software Tools Hardware-Software Co- Tools
3 Course Outline: Topics Covered Introduction to Embedded System : alternatives HW design: Introduction to HDL (Verilog) HW design alternatives (Custom, ASIC, FPGA) HW design flow, Behavioral design, RTL design, Synthesis HW/SW Co- HW/SW Co-Verification, Seamless CVE HW/SW Communication, Bus, Interface protocols Platform based Low Power Embedded System Project presentations Course Outline: Projects Project 1: HW design project (using Verilog) Subsequent projects: of MAC tasks Project 2: HW design of encryption tasks Area and Performance constraints Project 3: SW design of MAC Project 4: HW/SW design of MAC; Comparison with SW only implementation
4 Projects and Grading Project 1 10% Project 2 30% Project 3 15% Project 4 25% Presentation/Exam 20% Project group size: 2 students ing an Embedded System: How and Why? Metrics Performance Cost (Engg, BOM) Power Reliability Portability Serviceability Debug-ability Time to Market Time in Market (programmable, configurable, adaptive) Software Hardware HW/SW Desktop (e.g., Pentium) Embedded (e.g.arm) Application Specific (e.g., DSP) Custom Circuits Reconfigurable (e.g., Tensilica: cache config., instructions) ASIC Programmable Logic Application Specific SOC MPEG DSP ADC DES RAM1 Platform cpu mpg ram Domain Sp. Platform dsp cpu asic ram asic
5 Levels of Abstraction in System Customization Granularity Silicon Area Effort Performance Transistor Level Gate Level Register Transfer (RT) Level IP Core Based System-on-Chip Platform Based System System Implementation Tradeoffs ASIC SoC Time in Market Time to Market FPGA based HW/SW Platform Platform Based Embedded Software Configurability (Flexibility, Cost) Performance (Speed,Power)
6 Core-based System-on on-chip DSP UDL D/A Communication Architectures RAM MPEG Encoder Telecom RF Interface Bridging Productivity Gap By Reusing IP Cores What are IP cores? pre-designed, pre-verified complex functional block also termed Intellectual Property, mega-cells, macro-blocks Examples: processor cores: LSI Logic CW4001/10/100, ARM 7TDMI, ARM810, Strong ARM, NEC V85x, Motorola 680x0, IBM PowerPC DSP Cores: TI TMS320C54X, Pine, Oak Peripherals: Cache Controller, DMA Controller, MMU, BIU Interface: PCI, USB, UART Multimedia: JPEG compression, MPEG decoder, Video DAC Networking/Telecommunications - Ethernet controller, ATM SAR, MAC
7 Application-Specific System-on on-chip IP Cores, DSP Peripherals Interface Multimedia Telecom/ Networking S/W Tasks System Spec (Communicating Tasks) IP SELECTION/PARTITIONING/MAPPING Hard Cores Soft Cores Custom Hardware Validation ALGORITHMIC CO-VALIDATION Interfaces Communication Protocols & Architectures Memory Organizations Ultra-DSM Technology S/W SYNTHESIS H/W SYNTHESIS INTEGRATION COMMUNICATION CORE ROM/ RAM Coproc. Periph. UDL PCI/ MPEG Analysis -Power - Performance DSM noise DFT AND TEST ARCHITECTURAL CO-VALIDATION FULL TIMING VERIFICATION PROTOTYPE VERIFICATION
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