^1 USER MANUAL. ^2 Accessory 65E. ^3Digital I/O Sinking Inputs, Sourcing Outputs. ^5 February 14, 2015

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1 ^ USER MANUAL ^ Accessory 65E ^Digital I/O Sinking Inputs, Sourcing Outputs ^ Ax xUxx ^5 February, 05 DELTA TAU Data Systems, Inc. NEW IDEAS IN MOTION Single Source Machine Control Power // Flexibility // Ease of Use Lassen St. Chatsworth, CA 9 // Tel. (88) Fax. (88) //

2 Copyright Information 05 Delta Tau Data Systems, Inc. All rights reserved. This document is furnished for the customers of Delta Tau Data Systems, Inc. Other uses are unauthorized without written permission of Delta Tau Data Systems, Inc. Information contained in this manual may be updated from time-to-time due to product improvements, etc., and may not conform in every respect to former issues. To report errors or inconsistencies, call or Delta Tau Data Systems, Inc. Technical Support Phone: (88) Fax: (88) Website: Operating Conditions All Delta Tau Data Systems, Inc. motion controller products, accessories, and amplifiers contain static sensitive components that can be damaged by incorrect handling. When installing or handling Delta Tau Data Systems, Inc. products, avoid contact with highly insulated materials. Only qualified personnel should be allowed to handle this equipment. In the case of industrial applications, we expect our products to be protected from hazardous or conductive materials and/or environments that could cause harm to the controller by damaging components or causing electrical shorts. When our products are used in an industrial environment, install them into an industrial electrical cabinet or industrial PC to protect them from excessive or corrosive moisture, abnormal ambient temperatures, and conductive materials. If Delta Tau Data Systems, Inc. products are directly exposed to hazardous or conductive materials and/or environments, we cannot guarantee their operation. WARNING A Warning identifies hazards that could result in personal injury or death. It precedes the discussion of interest. Caution A Caution identifies hazards that could result in equipment damage. It precedes the discussion of interest. A identifies information critical to the understanding or use of the equipment. It follows the discussion of interest.

3 REVISION HISTORY REV. DESCRIPTION DATE CHG APPVD Added CE Declaration 06/07/06 CP SF Revs. To J, J, Pins 8, 5 05//07 CP AO Reformatted Schematics 0/8/08 CP SF Updated Max Current Output 0/9/08 CP SM 5 Added UL seal, updated agency approval 0/0/09 CP SF 6 Added Power PMAC/MACRO Reformatted manual 0// RN RN 7 Corrected DIP switch settings 0/0/5 RN RN

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5 Table of Contents INTRODUCTION... 7 SPECIFICATIONS... 8 Environmental Specifications... 8 Electrical Specifications... 8 Power Requirements... 8 Fuse... 8 Input Drivers... 8 Output Drivers... 8 Physical Specifications... 9 Terminal Block Layout... 9 D-Sub Layout... 9 Agency Approval and Safety... 0 ADDRESSING THE ACC-65E... Address Select DIP Switch SW... Legacy MACRO Dip Switch Settings... Hardware Address Limitations... USING THE ACC-65E WITH POWER UMAC... 5 Declaring Pointers to I/O Structure Elements... 5 USING THE ACC-65E WITH TURBO UMAC... 6 Assigning M-Variables to I/O Memory Locations... 6 Configuring the Control Word... 6 USING THE ACC-65E WITH MACRO... 7 MACRO6 I/O Node Addressing... 8 Ring Controller I/O Node Addressing... 0 Turbo PMAC I/O Node Addressing... 0 Power PMAC I/O Node Addressing... Power PMAC I/O Node Addressing... Configuring MACRO I/O Transfers... 5 MS{anynode},MI MS{anynode},MI MS{anynode},MI69/MI70... Accessing the Transferred Data... 7 Outputs Mirror Image Concept... 7 Turbo PMAC MI60 Mapping Example... 8 Turbo PMAC MI7 Mapping Example... 0 Turbo PMAC MI69/70 Mapping Example... Power PMAC MI60 Mapping Example... Power PMAC MI7 Mapping Example... 6 Power PMAC MI69/70 Mapping Example... 8 Power PMAC MI60 Mapping Example Table of Contents v

6 Power PMAC MI7 Mapping Example... 5 Power PMAC MI69/70 Mapping Example... 5 Configuring the Control Word for MACRO... 5 CONNECTOR PINOUTS AND WIRING... 5 Terminal Block Connectors... 5 Top: Inputs... 5 Bottom: Outputs TB Wiring Diagram D-Sub Connectors Top: Inputs Bottom: Outputs D-Sub Wiring diagram P: UMAC Bus (UBUS) Connector APPENDIX A: E-POINT JUMPERS APPENDIX B: SCHEMATICS... 6 APPENDIX C: USING THE ACC-65E IN C... 6 ACC-65E C Library... 6 Locations for the C Files... 6 Function Descriptions Example Table of Contents vi

7 INTRODUCTION The accessory 65E (ACC-65E) is a general purpose digital input and output card. It provides inputs and outputs of self-protected, optically isolated sinking inputs and sourcing outputs. The ACC-65E is a U Euro style card intended to plug into the UMAC BUS backplane. It can be used with the: Turbo UMAC CPU Power UMAC CPU MACRO UMAC Station (MACRO6 CPU, PMAC or PMAC Style) Introduction 7

8 SPECIFICATIONS Environmental Specifications Description Specification s Operating Temperature 0 C to 5 C Storage Temperature -5 C to 70 C Humidity 0% to 95 % Non-Condensing Electrical Specifications Power Requirements Whether providing the ACC-65E with power from the U backplane bus or externally (standalone mode) through TB, the power requirements (± 0%) are: A (Board Logic Input) A (Per Output Pin) A (Maximum current when using all outputs simultaneously) TB is a -pin 5V connector on the base board (used for standalone operation), not to be confused with the -pin TB connector on either of the I/O mezzanine boards. Fuse Manufacturer Specification Delta Tau Part Number Bussmann 5 0 A MDA 0A Input Drivers The inputs to the ACC-65E have an activation range from V to V. Due to the self-protecting circuitry, the inputs can only be configured as sinking. Although self-protecting, no more than VDC should be applied to any I/O pin. This is a limitation of the protective circuitry which includes MMBZVALT Zener diodes. Output Drivers The output drivers use the Diodes Inc. Zetex ZXMS6006DG chip. The current drawn from each output line should be limited to 600 ma at voltage levels between VDC and VDC and no more than 8 Amps total for all outputs simultaneously. Specifications 8

9 Physical Specifications Terminal Block Layout 0.9 Pin # 6.0 TB TB TB TB Pin # D-Sub Layout J J J J Specifications 9

10 Description Specification s Dimensions Length: 6.56 cm (6. in.) Height: 0 cm (.9 in.) Width:.0 cm (0.8 in.) Weight w/o Option A 80 g Front Plate included Terminal Block Connectors FRONT-MC,5/-ST,8 FRONT-MC,5/5-ST,8 FRONT-MC,5/-ST,8 Terminal Blocks from Phoenix Contact. UL 9V-0 DB Option Connectors DB5 Female UL 9V-0 The width is the width of the front plate. The length and height are the dimensions of the PCB. See Layout section for physical dimensions. Agency Approval and Safety Item Description CE Mark Full Compliance EN550 Class A Group EN Class A EN EN EMC EN EN EN EN EN Safety EN 600- UL cul UL 600- File E57 CAN/CSA C. No File E57 Specifications 0

11 Application of Council Directive: 89/6/EEC, 7//EEC Manufacturers Name: Manufacturers Address: Delta Tau Data Systems, Inc. Lassen Street Chatsworth, CA 9 USA We, Delta Tau Data Systems, Inc. hereby declare that the product Product Name: Accessory 65E Model Number: And all of its options conforms to the following standards: EN66: 997 EN550: 998 EN600- EN :995 A:998 EN6000--: 995 EN6000--:995 A: 998 EN6000--: 995 A: 998 EN6000--: 995 EN : 995 EN : 996 EN6000--: 99 Electrical equipment for measurement, control, and laboratory use- EMC requirements Limits and methods of measurements of radio disturbance characteristics of information technology equipment Electrical equipment for measurement, control, and laboratory use- Safety requirements Limits for harmonic current emissions. Criteria A Limitation of voltage fluctuations and flicker in low-voltage supply systems for equipment with rated current 6A. Criteria B. Electro Static Discharge immunity test. Criteria B Radiated, radio-frequency, electromagnetic field immunity test. Criteria A Electrical fast transients/burst immunity test. Criteria B Surge Test. Criteria B Conducted immunity test. Criteria A Voltage dips test. Criteria B and C Date Issued: May 006 Place Issued: Chatsworth, California USA Mark of Compliance Specifications

12 ADDRESSING THE ACC-65E Address Select DIP Switch SW The switch SW selects the starting address location for the first I/O gate on the ACC-65E. The following table shows the dip switch settings for the Turbo, Power, and MACRO Station settings: Base Address SW Positions Chip Select TURBO MACRO POWER I/O Base Offset Index ACC-65E[n] 6 5 CS0 CS CS Y:$78C00 Y:$8800 $A ON ON ON ON ON ON Y:$79C00 Y:$9800 $A08000 ON ON ON OFF ON ON Y:$7AC00 Y:$A800 $A ON ON OFF ON ON ON Y:$7BC00 Y:$B800 $A8000 ON ON OFF OFF ON ON Y:$78D00 Y:$880 $B00000 ON ON ON ON ON OFF Y:$79D00 Y:$980 $B ON ON ON OFF ON OFF Y:$7AD00 Y:$A80 $B ON ON OFF ON ON OFF Y:$7BD00 Y:$B80 $B8000 ON ON OFF OFF ON OFF Y:$78E00 Y:$8880 $C00000 ON ON ON ON OFF ON Y:$79E00 Y:$9880 $C ON ON ON OFF OFF ON Y:$7AE00 Y:$A880 $C ON ON OFF ON OFF ON Y:$7BE00 Y:$B880 $C8000 ON ON OFF OFF OFF ON Y:$78F00 Y:$88C0 $D00000 ON ON ON ON OFF OFF CS6 Y:$79F00 Y:$98C0 $D ON ON ON OFF OFF OFF Y:$7AF00 Y:$A8C0 $D0000 ON ON OFF ON OFF OFF Y:$7BF00 Y:$B8C0 $D ON ON OFF OFF OFF OFF ON designates Closed. OFF designates Open. Factory default is all ON. Addressing The ACC-65E

13 Legacy MACRO Dip Switch Settings Chip Select Base Address (Alternate) SW Positions Y:$B800 (Y:$FFE0) ON (OFF) ON (OFF) OFF OFF ON ON Y:$B80 (Y:$FFE8) ON (OFF) ON (OFF) OFF OFF ON OFF Y:$B880 (Y:$FFF0) ON (OFF) ON (OFF) OFF OFF OFF ON 6 Y:$B8C0 (Y:$FFF8) ON (OFF) ON (OFF) ON ON OFF OFF The Legacy Macro base addresses are double mapped. Set SW positions 5 & 6 to OFF if the alternate addressing is desired. Hardware Address Limitations Historically, two types of accessory cards have been designed for the UMAC U bus type rack: type A and type B cards. They can be sorted out as follows: Name Type Category Possible Number of Base Addresses ACC-9E A General I/O ACC-0E A General I/O ACC-E A General I/O ACC-E A General I/O Maximum Number of cards in rack 0 ACC-5E B Feedback ACC-57E B Feedback ACC-58E B Feedback ACC-59E B Analog I/O ACC-E B General I/O 6 ACC-8E B Analog I/O 6 ACC-6E B Analog I/O 6 ACC-65E B General I/O 6 ACC-66E B General I/O 6 ACC-67E B General I/O 6 ACC-68E B General I/O 6 6 ACC-8E B Feedback Addressing The ACC-65E

14 Addressing Type A and Type B accessory cards in a UMAC or MACRO station rack requires attention to the following set of rules: Populating Rack with Type A Cards Only (no conflicts) In this case, the card(s) can potentially use any available Address/Chip Select. The type A cards have only one base address per chip select (CS0, CS, and CS). Each card can be set up (jumper settings) to use the low, middle, or high byte of a specific base address. This makes it possible to populate a single rack with 9 ( bases x byte locations) Type A accessory cards. A fourth address is available at CS6 in which only the high byte can be used, thus making the maximum 0 Type A accessory cards. Populating Rack with Type B Cards Only (no conflicts) In this case, the card(s) can potentially use any available Address/Chip Select. Populating Rack with Type A & Type B Cards (possible conflicts) Typically, Type A and Type B cards should not share the same Chip Select. If this configuration is possible, then the following rules apply: Type A and Type B Feedback Cards Type A cards cannot share the same base address as Type B Feedback cards. Type A and Type B General I/O Cards Type A cards can share base addresses with Type B general I/O cards; however, in this case, Type B cards naturally use the lower byte (default), and Type A cards must be set to the middle/high byte of the selected base address. Type A Cards and Type B Analog Cards Type A cards can share base addresses with Type B analog I/O cards; however, in this case, Type B cards naturally use the middle/high bytes (default), so Type A cards should be set to the low byte of the selected base address. The above conflicts only occur with the first base address in each Chip Select of the Type B cards (i.e. $78C00, $78D00, $78E00, and $78F00). Conflicts can more simply be avoided by using only the second to fourth addresses of each Chip Select. Addressing The ACC-65E

15 USING THE ACC-65E WITH POWER UMAC Using the ACC-65E with Power UMAC requires: Knowing and configuring the index (address offset) of the card Declaring pointers, with user given names, to the appropriate I/O structure elements Declaring Pointers to I/O Structure Elements Mapping an ACC-65E at index 0, for example, with user configurable pointer names: Inputs Outputs PTR Input->ACC65E[0].DataReg[0].0.; PTR Input->ACC65E[0].DataReg[0]..; PTR Input->ACC65E[0].DataReg[0]..; PTR Input->ACC65E[0].DataReg[0]..; PTR Input5->ACC65E[0].DataReg[0]..; PTR Input6->ACC65E[0].DataReg[0].5.; PTR Input7->ACC65E[0].DataReg[0].6.; PTR Input8->ACC65E[0].DataReg[0].7.; PTR Input9->ACC65E[0].DataReg[].0.; PTR Input0->ACC65E[0].DataReg[]..; PTR Input->ACC65E[0].DataReg[]..; PTR Input->ACC65E[0].DataReg[]..; PTR Input->ACC65E[0].DataReg[]..; PTR Input->ACC65E[0].DataReg[].5.; PTR Input5->ACC65E[0].DataReg[].6.; PTR Input6->ACC65E[0].DataReg[].7.; PTR Input7->ACC65E[0].DataReg[].0.; PTR Input8->ACC65E[0].DataReg[]..; PTR Input9->ACC65E[0].DataReg[]..; PTR Input0->ACC65E[0].DataReg[]..; PTR Input->ACC65E[0].DataReg[]..; PTR Input->ACC65E[0].DataReg[].5.; PTR Input->ACC65E[0].DataReg[].6.; PTR Input->ACC65E[0].DataReg[].7.; PTR Output->ACC65E[0].DataReg[].0.; PTR Output->ACC65E[0].DataReg[]..; PTR Output->ACC65E[0].DataReg[]..; PTR Output->ACC65E[0].DataReg[]..; PTR Output5->ACC65E[0].DataReg[]..; PTR Output6->ACC65E[0].DataReg[].5.; PTR Output7->ACC65E[0].DataReg[].6.; PTR Output8->ACC65E[0].DataReg[].7.; PTR Output9->ACC65E[0].DataReg[].0.; PTR Output0->ACC65E[0].DataReg[]..; PTR Output->ACC65E[0].DataReg[]..; PTR Output->ACC65E[0].DataReg[]..; PTR Output->ACC65E[0].DataReg[]..; PTR Output->ACC65E[0].DataReg[].5.; PTR Output5->ACC65E[0].DataReg[].6.; PTR Output6->ACC65E[0].DataReg[].7.; PTR Output7->ACC65E[0].DataReg[5].0.; PTR Output8->ACC65E[0].DataReg[5]..; PTR Output9->ACC65E[0].DataReg[5]..; PTR Output0->ACC65E[0].DataReg[5]..; PTR Output->ACC65E[0].DataReg[5]..; PTR Output->ACC65E[0].DataReg[5].5.; PTR Output->ACC65E[0].DataReg[5].6.; PTR Output->ACC65E[0].DataReg[5].7.; Typically, these pointers would be put in a Global Includes file. To switch/add definitions to a different card, change the ACC65E[0] to ACC65E[n], where n is the card index set by the dip switch settings. With Power PMAC, the control word is set up automatically by the firmware with ACC65E[n].CtrlReg = 7. Using the ACC-65E with Power UMAC 5

16 USING THE ACC-65E WITH TURBO UMAC Using the ACC-65E with Turbo UMAC requires: Knowing (configuring) the base address of the card Pointing M-Variables to the appropriate I/O memory locations Configuring the control word Assigning M-Variables to I/O Memory Locations Mapping an ACC-65E at $78C00, for example, with user configurable M-Variable numbers and name substitutions: Inputs Outputs #define Input M700 #define Input M700 #define Input M700 #define Input M700 #define Input5 M7005 #define Input6 M7006 #define Input7 M7007 #define Input8 M7008 Input->Y:$078C00,0, Input->Y:$078C00,, Input->Y:$078C00,, Input->Y:$078C00,, Input5->Y:$078C00,, Input6->Y:$078C00,5, Input7->Y:$078C00,6, Input8->Y:$078C00,7, #define Output M705 #define Output M706 #define Output M707 #define Output M708 #define Output5 M709 #define Output6 M700 #define Output7 M70 #define Output8 M70 Output->Y:$078C0,0, Output->Y:$078C0,, Output->Y:$078C0,, Output->Y:$078C0,, Output5->Y:$078C0,, Output6->Y:$078C0,5, Output7->Y:$078C0,6, Output8->Y:$078C0,7, #define Input9 M7009 #define Input0 M700 #define Input M70 #define Input M70 #define Input M70 #define Input M70 #define Input5 M705 #define Input6 M706 Input9->Y:$078C0,0, Input0->Y:$078C0,, Input->Y:$078C0,, Input->Y:$078C0,, Input->Y:$078C0,, Input->Y:$078C0,5, Input5->Y:$078C0,6, Input6->Y:$078C0,7, #define Output9 M70 #define Output0 M70 #define Output M705 #define Output M706 #define Output M707 #define Output M708 #define Output5 M709 #define Output6 M700 Output9->Y:$078C0,0, Output0->Y:$078C0,, Output->Y:$078C0,, Output->Y:$078C0,, Output->Y:$078C0,, Output->Y:$078C0,5, Output5->Y:$078C0,6, Output6->Y:$078C0,7, #define Input7 M707 #define Input8 M708 #define Input9 M709 #define Input0 M700 #define Input M70 #define Input M70 #define Input M70 #define Input M70 Input7->Y:$078C0,0, Input8->Y:$078C0,, Input9->Y:$078C0,, Input0->Y:$078C0,, Input->Y:$078C0,, Input->Y:$078C0,5, Input->Y:$078C0,6, Input->Y:$078C0,7, #define Output7 M70 #define Output8 M70 #define Output9 M70 #define Output0 M70 #define Output M705 #define Output M706 #define Output M707 #define Output M708 Output7->Y:$078C05,0, Output8->Y:$078C05,, Output9->Y:$078C05,, Output0->Y:$078C05,, Output->Y:$078C05,, Output->Y:$078C05,5, Output->Y:$078C05,6, Output->Y:$078C05,7, To address a different card, replace the xx digits in the address locations $07xx00 to $07xx05 to correspond to the base address configured by the dip switch settings. Configuring the Control Word With Turbo PMAC, the control word must be set to 7. This is done by writing (once on power-up) to the control register which is at base address + 7, bits [7:0]. M7000->Y:$078C07,0,8 // For base address $78C00 Open PLC Clear M7000 = 7 Disable PLC Close Using the ACC-65E with Turbo UMAC 6

17 USING THE ACC-65E WITH MACRO In a MACRO configuration, the ACC-65E resides typically in a UMAC MACRO Station with a MACRO8 (legacy) or MACRO6 CPU. The ring controller can be either a Turbo or a Power PMAC. UMAC MACRO Station # Turbo PMAC ring controllers: Turbo Brick family Turbo UMAC with ACC-5E Turbo UltraLite Power PMAC ring controllers: Power Brick family Power UMAC with ACC-5E Power UMAC with ACC-5E Power EtherLite Ring Controller IN OUT OUT IN OUT IN MACRO6 MACRO6 ACC-65E ACC-65E ACC-65E ACC-65E UMAC MACRO Station # Generally, the user s goal is to transfer the ACC-65E I/O data (8 bits per card) from/to the ring controller by reading the -bits of inputs and writing to the -bits of outputs. This I/O data transfer is accomplished using I/O nodes; therefore, it is essential to know: Which I/O nodes are used Which MACRO station I/O node addresses correspond to which Ring Controller I/O node addresses Using the ACC-65E With MACRO 7

18 MACRO6 I/O Node Addressing A MACRO IC consists of a number of auxiliary, servo, and I/O nodes: Auxiliary nodes are Master/Control registers and are for internal firmware use. Servo nodes carry information such as feedback, commands, and flags for motor control. I/O nodes are by default unoccupied and are configurable for transferring miscellaneous data. The MACRO6 CPU is populated with two PMAC style MACRO ICs, each consisting of 6 nodes: auxiliary, 8 servo, and 6 I/O nodes (the legacy MACRO8 has only one IC). I/O Nodes Node Auxiliary Nodes Servo Nodes Each I/O node consists of one -bit and three 6-bit (upper) data registers: bit st 6-bit nd 6-bit rd 6-bit -bit st 6-bit nd 6-bit rd 6-bit -bit st 6-bit nd 6-bit rd 6-bit -bit st 6-bit nd 6-bit rd 6-bit -bit st 6-bit nd 6-bit rd 6-bit -bit st 6-bit nd 6-bit rd 6-bit The MACRO8 CPU is populated with only PMAC Style MACRO IC (IC# 0). Using the ACC-65E With MACRO 8

19 The I/O node data register addresses ($C0XX) for the two MACRO ICs on a station are: MACRO Station IC #0 Node bit X:$C0A0 X:$C0A X:$C0A8 X:$C0AC X:$C0B0 X:$C0B 6-bit X:$C0A X:$C0A5 X:$C0A9 X:$C0AD X:$C0B X:$C0B5 6-bit X:$C0A X:$C0A6 X:$C0AA X:$C0AE X:$C0B X:$C0B6 6-bit X:$C0A X:$C0A7 X:$C0AB X:$C0AF X:$C0B X:$C0B7 MACRO Station IC # Node bit X:$C0E0 X:$C0E X:$C0E8 X:$C0EC X:$C0F0 X:$C0F 6-bit X:$C0E X:$C0E5 X:$C0E9 X:$C0ED X:$C0F X:$C0F5 6-bit X:$C0E X:$C0E6 X:$C0EA X:$C0EE X:$C0F X:$C0F6 6-bit X:$C0E X:$C0E7 X:$C0EB X:$C0EF X:$C0F X:$C0F7 I/O nodes which will be chosen to transfer the ACC-65E(s) data are configurable and chosen by the user depending on availability and I/O node management in the MACRO station. Non-Turbo PMAC Ultralite (legacy) I/O node addresses are the same as MACRO Station IC# 0 node registers. For instance, addresses on the ring controller start at $C0A0, instead of at $780 as seen in the following section. Using the ACC-65E With MACRO 9

20 Ring Controller I/O Node Addressing Turbo PMAC I/O Node Addressing Turbo ring controllers interface with PMAC Style MACRO ICs. The data resides in the bit fields illustrated on the right: Turbo ring controllers can be populated with up to PMAC style MACRO ICs (reported by I90). Below are the I/O node addresses ($7XXXX) for each of the PMAC Style MACRO ICs: Turbo PMAC I/O Node -bit Register 6-bit Register 6-bit Register 6-bit Register Turbo Ring Controller MACRO IC #0 Node Registers Station I/O Node# Ring Controller I/O Node# bit X:$780 X:$78 X:$788 X:$78C X:$780 X:$78 6-bit X:$78 X:$785 X:$789 X:$78D X:$78 X:$785 6-bit X:$78 X:$786 X:$78A X:$78E X:$78 X:$786 6-bit X:$78 X:$787 X:$78B X:$78F X:$78 X:$787 Turbo Ring Controller MACRO IC # Node Registers Station I/O Node# Ring Controller I/O Node# bit X:$790 X:$79 X:$798 X:$79C X:$790 X:$79 6-bit X:$79 X:$795 X:$799 X:$79D X:$79 X:$795 6-bit X:$79 X:$796 X:$79A X:$79E X:$79 X:$796 6-bit X:$79 X:$797 X:$79B X:$79F X:$79 X:$797 Turbo Ring Controller MACRO IC # Node Registers Station I/O Node# Ring Controller I/O Node# bit X:$7A0 X:$7A X:$7A8 X:$7AC X:$7A0 X:$7A 6-bit X:$7A X:$7A5 X:$7A9 X:$7AD X:$7A X:$7A5 6-bit X:$7A X:$7A6 X:$7AA X:$7AE X:$7A X:$7A6 6-bit X:$7A X:$7A7 X:$7AB X:$7AF X:$7A X:$7A7 Turbo Ring Controller MACRO IC # Node Registers Station I/O Node# Ring Controller I/O Node# bit X:$7B0 X:$7B X:$7B8 X:$7BC X:$7B0 X:$7B 6-bit X:$7B X:$7B5 X:$7B9 X:$7BD X:$7B X:$7B5 6-bit X:$7B X:$7B6 X:$7BA X:$7BE X:$7B X:$7B6 6-bit X:$7B X:$7B7 X:$7BB X:$7BF X:$7B X:$7B7 Using the ACC-65E With MACRO 0

21 Power PMAC I/O Node Addressing PMAC Style I/O Node The Power PMAC can interface with the ACC-5E which carries PMAC Style MACRO ICs. The PMAC Style MACRO IC I/O node data registers reside in the bit fields illustrated on the right: And the corresponding structure elements: Structure Element -bit Register 6-bit Register 6-bit Register 6-bit Register Data Register Gate[i].Macro[j][0] Gate[i].Macro[j][] Gate[i].Macro[j][] Gate[i].Macro[j][] bits 6 bits 6 bits 6 bits Where: i is the PMAC Style MACRO IC index j is the I/O node number. Bitwise mapping, into the PMAC Style MACRO structure elements requires Power PMAC firmware version or newer. Using the ACC-65E With MACRO

22 The tables below show I/O Node numbers of the PMAC Style MACRO ICs: Gate[0] Station I/O Node# Ring Controller I/O Node [j] Gate[] Station I/O Node# 6 7 Ring Controller I/O Node [j] Gate[] Station I/O Node# Ring Controller I/O Node [j] Gate[] Station I/O Node# 6 7 Ring Controller I/O Node [j] Using the ACC-65E With MACRO

23 Power PMAC I/O Node Addressing A PMAC style MACRO IC consists of nodes: auxiliary, 6 servo, and I/O nodes. One or more of these ICs can be found in the following hardware: Power Brick Family Power UMAC with ACC-5E Power EtherLite I/O Nodes I/O Nodes Node Auxiliary Nodes Servo Nodes Auxiliary Nodes Servo Nodes Bank B Bank A The Power PMAC can have up to 6 PMAC Style MACRO ICs. ICs present are reported by the variable Macro.ICs. A PMAC Style MACRO IC I/O node consists of data registers: x -bit and x 6-bit residing in the following bit fields: 6-bit Register 6-bit Register 6-bit Register PMAC Style I/O Node -bit Register Using the ACC-65E With MACRO

24 With the PMAC Style MACRO ICs, the I/O node data registers are typically accessed using structure elements, which can be inputs or outputs for either bank: Bank B Bank A Data Register Inputs Outputs Inputs Outputs Gate[i].MacroInB[j][0] Gate[i].MacroOutB[j][0] Gate[i].MacroInA[j][0] Gate[i].MacroOutA[j][0] -bit Gate[i].MacroInB[j][] Gate[i].MacroOutB[j][] Gate[i].MacroInA[j][] Gate[i].MacroOutA[j][] st 6-bit Gate[i].MacroInB[j][] Gate[i].MacroOutB[j][] Gate[i].MacroInA[j][] Gate[i].MacroOutA[j][] nd 6-bit Gate[i].MacroInB[j][] Gate[i].MacroOutB[j][] Gate[i].MacroInA[j][] Gate[i].MacroOutA[j][] rd 6-bit Where: i is the PMAC Style MACRO IC index j is the I/O node number. Bitwise mapping into the PMAC Style MACRO structure elements requires Power PMAC firmware version or newer. Below are example tables showing I/O Node numbers of the first PMAC Style MACRO ICs: Gate[0] Bank A Bank B Station Node# Ring Controller I/O Node [j] Gate[] Bank A Bank B Station Node# Ring Controller I/O Node [j] Gate[] Bank A Bank B Station Node# Ring Controller I/O Node [j] Gate[] Bank A Bank B Station Node# Ring Controller I/O Node [j] Using the ACC-65E With MACRO

25 Configuring MACRO I/O Transfers Having set up the following: Ring Controller MACRO communication for ASCII and MS commands I680 with Turbo PMAC Gate[i].MacroMode with Power PMAC Gate[i].MacroModeA and Gate[i].MacroModeB with Power PMAC MACRO Station MACRO communication for ASCII and MS commands MI996 Enabled the chosen I/O nodes on the ring controller I68 with Turbo PMAC Gate[i].MacroEnable with Power PMAC Gate[i].MacroEnableA and Gate[i].MacroEnableB with Power PMAC Enabled the corresponding I/O nodes on the MACRO station IC MS{anynode},MI975 Typically, masked with the enabled I/O node(s) E.g. MS,MI975=$ enables transfers using I/O node number. Set up the I/O Data Transfer Period MS{anynode},MI9 Typically = The ACC-65E(s) I/O data should now be available to transfer to/from the ring controller. Each ACC-65E possesses 8 bits ( in/ out) of data to be transferred. Depending on the number of cards in the MACRO station and I/O nodes available, one or more of the following methods can be used, stated in the order of simplicity: MS{anynode},MI60 8-bit transfer into a x -bit data register (uses x I/O node) MS{anynode},MI7 8-bit transfer into x -bit data registers (uses x I/O nodes) MS{anynode},MI69/MI70 8-bit transfer into x 6-bit data registers (uses x I/O nodes) {anynode} refers to any activated node on a particular MACRO IC. MS{anynode},MI60 newer. requires MACRO6 CPU firmware.0 or Using the ACC-65E With MACRO 5

26 MS{anynode},MI60 MI60 transfers all 8 bits ( in, out) of an ACC-65E into a single read/write -bit data register. It handles up to x ACC-65Es at consecutive base addresses (e.g. Y:$8800, Y:$9800, Y:$A800) and places the data in x consecutive -bit data registers. MI60 is a 8-bit variable represented as hexadecimal digits which are set up as follows (digit # is leftmost when constructing the word): No. of consecutive nodes: = for I/O node = for I/O nodes = for I/O nodes (max.) Reserved, = 0 Digit #: Reserved, = 0 Starting I/O node register ($C0XX) Starting ACC-65E base address (i.e. $8800) MI60 requires MACRO6 CPU firmware ~.0 or higher. For multiple ACC-65E transfers with MI60, consecutive cards must be under the same chip select. Using the ACC-65E With MACRO 6

27 MI60 example Transferring I/O data for one ACC-65E at address $8800 over node of MACRO IC 0: MS,MI9= // Data transfer period [msec] MS,MI60=$0C0A // MI60 transfer MS,MI975=$ // Enable Mask I/O node MACRO Station ACC-65E ($8800) IN OUT MS,MI60=$0C0A Node, -bit Register Ring Controller Having downloaded the above settings into the MACRO6 station, the inputs can be read and outputs can be transferred from the ring controller side (I/O node ) in the following bit fields: Inputs Outputs Turbo I/O Node Address Data Bits Structure Element (PMAC) Data Bits X:$780 :00 Gate[0].Macro[][0] :00 Power Structure Element (PMAC) Gate[0].MacroInA[][0] Gate[0].MacroOutA[][0] Data Bits :08 Using the ACC-65E With MACRO 7

28 MI60 example Transferring I/O data for two ACC-65Es at consecutive base addresses $8800 and $9800 over nodes and of MACRO IC 0: MS,MI9= MS,MI60=$0C0A MS,MI975=$C ACC-65E ($8800) IN OUT MACRO Station MS,MI60=$0C0A ACC-65E ($9800) IN OUT Node, -bit Register Node, -bit Register Ring Controller Having downloaded the above settings into the MACRO6 station, the inputs can be read and outputs can be transferred from the ring controller side (I/O nodes and ) in the following bit fields: Turbo Power I/O Node Address Data Bits Structure Element (PMAC) Data Bits Structure Element (PMAC) Data Bits st ACC-65E Inputs Outputs X:$780 :00 Gate[0].Macro[][0] :00 Gate[0].MacroInA[][0] Gate[0].MacroOutA[][0] :08 nd ACC-65E Inputs Outputs X:$78 :00 Gate[0].Macro[][0] :00 Gate[0].MacroInA[][0] Gate[0].MacroOutA[][0] :08 Using the ACC-65E With MACRO 8

29 MI60 example Transferring I/O data for three ACC-65Es at consecutive base addresses $8800, $9800, and $A800 over nodes,, and 6: MS,MI9= MS,MI60=$0C0A MS,MI975=$C ACC-65E ($8800) IN OUT MACRO Station ACC-65E ($9800) IN OUT MS,MI60=$0C0A ACC-65E ($A800) IN OUT Node, -bit Register Node, -bit Register Ring Controller Node 6, -bit Register Having downloaded the above settings into the MACRO6 station, the inputs can be read and outputs can be transferred from the ring controller side (I/O nodes,, and 6) in the following bit fields: st ACC-65E Inputs Outputs Turbo I/O Node Address Data Bits Structure Element (PMAC) Data Bits X:$780 :00 Gate[0].Macro[][0] :00 Power Structure Element (PMAC) Gate[0].MacroInA[][0] Gate[0].MacroOutA[][0] Data Bits :08 nd ACC-65E Inputs Outputs X:$78 :00 Gate[0].Macro[][0] :00 Gate[0].MacroInA[][0] Gate[0].MacroOutA[][0] :08 rd ACC-65E Inputs Outputs X:$788 :00 Gate[0].Macro[6][0] :00 Gate[0].MacroInA[6][0] Gate[0].MacroOutA[6][0] :08 Using the ACC-65E With MACRO 9

30 MS{anynode},MI7 MI7 transfers all 8 bits ( in, out) of an ACC-65E into x consecutive I/O node -bit data registers. It handles up to x ACC-65Es at consecutive base addresses (e.g. Y:$8800, Y:$8900, Y:$8A00), and places the data in 6 x consecutive -bit I/O node data registers. MI7 is a 8-bit variable represented as hexadecimal digits which are set up as follows (digit # is leftmost when constructing the word): No. of consecutive node pairs: = for I/O nodes = for I/O nodes = for 6 I/O nodes (max.) No. of -bit banks per board Always = Digit #: Reserved, = 0 Starting I/O node register ($C0XX) Reserved, = Starting ACC-65E base address (i.e. $8800) For multiple ACC-65E transfers with MI7, consecutive cards must be under the same chip select. Using the ACC-65E With MACRO 0

31 MI7 example Transferring I/O data for one ACC-65E at address $8800 over nodes and of MACRO IC 0: MS,MI9= MS,MI7=$0C0A08800 MS,MI975=$C MACRO Station ACC-65E ($8800) IN OUT MS,MI7=$0C0A08800 Node, -bit Node, -bit Ring Controller Having downloaded the above settings into the MACRO6 station, the inputs and outputs are now available to access from the ring controller side (e.g. I/O nodes, ) in the following bit fields: Turbo I/O Node Address Data Bits Structure Element (PMAC) Data Bits Power Structure Element (PMAC) Inputs X:$780 :00 Gate[0].Macro[][0] :00 Gate[0].MacroInA[][0] :08 Outputs X:$78 :00 Gate[0].Macro[][0] :00 Gate[0].MacroOutA[][0] :08 Data Bits Using the ACC-65E With MACRO

32 MI7 example Transferring I/O data for two ACC-65Es at consecutive base addresses $8800 and $8900 over nodes,, 6, and 7 of MACRO IC 0: MS,MI9= MS,MI7=$0C0A08800 MS,MI975=$CC ACC-65E ($8800) IN OUT MACRO Station MS,MI7=$0C0A08800 ACC-65E ($9800) IN OUT Node, -bit Node, -bit Node 6, -bit Ring Controller Node 7, -bit Having downloaded the above settings into the MACRO6 station, the inputs and outputs are now available to access from the ring controller side (e.g. I/O nodes,, 6, and 7) in the following bit fields: st ACC- 65E Turbo I/O Node Address Data Bits Structure Element (PMAC) Data Bits Power Structure Element (PMAC) Inputs X:$780 :00 Gate[0].Macro[][0] :00 Gate[0].MacroInA[][0] :08 Outputs X:$78 :00 Gate[0].Macro[][0] :00 Gate[0].MacroOutA[][0] :08 Data Bits nd ACC- 65E Inputs X:$788 :00 Gate[0].Macro[6][0] :00 Gate[0].MacroInA[6][0] :08 Outputs X:$78C :00 Gate[0].Macro[7][0] :00 Gate[0].MacroOutA[7][0] :08 Using the ACC-65E With MACRO

33 MI7 example Transferring I/O data for three ACC-65Es at consecutive base addresses $8800, $9800, and $A800 over nodes,, 6, 7, 0, and : MS,MI9= MS,MI7=$0C0A08800 MS,MI975=$CCC ACC-65E ($8800) IN OUT MACRO Station ACC-65E ($9800) IN OUT MS,MI7=$0C0A08800 ACC-65E ($A800) IN OUT Node, -bit Node, -bit Node 6, -bit Node 7, -bit Ring Controller Node 0, -bit Node, -bit st ACC- 65E Having downloaded the above settings into the MACRO6 station, the inputs and outputs are now available to access on the ring controller side (I/O nodes,, 6, 7, 0, and ) in the following bit fields: Turbo I/O Node Address Data Bits Structure Element (PMAC) Data Bits Power Structure Element (PMAC) Inputs X:$780 :00 Gate[0].Macro[][0] :00 Gate[0].MacroInA[][0] :08 Outputs X:$78 :00 Gate[0].Macro[][0] :00 Gate[0].MacroOutA[][0] :08 Data Bits nd ACC- 65E Inputs X:$788 :00 Gate[0].Macro[6][0] :00 Gate[0].MacroInA[6][0] :08 Outputs X:$78C :00 Gate[0].Macro[7][0] :00 Gate[0].MacroOutA[7][0] :08 rd ACC- 65E Inputs X:$780 :00 Gate[0].Macro[0][0] :00 Gate[0].MacroInA[0][0] :08 Outputs X:$78 :00 Gate[0].Macro[][0] :00 Gate[0].MacroOutA[][0] :08 Using the ACC-65E With MACRO

34 MS{anynode},MI69/MI70 MI69/MI70 transfers all 8 bits ( in, out) of an ACC-65E into x I/O node 6-bit data registers. It handles up to x ACC-65Es at consecutive base addresses (e.g. Y:$8800, Y:$8900, Y:$8A00), and places the data in 9 x consecutive 6-bit I/O node data registers. MI69/70 are 8-bit variables represented as hexadecimal digits which are set up as follows (digit # is leftmost when constructing the word): No. of consecutive nodes: = for IO node = for IO nodes = for IO nodes (max.) No. of 6-bit banks per board Always = Digit #: Reserved, = 0 Starting I/O node register ($C0XX) Reserved, = Starting ACC-68E base address (i.e. $8800) For multiple ACC-65E transfers with MI69/MI70, consecutive cards must be under the same chip select. Using the ACC-65E With MACRO

35 MI69/70 example Transferring I/O data for one ACC-65E at address $8800 over node of MACRO IC 0: MS,MI9= MS,MI69=$0C0A8800 MS,MI975=$ Ring Controller Node, -bit Reg. Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg. MS,MI69=$0C0A8800 OUT IN ACC-65E ($8800) MACRO Station Having downloaded the above settings into the MACRO6 station, the inputs and outputs are now available to access on the ring controller side (I/O node ) in the following bit fields: Inputs Outputs Turbo I/O Node Address Data Bits Structure Element (PMAC) Data Bits Power Structure Element (PMAC) X:$78 :08 Gate[0].Macro[][] :08 Gate[0].MacroInA[][] :6 X:$78 5:08 Gate[0].Macro[][] 5:08 Gate[0].MacroInA[][] :6 X:$78 :6 Gate[0].Macro[][] :6 Gate[0].MacroOutA[][] : X:$78 :08 Gate[0].Macro[][] :08 Gate[0].MacroOutA[][] :6 Data Bits Using the ACC-65E With MACRO 5

36 MI69/70 example Transferring I/O data for two ACC-65Es at consecutive base addresses $8800 and $9800 over nodes and of MACRO IC 0: MS,MI9= MS,MI69=$0C0A8800 MS,MI975=$C Node, -bit Reg. Ring Controller Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg. Node, -bit Reg. Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg. MS,MI69=$0C0A8800 OUT IN OUT IN ACC-65E ($8800) ACC-65E ($9800) MACRO Station Having downloaded the above settings into the MACRO6 station, the inputs and outputs are now available to access on the ring controller side (I/O nodes and ) in the following bit fields: Turbo Power I/O Node Address Data Bits Structure Element (PMAC) Data Bits Structure Element (PMAC) Data Bits st ACC- 65E Inputs Outputs X:$78 :08 Gate[0].Macro[][] :08 Gate[0].MacroInA[][] :6 X:$78 6:08 Gate[0].Macro[][] 6:08 Gate[0].MacroInA[][] :6 X:$78 :6 Gate[0].Macro[][] :6 Gate[0].MacroOutA[][] : X:$78 :08 Gate[0].Macro[][] :08 Gate[0].MacroOutA[][] :6 nd ACC- 65E Inputs Outputs X:$785 :08 Gate[0].Macro[][] :08 Gate[0].MacroInA[][] :6 X:$786 5:08 Gate[0].Macro[][] 5:08 Gate[0].MacroInA[][] :6 X:$786 :6 Gate[0].Macro[][] :6 Gate[0].MacroOutA[][] : X:$787 :08 Gate[0].Macro[][] :08 Gate[0].MacroOutA[][] :6 Using the ACC-65E With MACRO 6

37 Accessing the Transferred Data Having transferred the ACC-65E I/O data to and from the MACRO station and into the ring controller s registers mentioned above, bitwise mapping is the final step. With the PMAC style MACRO IC: The inputs can be bitwise mapped and read. The output state is not reported, and writing to two separate bits simultaneously (without using the full word) is not possible, thus an image word is required. With the PMAC style MACRO IC: The inputs can be bitwise mapped and read. The outputs can be directly bitwise mapped, written to, and reported. Outputs Mirror Image Concept A mirror image is a memory location on the ring controller, typically open or scratch memory that mimics the state of the ACC-65E outputs (residing in the MACRO station). This can be done in a PLC program. The following are recommended memory registers to use: Turbo PMAC Open Memory Registers ( bits) $0F0-$0FF (X and Y) Power PMAC Open Memory Registers ( bits), unsigned Sys.Udata[i] Use Sys.Udata[], Sys.Udata[], Sys.Udata[] User writes to / reads single bits of open memory PLC copies open memory to appropriate node Bitwise mapping to user memory structure elements in Power PMAC is not allowed. Explicit syntax with offset address must be used. The offset address is found by multiplying the element structure index by. To the right is an example of the first unsigned open memory structure elements and their corresponding address offsets: Structure Element Address Offset Sys.Udata[] U.USER: Sys.Udata[] U.USER: 8 Sys.Udata[] U.USER: Sys.Udata[] U.USER:6 A large number of self-addressed (default Sys.pushm) pointers in Power PMAC use Sys.Udata[0]; therefore, it is highly advised NOT to use it as a general purpose user memory. Using the ACC-65E With MACRO 7

38 Turbo PMAC MI60 Mapping Example MI60 is used to transfer ACC-65E data through MACRO IC 0 node of the ring controller, which places the bits of inputs and bits of outputs in the same -bit data register: Inputs I/O Node Outputs Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg. The inputs are mapped into the -bit register of node #define Input M700 #define Input M700 #define Input M700 #define Input M700 #define Input5 M7005 #define Input6 M7006 #define Input7 M7007 #define Input8 M7008 #define Input9 M7009 #define Input0 M700 #define Input M70 #define Input M70 #define Input M70 #define Input M70 #define Input5 M705 #define Input6 M706 #define Input7 M707 #define Input8 M708 #define Input9 M709 #define Input0 M700 #define Input M70 #define Input M70 #define Input M70 #define Input M70 Input->X:$780,0, Input->X:$780,, Input->X:$780,, Input->X:$780,, Input5->X:$780,, Input6->X:$780,5, Input7->X:$780,6, Input8->X:$780,7, Input9->X:$780,8, Input0->X:$780,9, Input->X:$780,0, Input->X:$780,, Input->X:$780,, Input->X:$780,, Input5->X:$780,, Input6->X:$780,5, Input7->X:$780,6, Input8->X:$780,7, Input9->X:$780,8, Input0->X:$780,9, Input->X:$780,0, Input->X:$780,, Input->X:$780,, Input->X:$780,, Using the ACC-65E With MACRO 8

39 The outputs require an image word. We will use Y:$0FF ( bits) open memory register; therefore, the bitwise mapping of the outputs should point to the open memory. #define Output M705 #define Output M706 #define Output M707 #define Output M708 #define Output5 M709 #define Output6 M700 #define Output7 M70 #define Output8 M70 #define Output9 M70 #define Output0 M70 #define Output M705 #define Output M706 #define Output M707 #define Output M708 #define Output5 M709 #define Output6 M700 #define Output7 M70 #define Output8 M70 #define Output9 M70 #define Output0 M70 #define Output M705 #define Output M706 #define Output M707 #define Output M708 Output->Y:$0FF,0, Output->Y:$0FF,, Output->Y:$0FF,, Output->Y:$0FF,, Output5->Y:$0FF,, Output6->Y:$0FF,5, Output7->Y:$0FF,6, Output8->Y:$0FF,7, Output9->Y:$0FF,8, Output0->Y:$0FF,9, Output->Y:$0FF,0, Output->Y:$0FF,, Output->Y:$0FF,, Output->Y:$0FF,, Output5->Y:$0FF,, Output6->Y:$0FF,5, Output7->Y:$0FF,6, Output8->Y:$0FF,7, Output9->Y:$0FF,8, Output0->Y:$0FF,9, Output->Y:$0FF,0, Output->Y:$0FF,, Output->Y:$0FF,, Output->Y:$0FF,, The following mirror image PLC (which should be executing constantly) will copy the outputs into node : #define NTwenty M709 ; Node, -bit data register #define OutMirror M7050 ; Mirror word, open memory NTwenty->Y:$780,0, OutMirror->Y:$0FF,0, OutMirror = 0 Open PLC Clear NTwenty = OutMirror Close ; Node, -bit data register ; Open memmory register ; Save/Initialize to zero or desired state ; Update data register The output states are now reported and can now be toggled individually using the bitwise assignments to the open memory register. Using the ACC-65E With MACRO 9

40 Turbo PMAC MI7 Mapping Example MI7 is used to transfer ACC-65E data through MACRO IC 0 nodes and of the ring controller, which places the bits of inputs in the -bit register of node and the bits of outputs in the -bit register of node : I/O Node I/O Node Node. -bit Register Node. -bit Register Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg The inputs are mapped into the -bit register of node #define Input M700 #define Input M700 #define Input M700 #define Input M700 #define Input5 M7005 #define Input6 M7006 #define Input7 M7007 #define Input8 M7008 #define Input9 M7009 #define Input0 M700 #define Input M70 #define Input M70 #define Input M70 #define Input M70 #define Input5 M705 #define Input6 M706 #define Input7 M707 #define Input8 M708 #define Input9 M709 #define Input0 M700 #define Input M70 #define Input M70 #define Input M70 #define Input M70 Input->X:$780,0, Input->X:$780,, Input->X:$780,, Input->X:$780,, Input5->X:$780,, Input6->X:$780,5, Input7->X:$780,6, Input8->X:$780,7, Input9->X:$780,8, Input0->X:$780,9, Input->X:$780,0, Input->X:$780,, Input->X:$780,, Input->X:$780,, Input5->X:$780,, Input6->X:$780,5, Input7->X:$780,6, Input8->X:$780,7, Input9->X:$780,8, Input0->X:$780,9, Input->X:$780,0, Input->X:$780,, Input->X:$780,, Input->X:$780,, Using the ACC-65E With MACRO 0

41 The outputs require an image word. We will use Y:$0FF ( bits) open memory register (to copy the bits of node ); therefore, the bitwise mapping of the outputs should point to the open memory. #define Output M705 #define Output M706 #define Output M707 #define Output M708 #define Output5 M709 #define Output6 M700 #define Output7 M70 #define Output8 M70 #define Output9 M70 #define Output0 M70 #define Output M705 #define Output M706 #define Output M707 #define Output M708 #define Output5 M709 #define Output6 M700 #define Output7 M70 #define Output8 M70 #define Output9 M70 #define Output0 M70 #define Output M705 #define Output M706 #define Output M707 #define Output M708 Output->Y:$0FF,0, Output->Y:$0FF,, Output->Y:$0FF,, Output->Y:$0FF,, Output5->Y:$0FF,, Output6->Y:$0FF,5, Output7->Y:$0FF,6, Output8->Y:$0FF,7, Output9->Y:$0FF,8, Output0->Y:$0FF,9, Output->Y:$0FF,0, Output->Y:$0FF,, Output->Y:$0FF,, Output->Y:$0FF,, Output5->Y:$0FF,, Output6->Y:$0FF,5, Output7->Y:$0FF,6, Output8->Y:$0FF,7, Output9->Y:$0FF,8, Output0->Y:$0FF,9, Output->Y:$0FF,0, Output->Y:$0FF,, Output->Y:$0FF,, Output->Y:$0FF,, The following mirror image PLC (which should be executing constantly) will copy the outputs into node : #define NTwenty M709 ; Node, -bit register #define OutMirror M7050 ; Mirror word, open memory NTwenty->Y:$78,0, ; -bit register, node OutMirror->Y:$0FF,0, ; Open memmory register OutMirror = 0 ; Save/Initialize to zero or desired state Open PLC Clear NTwenty = OutMirror Close ; Update data register The output states are now reported and can be toggled individually using the bitwise assignments to the open memory register. Using the ACC-65E With MACRO

42 Turbo PMAC MI69/70 Mapping Example MI69 / MI70 is used to transfer ACC-66E data through MACRO IC 0 node of the ring controller, which places the data in registers as illustrated on the right: The lower 6 bits of the bits of inputs reside in the first 6- bit register, and the upper 8 bits of the bits of inputs reside in the lower byte of the second 6-bit register. The lower 8 bits of the bits of outputs reside in the upper byte of the second 6-bit register, and the upper 6 bits of the bits of outputs reside in the third 6-bit register. I/O Node Node. -bit Register (not used in this example) Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg The inputs are mapped into 6-bit registers of node : #define Input M700 #define Input M700 #define Input M700 #define Input M700 #define Input5 M7005 #define Input6 M7006 #define Input7 M7007 #define Input8 M7008 #define Input9 M7009 #define Input0 M700 #define Input M70 #define Input M70 #define Input M70 #define Input M70 #define Input5 M705 #define Input6 M706 #define Input7 M707 #define Input8 M708 #define Input9 M709 #define Input0 M700 #define Input M70 #define Input M70 #define Input M70 #define Input M70 Input->X:$78,8, Input->X:$78,9, Input->X:$78,0, Input->X:$78,, Input5->X:$78,, Input6->X:$78,, Input7->X:$78,, Input8->X:$78,5, Input9->X:$78,6, Input0->X:$78,7, Input->X:$78,8, Input->X:$78,9, Input->X:$78,0, Input->X:$78,, Input5->X:$78,, Input6->X:$78,, Input7->X:$78,8, Input8->X:$78,9, Input9->X:$78,0, Input0->X:$78,, Input->X:$78,, Input->X:$78,, Input->X:$78,, Input->X:$78,5, Using the ACC-65E With MACRO

43 The outputs require an image word We will use Y:$0FF open memory register to create an image word; therefore, the bitwise mapping of the outputs should point to the open memory. #define Output M705 #define Output M706 #define Output M707 #define Output M708 #define Output5 M709 #define Output6 M700 #define Output7 M70 #define Output8 M70 #define Output9 M70 #define Output0 M70 #define Output M705 #define Output M706 #define Output M707 #define Output M708 #define Output5 M709 #define Output6 M700 #define Output7 M70 #define Output8 M70 #define Output9 M70 #define Output0 M70 #define Output M705 #define Output M706 #define Output M707 #define Output M708 Output->Y:$0FF,0, Output->Y:$0FF,, Output->Y:$0FF,, Output->Y:$0FF,, Output5->Y:$0FF,, Output6->Y:$0FF,5, Output7->Y:$0FF,6, Output8->Y:$0FF,7, Output9->Y:$0FF,8, Output0->Y:$0FF,9, Output->Y:$0FF,0, Output->Y:$0FF,, Output->Y:$0FF,, Output->Y:$0FF,, Output5->Y:$0FF,, Output6->Y:$0FF,5, Output7->Y:$0FF,6, Output8->Y:$0FF,7, Output9->Y:$0FF,8, Output0->Y:$0FF,9, Output->Y:$0FF,0, Output->Y:$0FF,, Output->Y:$0FF,, Output->Y:$0FF,, The following mirror image PLC (which should be executing constantly) will copy the outputs into node : #define NSecond6 M709 ; Node, second 6-bit register #define NThird6 M7050 ; Node, third 6-bit register #define OutMirror M705 ; Mirror word, open memory NSecond6->X:$78,8,6 ; Second 6-bit register, node NThird6->X:$78,8,6 ; Third 6-bit register, node OutMirror->Y:$0FF,0, ; Open memory OutMirror = 0 ; Save/Initialize to zero or desired state Open PLC Clear NSecond6 = OutMirror & $0000FF ; Mask with lower 8 bits NThird6 = OutMirror & $FFFF00/$00 ; Mask OutMirror with upper 6 bits and shift to lower 6 Close The output states are now reported and can be toggled individually using the bitwise assignments to the open memory register. Using the ACC-65E With MACRO

44 Power PMAC MI60 Mapping Example MI60 is used to transfer ACC-65E data through MACRO IC 0 node of the ring controller, which places the bits of inputs and bits of outputs in the same -bit data register: Inputs I/O Node Outputs Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg The inputs are mapped into the bits of node : PTR Input->Gate[0].Macro[][0].0.; PTR Input->Gate[0].Macro[][0]..; PTR Input->Gate[0].Macro[][0]..; PTR Input->Gate[0].Macro[][0]..; PTR Input5->Gate[0].Macro[][0]..; PTR Input6->Gate[0].Macro[][0].5.; PTR Input7->Gate[0].Macro[][0].6.; PTR Input8->Gate[0].Macro[][0].7.; PTR Input9->Gate[0].Macro[][0].8.; PTR Input0->Gate[0].Macro[][0].9.; PTR Input->Gate[0].Macro[][0].0.; PTR Input->Gate[0].Macro[][0]..; PTR Input->Gate[0].Macro[][0]..; PTR Input->Gate[0].Macro[][0]..; PTR Input5->Gate[0].Macro[][0]..; PTR Input6->Gate[0].Macro[][0].5.; PTR Input7->Gate[0].Macro[][0].6.; PTR Input8->Gate[0].Macro[][0].7.; PTR Input9->Gate[0].Macro[][0].8.; PTR Input0->Gate[0].Macro[][0].9.; PTR Input->Gate[0].Macro[][0].0.; PTR Input->Gate[0].Macro[][0]..; PTR Input->Gate[0].Macro[][0]..; PTR Input->Gate[0].Macro[][0]..; Bitwise mapping with PMAC style MACRO IC is supported starting with Power PMAC firmware version Using the ACC-65E With MACRO

45 The outputs require an image word. We will use Sys.Udata[] open memory register to create the image word; therefore, the bitwise mapping of the outputs: PTR Output->U.USER:.0.; PTR Output->U.USER:..; PTR Output->U.USER:..; PTR Output->U.USER:..; PTR Output5->U.USER:..; PTR Output6->U.USER:.5.; PTR Output7->U.USER:.6.; PTR Output8->U.USER:.7.; PTR Output9->U.USER:.8.; PTR Output0->U.USER:.9.; PTR Output->U.USER:.0.; PTR Output->U.USER:..; PTR Output->U.USER:..; PTR Output->U.USER:..; PTR Output5->U.USER:..; PTR Output6->U.USER:.5.; PTR Output7->U.USER:.6.; PTR Output8->U.USER:.7.; PTR Output9->U.USER:.8.; PTR Output0->U.USER:.9.; PTR Output->U.USER:.0.; PTR Output->U.USER:..; PTR Output->U.USER:..; PTR Output->U.USER:..; Bitwise mapping to user memory structure elements is not allowed. Explicit syntax with offset address must be used. The offset address is found by multiplying the element structure index by. To the right is an example of the first unsigned open memory structure elements and their corresponding address offsets: Structure Element Sys.Udata[] Sys.Udata[] Sys.Udata[] Sys.Udata[] Address Offset U.USER: U.USER:8 U.USER: U.USER:6 A large number of self-addressed (default Sys.pushm) pointers in Power PMAC use Sys.Udata[0]; therefore, it is highly advised NOT to use it as general purpose user memory. The following mirror image PLC (which should be executing constantly) will copy the outputs into node : PTR NTwenty->Gate[0].Macro[][0]; PTR OutMirror->U.USER:.0.; OutMirror = 0 // node (shared with inputs) // Mirror Word, shared user memmory // Save/initialize to zero or desired state Open PLC NTwenty = OutMirror Close // Update data register The output states are now reported and can be toggled individually using the bitwise assignments to the open memory register. Using the ACC-65E With MACRO 5

46 Power PMAC MI7 Mapping Example MI7 is used to transfer ACC-65E data to MACRO IC 0 nodes and of the ring controller, which places the bits of inputs in the -bit register of node and the bits of outputs in the -bit register of node : I/O Node I/O Node Node. -bit Register Node. -bit Register Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg The inputs are mapped into the bits of node : PTR Input->Gate[0].Macro[][0].0.; PTR Input->Gate[0].Macro[][0]..; PTR Input->Gate[0].Macro[][0]..; PTR Input->Gate[0].Macro[][0]..; PTR Input5->Gate[0].Macro[][0]..; PTR Input6->Gate[0].Macro[][0].5.; PTR Input7->Gate[0].Macro[][0].6.; PTR Input8->Gate[0].Macro[][0].7.; PTR Input9->Gate[0].Macro[][0].8.; PTR Input0->Gate[0].Macro[][0].9.; PTR Input->Gate[0].Macro[][0].0.; PTR Input->Gate[0].Macro[][0]..; PTR Input->Gate[0].Macro[][0]..; PTR Input->Gate[0].Macro[][0]..; PTR Input5->Gate[0].Macro[][0]..; PTR Input6->Gate[0].Macro[][0].5.; PTR Input7->Gate[0].Macro[][0].6.; PTR Input8->Gate[0].Macro[][0].7.; PTR Input9->Gate[0].Macro[][0].8.; PTR Input0->Gate[0].Macro[][0].9.; PTR Input->Gate[0].Macro[][0].0.; PTR Input->Gate[0].Macro[][0]..; PTR Input->Gate[0].Macro[][0]..; PTR Input->Gate[0].Macro[][0]..; Bitwise mapping with PMAC style MACRO IC is supported starting with Power PMAC firmware version Using the ACC-65E With MACRO 6

47 The outputs require an image word. We will use Sys.Udata[] open memory register (to copy the bits of node ) to create the image word. Therefore, the bitwise mapping of the outputs: PTR Output->U.USER:.0.; PTR Output->U.USER:..; PTR Output->U.USER:..; PTR Output->U.USER:..; PTR Output5->U.USER:..; PTR Output6->U.USER:.5.; PTR Output7->U.USER:.6.; PTR Output8->U.USER:.7.; PTR Output9->U.USER:.8.; PTR Output0->U.USER:.9.; PTR Output->U.USER:.0.; PTR Output->U.USER:..; PTR Output->U.USER:..; PTR Output->U.USER:..; PTR Output5->U.USER:..; PTR Output6->U.USER:.5.; PTR Output7->U.USER:.6.; PTR Output8->U.USER:.7.; PTR Output9->U.USER:.8.; PTR Output0->U.USER:.9.; PTR Output->U.USER:.0.; PTR Output->U.USER:..; PTR Output->U.USER:..; PTR Output->U.USER:..; Bitwise mapping to user memory structure elements is not allowed. Explicit syntax with offset address must be used. The offset address is found by multiplying the element structure index by. To the right is an example of the first unsigned open memory structure elements and their corresponding address offsets: Structure Element Sys.Udata[] Sys.Udata[] Sys.Udata[] Sys.Udata[] Address Offset U.USER: U.USER:8 U.USER: U.USER:6 A large number of self-addressed (default Sys.pushm) pointers in Power PMAC use Sys.Udata[0]; therefore, it is highly advised NOT to use it as general purpose user memory. The following PLC (which should be executing constantly) will copy the outputs into node : PTR NTwenty->Gate[0].Macro[][0]; // -bit register, node PTR OutMirror->U.USER:.0.; // Mirror Word, shared user memory OutMirror = 0 // Save/initialize to zero or desired state Open PLC NTwenty = OutMirror Close // Update data register The output states are now reported and can be toggled individually using the bitwise assignments to the open memory register. Using the ACC-65E With MACRO 7

48 Power PMAC MI69/70 Mapping Example MI69 / MI70 is used to transfer ACC-65E data through MACRO IC 0 node of the ring controller, which places the data as illustrated on the right: The lower 6 bits of the bits of inputs reside in the first 6-bit register, and the upper 8 bits of the bits of inputs reside in the lower byte of the second 6-bit register. The lower 8 bits of the bits of outputs reside in the upper byte of the second 6-bit register, and the upper 6 bits of the bits of outputs reside in the third 6-bit register. I/ O Node Node. - bit Register Node, 6- bit Reg. Node, 6- bit Reg. Node, 6- bit Reg The inputs are mapped into 6-bit registers of node : PTR Input->Gate[0].Macro[][].8. PTR Input->Gate[0].Macro[][].9. PTR Input->Gate[0].Macro[][].0. PTR Input->Gate[0].Macro[][].. PTR Input5->Gate[0].Macro[][].. PTR Input6->Gate[0].Macro[][].. PTR Input7->Gate[0].Macro[][].. PTR Input8->Gate[0].Macro[][].5. PTR Input9->Gate[0].Macro[][].6. PTR Input0->Gate[0].Macro[][].7. PTR Input->Gate[0].Macro[][].8. PTR Input->Gate[0].Macro[][].9. PTR Input->Gate[0].Macro[][].0. PTR Input->Gate[0].Macro[][].. PTR Input5->Gate[0].Macro[][].. PTR Input6->Gate[0].Macro[][].. PTR Input7->Gate[0].Macro[][].8. PTR Input8->Gate[0].Macro[][].9. PTR Input9->Gate[0].Macro[][].0. PTR Input0->Gate[0].Macro[][].. PTR Input->Gate[0].Macro[][].. PTR Input->Gate[0].Macro[][].. PTR Input->Gate[0].Macro[][].. PTR Input->Gate[0].Macro[][].5. Bitwise mapping with PMAC style MACRO IC is supported starting with Power PMAC firmware version Using the ACC-65E With MACRO 8

49 The outputs require an image word. We will use Sys.Udata[] open memory register to create the image word. Therefore, the bitwise mapping of the outputs: PTR Output->U.USER:.0.; PTR Output->U.USER:..; PTR Output->U.USER:..; PTR Output->U.USER:..; PTR Output5->U.USER:..; PTR Output6->U.USER:.5.; PTR Output7->U.USER:.6.; PTR Output8->U.USER:.7.; PTR Output9->U.USER:.8.; PTR Output0->U.USER:.9.; PTR Output->U.USER:.0.; PTR Output->U.USER:..; PTR Output->U.USER:..; PTR Output->U.USER:..; PTR Output5->U.USER:..; PTR Output6->U.USER:.5.; PTR Output7->U.USER:.6.; PTR Output8->U.USER:.7.; PTR Output9->U.USER:.8.; PTR Output0->U.USER:.9.; PTR Output->U.USER:.0.; PTR Output->U.USER:..; PTR Output->U.USER:..; PTR Output->U.USER:..; Bitwise mapping to user memory structure elements is not allowed. Explicit syntax with offset address must be used. The offset address is found by multiplying the element structure index by. To the right is an example of the first unsigned open memory structure elements and their corresponding address offsets: Structure Element Sys.Udata[] Sys.Udata[] Sys.Udata[] Sys.Udata[] Address Offset U.USER: U.USER:8 U.USER: U.USER:6 A large number of self-addressed (default Sys.pushm) pointers in Power PMAC use Sys.Udata[0]; therefore, it is highly advised NOT to use it as general purpose user memory. The following mirror image PLC (which should be executing constantly) will copy the outputs into node : PTR NSecond6->Gate[0].Macro[][]; PTR NThird6->Gate[0].Macro[][]; PTR OutMirror->U.USER:.0.; OutMirror = 0 // Node, Second 6-bit register (upper 8 bits) // Node, Third 6-bit register (upper 6 bits) // Mirror Word, shared user memory // Save/initialize to zero or desired state Open PLC NSecond6 = OutMirror & $0000FF <<6 NThird6 = OutMirror & $FFFF00 Close // Update nd 6-bit reg; shift to upper 6-bits // Update node third 6-bit register The output states are now reported and can be toggled individually using the bitwise assignments to the open memory register. Using the ACC-65E With MACRO 9

50 Power PMAC MI60 Mapping Example MI60 is used to transfer ACC-65E data through MACRO IC 0 Bank A node of the ring controller, which places the bits of inputs in the IN -bit data register of node, and the bits of outputs in the OUT -bit data register of node : I/O Node Inputs Outputs Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg Inputs PTR Input->Gate[0].MacroInA[][0].8.; PTR Input->Gate[0].MacroInA[][0].9.; PTR Input->Gate[0].MacroInA[][0].0.; PTR Input->Gate[0].MacroInA[][0]..; PTR Input5->Gate[0].MacroInA[][0]..; PTR Input6->Gate[0].MacroInA[][0]..; PTR Input7->Gate[0].MacroInA[][0]..; PTR Input8->Gate[0].MacroInA[][0].5.; PTR Input9->Gate[0].MacroInA[][0].6.; PTR Input0->Gate[0].MacroInA[][0].7.; PTR Input->Gate[0].MacroInA[][0].8.; PTR Input->Gate[0].MacroInA[][0].9.; PTR Input->Gate[0].MacroInA[][0].0.; PTR Input->Gate[0].MacroInA[][0]..; PTR Input5->Gate[0].MacroInA[][0]..; PTR Input6->Gate[0].MacroInA[][0]..; PTR Input7->Gate[0].MacroInA[][0]..; PTR Input8->Gate[0].MacroInA[][0].5.; PTR Input9->Gate[0].MacroInA[][0].6.; PTR Input0->Gate[0].MacroInA[][0].7.; PTR Input->Gate[0].MacroInA[][0].8.; PTR Input->Gate[0].MacroInA[][0].9.; PTR Input->Gate[0].MacroInA[][0].0.; PTR Input->Gate[0].MacroInA[][0]..; Outputs PTR Output->Gate[0].MacroOutA[][0].8.; PTR Output->Gate[0].MacroOutA[][0].9.; PTR Output->Gate[0].MacroOutA[][0].0.; PTR Output->Gate[0].MacroOutA[][0]..; PTR Output5->Gate[0].MacroOutA[][0]..; PTR Output6->Gate[0].MacroOutA[][0]..; PTR Output7->Gate[0].MacroOutA[][0]..; PTR Output8->Gate[0].MacroOutA[][0].5.; PTR Output9->Gate[0].MacroOutA[][0].6.; PTR Output0->Gate[0].MacroOutA[][0].7.; PTR Output->Gate[0].MacroOutA[][0].8.; PTR Output->Gate[0].MacroOutA[][0].9.; PTR Output->Gate[0].MacroOutA[][0].0.; PTR Output->Gate[0].MacroOutA[][0]..; PTR Output5->Gate[0].MacroOutA[][0]..; PTR Output6->Gate[0].MacroOutA[][0]..; PTR Output7->Gate[0].MacroOutA[][0]..; PTR Output8->Gate[0].MacroOutA[][0].5.; PTR Output9->Gate[0].MacroOutA[][0].6.; PTR Output0->Gate[0].MacroOutA[][0].7.; PTR Output->Gate[0].MacroOutA[][0].8.; PTR Output->Gate[0].MacroOutA[][0].9.; PTR Output->Gate[0].MacroOutA[][0].0.; PTR Output->Gate[0].MacroOutA[][0]..; With Power PMAC, the outputs can be directly bitwise mapped, written to, and reported. Mirror word is not required. Using the ACC-65E With MACRO 50

51 Power PMAC MI7 Mapping Example MI7 is used to transfer ACC-65E data through MACRO IC 0 Bank A nodes and of the ring controller, which places the bits of inputs in the In -bit data register of node and the bits of outputs in the Out -bit register of node : I/O Node I/O Node Node, -bit Register Node, -bit Register Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg Inputs PTR Input->Gate[0].MacroInA[][0].8.; PTR Input->Gate[0].MacroInA[][0].9.; PTR Input->Gate[0].MacroInA[][0].0.; PTR Input->Gate[0].MacroInA[][0]..; PTR Input5->Gate[0].MacroInA[][0]..; PTR Input6->Gate[0].MacroInA[][0]..; PTR Input7->Gate[0].MacroInA[][0]..; PTR Input8->Gate[0].MacroInA[][0].5.; PTR Input9->Gate[0].MacroInA[][0].6.; PTR Input0->Gate[0].MacroInA[][0].7.; PTR Input->Gate[0].MacroInA[][0].8.; PTR Input->Gate[0].MacroInA[][0].9.; PTR Input->Gate[0].MacroInA[][0].0.; PTR Input->Gate[0].MacroInA[][0]..; PTR Input5->Gate[0].MacroInA[][0]..; PTR Input6->Gate[0].MacroInA[][0]..; PTR Input7->Gate[0].MacroInA[][0]..; PTR Input8->Gate[0].MacroInA[][0].5.; PTR Input9->Gate[0].MacroInA[][0].6.; PTR Input0->Gate[0].MacroInA[][0].7.; PTR Input->Gate[0].MacroInA[][0].8.; PTR Input->Gate[0].MacroInA[][0].9.; PTR Input->Gate[0].MacroInA[][0].0.; PTR Input->Gate[0].MacroInA[][0]..; Outputs PTR Output->Gate[0].MacroOutA[][0].8.; PTR Output->Gate[0].MacroOutA[][0].9.; PTR Output->Gate[0].MacroOutA[][0].0.; PTR Output->Gate[0].MacroOutA[][0]..; PTR Output5->Gate[0].MacroOutA[][0]..; PTR Output6->Gate[0].MacroOutA[][0]..; PTR Output7->Gate[0].MacroOutA[][0]..; PTR Output8->Gate[0].MacroOutA[][0].5.; PTR Output9->Gate[0].MacroOutA[][0].6.; PTR Output0->Gate[0].MacroOutA[][0].7.; PTR Output->Gate[0].MacroOutA[][0].8.; PTR Output->Gate[0].MacroOutA[][0].9.; PTR Output->Gate[0].MacroOutA[][0].0.; PTR Output->Gate[0].MacroOutA[][0]..; PTR Output5->Gate[0].MacroOutA[][0]..; PTR Output6->Gate[0].MacroOutA[][0]..; PTR Output7->Gate[0].MacroOutA[][0]..; PTR Output8->Gate[0].MacroOutA[][0].5.; PTR Output9->Gate[0].MacroOutA[][0].6.; PTR Output0->Gate[0].MacroOutA[][0].7.; PTR Output->Gate[0].MacroOutA[][0].8.; PTR Output->Gate[0].MacroOutA[][0].9.; PTR Output->Gate[0].MacroOutA[][0].0.; PTR Output->Gate[0].MacroOutA[][0]..; With Power PMAC, the outputs can be directly bitwise mapped, written to, and reported. Mirror word is not required. Using the ACC-65E With MACRO 5

52 Power PMAC MI69/70 Mapping Example MI69 / MI70 is used to transfer ACC-65E data through MACRO IC 0 Bank A node of the ring controller, which places the data as illustrated on the right: The lower 6 bits of the bits of inputs reside in the first 6-bit register, and the upper 8 bits of the bits of inputs reside in the lower byte of the second 6-bit register. All in In registers. The lower 8 bits of the bits of outputs reside in the upper byte of the second 6-bit register, and the upper 6 bits of the bits of outputs reside in the third 6-bit register. All in Out registers. I/O Node Node. -bit Register Node, 6-bit Reg. Node, 6-bit Reg. Node, 6-bit Reg Inputs PTR Input->Gate[0].MacroInA[][].6.; PTR Input->Gate[0].MacroInA[][].7.; PTR Input->Gate[0].MacroInA[][].8.; PTR Input->Gate[0].MacroInA[][].9.; PTR Input5->Gate[0].MacroInA[][].0.; PTR Input6->Gate[0].MacroInA[][]..; PTR Input7->Gate[0].MacroInA[][]..; PTR Input8->Gate[0].MacroInA[][]..; PTR Input9->Gate[0].MacroInA[][]..; PTR Input0->Gate[0].MacroInA[][].5.; PTR Input->Gate[0].MacroInA[][].6.; PTR Input->Gate[0].MacroInA[][].7.; PTR Input->Gate[0].MacroInA[][].8.; PTR Input->Gate[0].MacroInA[][].9.; PTR Input5->Gate[0].MacroInA[][].0.; PTR Input6->Gate[0].MacroInA[][]..; PTR Input7->Gate[0].MacroInA[][].6.; PTR Input8->Gate[0].MacroInA[][].7.; PTR Input9->Gate[0].MacroInA[][].8.; PTR Input0->Gate[0].MacroInA[][].9.; PTR Input->Gate[0].MacroInA[][].0.; PTR Input->Gate[0].MacroInA[][]..; PTR Input->Gate[0].MacroInA[][]..; PTR Input->Gate[0].MacroInA[][]..; Outputs PTR Output->Gate[0].MacroOutA[][]..; PTR Output->Gate[0].MacroOutA[][].5.; PTR Output->Gate[0].MacroOutA[][].6.; PTR Output->Gate[0].MacroOutA[][].7.; PTR Output5->Gate[0].MacroOutA[][].8.; PTR Output6->Gate[0].MacroOutA[][].9.; PTR Output7->Gate[0].MacroOutA[][].0.; PTR Output8->Gate[0].MacroOutA[][]..; PTR Output9->Gate[0].MacroOutA[][].6.; PTR Output0->Gate[0].MacroOutA[][].7.; PTR Output->Gate[0].MacroOutA[][].8.; PTR Output->Gate[0].MacroOutA[][].9.; PTR Output->Gate[0].MacroOutA[][].0.; PTR Output->Gate[0].MacroOutA[][]..; PTR Output5->Gate[0].MacroOutA[][]..; PTR Output6->Gate[0].MacroOutA[][]..; PTR Output7->Gate[0].MacroOutA[][]..; PTR Output8->Gate[0].MacroOutA[][].5.; PTR Output9->Gate[0].MacroOutA[][].6.; PTR Output0->Gate[0].MacroOutA[][].7.; PTR Output->Gate[0].MacroOutA[][].8.; PTR Output->Gate[0].MacroOutA[][].9.; PTR Output->Gate[0].MacroOutA[][].0.; PTR Output->Gate[0].MacroOutA[][]..; With Power PMAC, the outputs can be directly bitwise mapped, written to, and reported. Mirror word is not required. Using the ACC-65E With MACRO 5

53 Configuring the Control Word for MACRO The control word is configured automatically with MACRO6 CPU firmware version.0 and newer. The setup below is for older firmware versions. The control word can be configured with MACRO using MI98 and MI99: Set MI98 to $ {base address} + 7 Set MI99 = 7 Configuring the Control Word must be done on every power-up/reset such as in the following example PLC which performs the configuration and then disables itself. Example: With ACC-65E at base addresses $8800, and using node for MACRO Station communication. Turbo PMAC ring controllers: Open PLC Clear I5 = 50 * / I0 WHILE (I5 > 0) EndW CMD"MS,MI98=$08807" // Point to control word of Card at address $8800 CMD"MS,MI99=7" // Write to control word I5 = 50 * / I0 WHILE (I5 > 0) EndW Disable PLC Close Power PMAC ring controllers: Open PLC CALL Timer(0.50) // 50 msec delay. Requires loading the Timer subprogram. CMD"MACROSTATION,MI98=$08807" // Point to control word of Card at address $8800 CMD"MACROSTATION,MI99=7" // Write to control word CALL Timer(0.50) Disable PLC Close // Disable this PLC Using the ACC-65E With MACRO 5

54 CONNECTOR PINOUTS AND WIRING Terminal Block Connectors Top: Inputs TB / TB Top (Inputs) Pin # Function Description Input Input # / Input Input # / Input Input # / 5 Input Input # / 6 5 Input Input #5 / 7 6 Input Input #6 / 8 7 Input Input #7 / 9 8 Input Input #8 / 0 9 Input Input #9 / 0 Input Input #0 / Input Input # / Input Input # / TB Top (Inputs Reference / Return) Pin # Function / Description Inputs Return 0 08 Inputs Return 09 6 Inputs Return 7 Connector Pinouts and Wiring 5

55 Bottom: Outputs TB / TB Bottom (Outputs) Pin # Function Description Output Output # / Output Output # / Output Output # / 5 Output Output # / 6 5 Output Output #5 / 7 6 Output Output #6 / 8 7 Output Output #7 / 9 8 Output Output #8 / 0 9 Output Output #9 / 0 Output Output #0 / Output Output # / Output Output # / TB Bottom (Outputs Power) Pin # Function / Description + V +V RETURN + V Connector Pinouts and Wiring 55

56 TB Wiring Diagram Top Inputs Bottom: Outputs - VDC Power Supply + / V COM INPUT INPUT - VDC Power Supply COM + / V Output Output INPUT Output INPUT Output INPUT 5 5 Output 5 5 INPUT 6 6 Output 6 6 INPUT 7 7 Output 7 7 INPUT 8 8 Output 8 8 INPUT 9 9 Output 9 9 INPUT 0 0 Output 0 0 INPUT Output INPUT Output RET V RET V RET RET 7 - +V INPUT Output INPUT Output INPUT 5 Output 5 INPUT 6 Output 6 INPUT 7 5 Output 7 5 INPUT 8 6 Output 8 6 INPUT 9 7 Output 9 7 INPUT 0 8 Output 0 8 INPUT 9 Output 9 INPUT 0 Output 0 INPUT Output INPUT Output Connector Pinouts and Wiring 56

57 D-Sub Connectors Top: Inputs J / J Top: D-sub DA-5F Mating: D-sub DA-5M Pin # Function J J Input Input # Input # Input Input # Input #5 Input Input #5 Input #7 Input Input #7 Input #9 5 Input Input #9 Input # 6 Input Input # Input # 7 Return Inputs Return 8 8 Return Inputs Return 7 9 Input Input # Input # 0 Input Input # Input #6 Input Input #6 Input #8 Input Input #8 Input #0 Input Input #0 Input # Input Input # Input # 5 Return Inputs Return 9 6 Bottom: Outputs J / J Top: D-sub DA-5F Mating: D-sub DA-5M Pin # Function J J Output Output # Output # Output Output # Output #5 Output Output #5 Output #7 Output Output #7 Output #9 5 Output Output #9 Output # 6 Output Output # Output # 7 Input + V 8 Input + V 9 Output Output # Output # 0 Output Output # Output #6 Output Output #6 Output #8 Output Output #8 Output #0 Output Output #0 Output # Output Output # Output # 5 Return +V RETURN Connector Pinouts and Wiring 57

58 D-Sub Wiring diagram Top: Inputs Bottom: Outputs VDC Power Supply VDC Power Supply COM + / V INPUT / INPUT / INPUT / / V COM Output / Output / Output / 5 9 INPUT / 6 0 Output / 6 0 INPUT 5 / 7 Output 5 / 7 INPUT 6 / 8 INPUT 7 / 9 Output 6 / 8 Output 7 / 9 INPUT 8 / 0 INPUT 9 / 5 Output 8 / 0 Output 9 / 5 INPUT 0 / Output 0 / INPUT / 6 Output / 6 INPUT / RET 0-08 RET 09-6 RET Output / +VDC +V RET +VDC Connector Pinouts and Wiring 58

59 P: UMAC Bus (UBUS) Connector P UBUS (96-Pin Header) Pin # Row A Row B Row C +5 Vdc +5 Vdc +5 Vdc GND GND GND BD0 DAT0 BD00 BD0 SEL0 BD0 5 BD05 DAT BD0 6 BD07 SEL BD06 7 BD09 DAT BD08 8 BD SEL BD0 9 BD DAT BD 0 BD5 SEL BD BD7 DAT BD6 BD9 SEL BD8 BD DAT5 BD0 BD SEL5 BD 5 BS DAT6 BS0 6 BA0 SEL6 BA00 7 BA0 DAT7 BA0 8 BX/Y SEL7 BA0 9 CS- BA06 CS- 0 BA05 BA07 CS- CS- BA08 CS0- CS6- BA09 CS- BA BA0 BA BRD- BA BWR- 5 BS MEMCS0- BS 6 WAIT- MEMCS- RESET 7 PHASE+ IREQ- SERVO+ 8 PHASE- IREQ- SERVO- 9 ANALOG GND IREQ- ANALOG GND 0-5 Vdc PWRGND +5 Vdc GND GND GND +5 Vdc +5 Vdc +5 Vdc Connector Pinouts and Wiring 59

60 APPENDIX A: E-POINT JUMPERS Jumper Configuration Default E: to Turbo/Power/MACRO CPUs Revision 0 or newer to for Legacy MACRO CPUs Rev. 0 or older Factory Set E: to to sample at Servo Rate to to sample at Phase Rate Appendix A: E-Point Jumpers 60

61 Appendix B: Schematics 6 APPENDIX B: SCHEMATICS D9 MMBZVALTG D7 MMBZ5V6ALT D66 MMBZ5V6ALT D69 MMBZ5V6ALT C5 0.UF D6 MMBZ5V6ALT C8 0.UF C6 0.UF C7 0.UF D5 MMBZ5V6ALT D56 MMBZ5V6ALT D MMBZVALTG D50 MMBZ5V6ALT D5 MMBZVALTG RP7.K C5 0.UF C8 0.UF C6 0.UF C7 0.UF RP7.K D8 MMBZVALTG UD0 PS705-NEC ACIN ACIN E C UA0 PS705-NEC ACIN ACIN E C UC0 PS705-NEC ACIN ACIN E C UB0 PS705-NEC ACIN ACIN E C IN- UD8 PS705-NEC ACIN ACIN E C UA8 PS705-NEC ACIN ACIN E C D MMBZVALTG UB8 PS705-NEC ACIN ACIN E C UC8 PS705-NEC ACIN ACIN E C D59 MMBZ5V6ALT UD6 PS705-NEC ACIN ACIN E C UA6 PS705-NEC ACIN ACIN E C D MMBZVALTG UB6 PS705-NEC ACIN ACIN E C UC6 PS705-NEC ACIN ACIN E C IN9- IN06- RP0.K RP.K IN00- D7 MMBZVALTG IN0- RP57.K IN8- D7 MMBZVALTG RP.K I_RET_ IN05- D0 MMBZVALTG D67 MMBZ5V6ALT D70 MMBZ5V6ALT D6 MMBZ5V6ALT D6 MMBZ5V6ALT D5 MMBZ5V6ALT IN7- D5 MMBZ5V6ALT D MMBZVALTG RP.K RP5.K RP50.K IN0- D6 MMBZVALTG UD PS705-NEC ACIN ACIN E C UA PS705-NEC ACIN ACIN E C UB PS705-NEC ACIN ACIN E C IN- UC PS705-NEC ACIN ACIN E C IN- D9 MMBZVALTG D5 MMBZVALTG RP6.K RP.K I_RET_ IN0- C 0.UF C0 0.UF IN0- C 0.UF C 0.UF IN07- IN6- D MMBZVALTG D60 MMBZ5V6ALT D57 MMBZ5V6ALT IN0- D9 MMBZ5V6ALT C0 0.UF C 0.UF C 0.UF C 0.UF D5 MMBZVALTG C0 0.UF C 0.UF C 0.UF C 0.UF RP0.K D8 MMBZVALTG UD0 PS705-NEC ACIN ACIN E C UA0 PS705-NEC ACIN ACIN E C UC0 PS705-NEC ACIN ACIN E C UB0 PS705-NEC ACIN ACIN E C D8 MMBZVALTG D MMBZVALTG D68 MMBZ5V6ALT D7 MMBZ5V6ALT D65 MMBZ5V6ALT D6 MMBZ5V6ALT D55 MMBZ5V6ALT D5 MMBZ5V6ALT RP5.K D MMBZVALTG D7 MMBZVALTG D0 MMBZVALTG D MMBZVALTG RP8.K D58 MMBZ5V6ALT I_RET_ IN- IN08- IN- RP56.K RP6.K IN0- IN- IN5- IN09- IN- D6 MMBZVALTG RP58.K RP8.K UA PS705-NEC ACIN ACIN E C UD PS705-NEC ACIN ACIN E C UB PS705-NEC ACIN ACIN E C UC PS705-NEC ACIN ACIN E C D6 MMBZVALTG C6 0.UF C7 0.UF C5 0.UF C8 0.UF

62 Appendix B: Schematics 6 D96 BZX8C5V R6 0K R0 0K UA PS70-NEC ANA CAT E C UC PS70-NEC ANA CAT E C UB PS70-NEC ANA CAT E C UD PS70-NEC ANA CAT E C D9 BZX8C5V R 0K O+V D88 BZX8C5V R 0K HEAVY ETCH AT PIN R6 0K D85 BZX8C5V Opto Gnd Plane R7 0K I/O9- I/O- I/O7- I/O9- I/O0- I/O- I/O8- I/O- I/O5- I/O6- I/O5- I/O6- I/O7- I/O8- UB PS70-NEC ANA CAT E C UA PS70-NEC ANA CAT E C UC PS70-NEC ANA CAT E C UD PS70-NEC ANA CAT E C D9 BZX8C5V R8 0K R 0K I/O- R 0K R7 0K D80 BZX8C5V D77 BZX8C5V D7 BZX8C5V +5V Opto Gnd Plane D78 BZX8C5V D75 BZX8C5V D86 BZX8C5V R8 0K GND D7 BZX8C5V I/O5- I/O6- I/O7- I/O- D79 BZX8C5V D76 BZX8C5V I/O- I/O- I/O- RP RP RP UA0 PS70-NEC ANA CAT E C RP UC0 PS70-NEC ANA CAT E C UD0 PS70-NEC ANA CAT E C UB0 PS70-NEC ANA CAT E C UB PS70-NEC ANA CAT E C UA PS70-NEC ANA CAT E C D9 BZX8C5V UD PS70-NEC ANA CAT E C UC PS70-NEC ANA CAT E C I/O0- +5V I/O7- I/O6- I/O5- I/O- I/O- I/O- I/O0- I/O- GND GND R9 0K RP RP Q8 ZXMS6006DG INPUT Source Drain TAB Q7 ZXMS6006DG INPUT Source Drain TAB Q9 ZXMS6006DG INPUT Source Drain TAB Q0 ZXMS6006DG INPUT Source Drain TAB C9 0.0UF OUT7 C96 0.0UF OUT0 OUT C95 0.0UF OUT OUT C97 0.0UF C98 0.0UF R 0K C90 0.0UF OUT6 C9 0.0UF OUT8 OUT9 C9 0.0UF Q ZXMS6006DG INPUT Source Drain TAB Q ZXMS6006DG INPUT Source Drain TAB Q ZXMS6006DG INPUT Source Drain TAB Q ZXMS6006DG INPUT Source Drain TAB C6 0.UF RP6.K U 7ACT5MTC A A A A 5 A5 6 A6 7 A7 8 A8 9 G G 9 Y 8 Y 7 Y 6 Y 5 Y5 Y6 Y7 Y8 VCC 0 GND 0 Q ZXMS6006DG INPUT Source Drain TAB I/O7- I/O6- I/O5- Q ZXMS6006DG INPUT Source Drain TAB I/O- Q ZXMS6006DG INPUT Source Drain TAB Q ZXMS6006DG INPUT Source Drain TAB C7 0.0UF OUT0 C76 0.0UF OUT0 OUT05 C75 0.0UF R 0K C78 0.0UF OUT06 OUT07 C77 0.0UF C70 0.0UF OUT00 OUT0 OUT0 C7 0.0UF C7 0.0UF Q5 ZXMS6006DG INPUT Source Drain TAB Q7 ZXMS6006DG INPUT Source Drain TAB Q6 ZXMS6006DG INPUT Source Drain TAB Q8 ZXMS6006DG INPUT Source Drain TAB R8 0K UA6 PS70-NEC ANA CAT E C UC6 PS70-NEC ANA CAT E C UB6 PS70-NEC ANA CAT E C UD6 PS70-NEC ANA CAT E C UB8 PS70-NEC ANA CAT E C UA8 PS70-NEC ANA CAT E C UC8 PS70-NEC ANA CAT E C UD8 PS70-NEC ANA CAT E C I/O- D87 BZX8C5V D8 BZX8C5V +5V D8 BZX8C5V R9 0K D9 BZX8C5V GND D8 BZX8C5V D8 BZX8C5V Q0 ZXMS6006DG INPUT Source Drain TAB Q9 ZXMS6006DG INPUT Source Drain TAB Q ZXMS6006DG INPUT Source Drain TAB Q ZXMS6006DG INPUT Source Drain TAB OUT09 C8 0.0UF C86 0.0UF R7 0K OUT OUT C85 0.0UF C88 0.0UF OUT OUT5 C87 0.0UF C80 0.0UF OUT08 C8 0.0UF OUT0 OUT C8 0.0UF Q ZXMS6006DG INPUT Source Drain TAB Q5 ZXMS6006DG INPUT Source Drain TAB Q ZXMS6006DG INPUT Source Drain TAB Q6 ZXMS6006DG INPUT Source Drain TAB D89 BZX8C5V C5 0.UF RP5.K U7 7ACT5MTC A A A A 5 A5 6 A6 7 A7 8 A8 9 G G 9 Y 8 Y 7 Y 6 Y 5 Y5 Y6 Y7 Y8 VCC 0 GND 0 C 0.UF I/O8- I/O7- I/O6- I/O- I/O- I/O9- R0 0K I/O5- I/O- R 0K PLANE I/O9- I/O8- I/O- I/O0- R5 0K R9 0K D95 BZX8C5V RP.K R0 0K O+V_5v BIAS D90 BZX8C5V U 7ACT5MTC A A A A 5 A5 6 A6 7 A7 8 A8 9 G G 9 Y 8 Y 7 Y 6 Y 5 Y5 Y6 Y7 Y8 VCC 0 GND 0 R 0K R5 0K

63 APPENDIX C: USING THE ACC-65E IN C This section shows how the ACC-65E can be programmed and used via the C programming language in Power PMAC. ACC-65E C Library Include the following header file (acc65e.h) into the Project: #include <gplib.h> #include <RtGpShm.h> // Global Rt/Gp Shared memory pointers // // The following is a projpp created file from the User defines // #include "../../Include/pp_proj.h" #define ON // Assumes that (logic high)=true #define OFF 0 // Assumes that (logic low)=false void ACC65E_SetControlWord(unsigned int CardNumber); unsigned int ACC65E_GetInputState(unsigned int CardNumber, unsigned int InputNumber); unsigned int ACC65E_GetOutputState(unsigned int CardNumber, unsigned int OutputNumber); void ACC65E_SetOutputState(unsigned int CardNumber, unsigned int OutputNumber, unsigned int State); Then put the following source code file (acc65e.c) into the same folder as the header above: #include <gplib.h> #include <RtGpShm.h> // Global Rt/Gp Shared memory pointers // // The following is a projpp created file from the User defines // #include "../../Include/pp_proj.h" #include "acc65e.h" void ACC65E_SetControlWord(unsigned int CardNumber) { // CardNumber: Power PMAC I/O Card Index of this card (0-5) volatile unsigned int *ioptr; ioptr = piom + pshm->offsetcardio[cardnumber]/ + 7; *ioptr = 7 << 8; // Shift 7 up 8 and write the value return; } unsigned int ACC65E_GetInputState(unsigned int CardNumber, unsigned int InputNumber) { // CardNumber: Power PMAC I/O Card Index of this card (0-5) // InputNumber: Input Pin Number (-) volatile unsigned int *ioptr; InputNumber--; ioptr = piom + pshm->offsetcardio[cardnumber]/; ioptr += InputNumber/8; // Shift all bits above the desired bit out // Then shift down to bit 0 and return return (unsigned int)((*ioptr << ( - (InputNumber%8 + 8))) >> ); } unsigned int ACC65E_GetOutputState(unsigned int CardNumber, unsigned int OutputNumber) { // CardNumber: Power PMAC I/O Card Index of this card (0-5) // OutputNumber: Input Pin Number (-) volatile unsigned int *ioptr; OutputNumber--; ioptr = piom + pshm->offsetcardio[cardnumber]/; Appendix C: Using The ACC-65E in C 6

64 ioptr += OutputNumber/8 + ; // Shift all bits above the desired bit out // Then shift down to bit 0 and return return (unsigned int)((*ioptr << ( - (OutputNumber%8 + 8))) >> ); } void ACC65E_SetOutputState(unsigned int CardNumber, unsigned int OutputNumber, unsigned int State) { // CardNumber: Power PMAC I/O Card Index of this card (0-5) // OutputNumber: Input Pin Number (-) // State: =ON, 0=OFF volatile unsigned int *ioptr; unsigned int HighBitInCorrectLocation; OutputNumber--; HighBitInCorrectLocation = << ((OutputNumber % 8) + 8); ioptr = piom + pshm->offsetcardio[cardnumber]/; ioptr += OutputNumber/8 + ; if(state == ) // If the user wants the pin to be ON (high true) // Logical OR with the bit the user desires to activate *ioptr = HighBitInCorrectLocation; else // Logical AND the register with a 0 in the desired location to bring the pin's state low // right shift to push out garbage in lowest 8 bits, then shift back up 8 bits to have // data in the proper location *ioptr &= (((~0)^HighBitInCorrectLocation) >> 8) << 8; return; } Locations for the C Files Background C Programs To use the above ACC-65E code in a Background C Program, make a new folder called acc65e in the C Language Libraries folder under the Solution Explorer in the Power PMAC IDE. Then, put the code into this folder and make sure that the Build Action for acc65e.c under Properties is set to Compile. The Solution Explorer should then look something like the screenshot to the right. Then, in the Background Program, include the header file with the following preprocessor directive: #include "../../Libraries/acc65e/acc65e.h" Appendix C: Using The ACC-65E in C 6

65 Background CPLCs (BGCPLCs) and Real-Time CPLCs (RTICPLCs) To use the above code in a Background CPLC (BGCPLC), put acc65e.h and acc65e.c into the same folder as the BGCPLC. For example, when using BGCPLC00, Solution Explorer might look like the following: Then, include the header file with the following preprocessor directive: #include "acc65e.h" The same is true for RTICPLCs: Appendix C: Using The ACC-65E in C 65