STEVEN R. BAGLEY ARM: LOOPS AND ADDRESSING
|
|
- Liliana Dixon
- 5 years ago
- Views:
Transcription
1 STEVEN R. BAGLEY ARM: LOOPS AND ADDRESSING
2 FROM C TO ASSEMBLER Plan your assembler programs in C first Much easier to get the logic right in C using ifs, whiles etc. Can then convert those high-level structures into machine code Already seen how to convert if statements At least to start with Difference between the logic behind a program and the syntax of the language
3 IF IN ASSEMBLER Do a CMP to test for the condition Branch if the condition is not met to skip over the code inside the if block Code is then executed only if the condition is met Otherwise we skip over it
4 if EXAMPLES C ASSEMBLER
5 if EXAMPLES if(r0 == 10) { C ASSEMBLER CMP R0, #10 BNE skip skip
6 if EXAMPLES if(r0 == 10) { if(r0 < R1) { C ASSEMBLER CMP R0, #10 BNE skip skip CMP R0, R1 BGE skip skip
7 if EXAMPLES if(r0 == 10) { if(r0 < R1) { if(r0 >= 10) { C ASSEMBLER CMP R0, #10 BNE skip skip CMP R0, R1 BGE skip skip CMP R0, #10 BLT skip skip
8 if EXAMPLES if(r0 == 10) { if(r0 < R1) { if(r0 >= 10) { if(r0!= 0) { C ASSEMBLER CMP R0, #10 BNE skip skip CMP R0, R1 BGE skip skip CMP R0, #10 BLT skip skip CMP R0, #10 BEQ skip skip
9 B main menu coke DEFB G51SYS Vending Machine \n\0 DEFB Have a bottle of Coke\n\0 ALIGN main SWI 1 ; Read a character CMP R0, #49 BNE skip ADR R0, coke SWI 3 skip SWI 2 Beginning of the Coke vending machine from G51PRG label name for skip unimportant but it needs to be unique
10 B main menu coke DEFB G51SYS Vending Machine \n\0 DEFB Have a bottle of Coke\n\0 ALIGN main SWI 1 ; Read a character CMP R0, #49 BNE skip ADR R0, coke SWI 3 skip SWI 2 Beginning of the Coke vending machine from G51PRG label name for skip unimportant but it needs to be unique
11 B main menu coke DEFB G51SYS Vending Machine \n\0 DEFB Have a bottle of Coke\n\0 ALIGN main SWI 1 ; Read a character CMP R0, #49 BNE skip ADR R0, coke SWI 3 skip SWI 2 Beginning of the Coke vending machine from G51PRG label name for skip unimportant but it needs to be unique
12 OR ELSE How do we handle the else clause? Already doing it If it s not true we are branching to skip Can put the else section there But the code that is executed when the condition is true will also get executed
13 OR ELSE But we can easily get around that Put a branch at the end of the true block to skip the else section This would be an unconditional branch
14 B main menu coke error DEFB G51SYS Vending Machine \n\0 DEFB Have a bottle of Coke\n\0 DEFB Incorrect option\n\0 ALIGN main SWI 1 ; Read a character CMP R0, #49 BNE skip ADR R0, coke SWI 3 B end skip ADR R0, error SWI 3 end SWI 2
15 B main menu coke error DEFB G51SYS Vending Machine \n\0 DEFB Have a bottle of Coke\n\0 DEFB Incorrect option\n\0 ALIGN main SWI 1 ; Read a character CMP R0, #49 BNE skip ADR R0, coke SWI 3 B end skip ADR R0, error SWI 3 end SWI 2
16 B main menu coke error DEFB G51SYS Vending Machine \n\0 DEFB Have a bottle of Coke\n\0 DEFB Incorrect option\n\0 ALIGN main SWI 1 ; Read a character CMP R0, #49 BNE skip ADR R0, coke SWI 3 B end skip ADR R0, error SWI 3 end SWI 2
17 COMBINED CONDITIONALS Should be possible to see how we can do combined conditionals too Just use multiple CMP/Bxx pairs Can also do lazy evaluation as with C But need to watch our branch conditions
18 AND CONDITIONALS if(r0 == 1 && R1 == 2) { printf("have \n ); CMP R0, #1 BNE skip CMP R1, #2 BNE skip ADR R0, mesg SWI 3 skip SWI 2 Could optimise this a lot though Highlighted code is only executed when r0 == 1 and r1 == 2 Note how both branches use the same condition code If it s ever false skip it
19 AND CONDITIONALS if(r0 == 1 && R1 == 2) { printf("have \n ); CMP R0, #1 BNE skip CMP R1, #2 BNE skip ADR R0, mesg SWI 3 skip SWI 2 Could optimise this a lot though Highlighted code is only executed when r0 == 1 and r1 == 2 Note how both branches use the same condition code If it s ever false skip it
20 AND CONDITIONALS if(r0 == 1 && R1 == 2) { printf("have \n ); CMP R0, #1 BNE skip CMP R1, #2 BNE skip ADR R0, mesg SWI 3 skip SWI 2 Could optimise this a lot though Highlighted code is only executed when r0 == 1 and r1 == 2 Note how both branches use the same condition code If it s ever false skip it
21 AND CONDITIONALS if(r0 == 1 && R1 == 2) { printf("have \n ); CMP R0, #1 BNE skip CMP R1, #2 BNE skip ADR R0, mesg SWI 3 skip SWI 2 Could optimise this a lot though Highlighted code is only executed when r0 == 1 and r1 == 2 Note how both branches use the same condition code If it s ever false skip it
22 OR COMBINATION if(r0 == 1 R1 == 2) { printf("have \n ); CMP R0, #1 BEQ code CMP R1, #2 BNE skip code ADR R0, mesg SWI 3 skip SWI 2 Could optimise this a lot though Highlighted code is only executed when r0 == 1 or r1 == 2 Note how the first branch branches if equal, the second if not equal Again it s lazy evaluation if the first test is true, then we don t need to do the second test so can just jump into the code
23 OR COMBINATION if(r0 == 1 R1 == 2) { printf("have \n ); CMP R0, #1 BEQ code CMP R1, #2 BNE skip code ADR R0, mesg SWI 3 skip SWI 2 Could optimise this a lot though Highlighted code is only executed when r0 == 1 or r1 == 2 Note how the first branch branches if equal, the second if not equal Again it s lazy evaluation if the first test is true, then we don t need to do the second test so can just jump into the code
24 OR COMBINATION if(r0 == 1 R1 == 2) { printf("have \n ); CMP R0, #1 BEQ code CMP R1, #2 BNE skip code ADR R0, mesg SWI 3 skip SWI 2 Could optimise this a lot though Highlighted code is only executed when r0 == 1 or r1 == 2 Note how the first branch branches if equal, the second if not equal Again it s lazy evaluation if the first test is true, then we don t need to do the second test so can just jump into the code
25 OR COMBINATION if(r0 == 1 R1 == 2) { printf("have \n ); CMP R0, #1 BEQ code CMP R1, #2 BNE skip code ADR R0, mesg SWI 3 skip SWI 2 Could optimise this a lot though Highlighted code is only executed when r0 == 1 or r1 == 2 Note how the first branch branches if equal, the second if not equal Again it s lazy evaluation if the first test is true, then we don t need to do the second test so can just jump into the code
26 LOOPS Important building blocks in programs while loops repeat a block of code whilst the condition holds But again, like if, ARM assembler does not provide a while loop Need to manufacture it out of simple components In ARM this is the B instruction In C, there is an equivalent in the goto instruction
27 LOOPS USING GOTO We can translate our while loop to using gotos Bad programming practice normally But a good halfway stage between structured programming and assembler Remember though that a while loop can execute zero or more times Run through an example in C Show that they both run and produce the same result.
28 while LOOP while(i < 8) { j = j + 3; i = i + 1; Note how we ve turned the structure of the while loop upside down We ve put the test at the end There s reasons for this madness Can then convert this very easily into machine code ASM version assumes i is in R1 and j is in R0
29 while LOOP while(i < 8) { j = j + 3; i = i + 1; goto while_cond; while_loop: j = j + 3; i = i + 1; while_cond: if(i < 8) goto while_loop; Note how we ve turned the structure of the while loop upside down We ve put the test at the end There s reasons for this madness Can then convert this very easily into machine code ASM version assumes i is in R1 and j is in R0
30 while LOOP goto while_cond; while_loop: j = j + 3; i = i + 1; while_cond: if(i < 8) goto while_loop; B while_cond while_loop ADD R0, R0, #3 ADD R1, R1, #1 while_cond CMP R1, #8 BLT while_loop Note how we ve turned the structure of the while loop upside down We ve put the test at the end There s reasons for this madness Can then convert this very easily into machine code ASM version assumes i is in R1 and j is in R0
31 WHILE LOOP Putting the conditional at the end has several advantages Don t have to invert the conditional (as we did with if) Will actually execute less instructions Code for a do while() loop is near identical
32 WHILE LOOP B while_cond while_loop ADD R0, R0, #3 ADD R1, R1, #1 while_cond CMP R1, #8 BLT while_loop while_cond CMP R1, #8 BGE end ADD R0, R0, #3 ADD R1, R1, #1 B while_cond end: ASM version assumes i is in R1 and j is in R0 Uses 4 instructions per loop iteration + 3 to start it off (35) second method takes 5 instructions per loop +2 extra (42) Take a look and see what the compiler does too
33 WORKED EXAMPLE Going to work through an example bit of code now To calculate the Highest Common Factor (HCF) Use Euclid s algorithm
34 EUCLID S HCF ALGORITHM Euclid was a famous Greek mathematician (~300BC) Devised a simple algorithm for finding the Highest Common Factor of two integers while(a!= b) { if(a > b) a = a - b; else b = b - a; Let s convert this into assembler
35 LOOPS Firstly, we need to remove the while loop Don t have such luxuries in assembly Only have branches, the equivalent of C s goto Rewrite our C program to use ifs and goto instead Eek GOTO alert Go and do this, show the program works
36 REGISTERS Now we can start assigning the variables to registers Small number here, so we ll use R0 to be equivalent to a, and R1 to be equivalent to b Actual registers used doesn t matter (more or less) If you run out, you can always store the value in memory and the load it back into a register later Okay now start developing an ARM version alongside the C version split screen then test in Komodo
37 FOR LOOPS Again, we can model a for loop in assembler Already seen how to do this in G51PGA Saw that there is an equivalent while loop for every for loop So when we want to use a for loop we can convert it to a while loop Then convert the while loop to assembler as before
38 for(expr1; expr2; expr3) statement; expr1; while(expr2) { statement; expr3;
39 for(expr1; expr2; expr3) statement; expr1; while(expr2) { statement; expr3; These are equivalent
40 for LOOP for(i = 0; i < 10; i++) { printf( %d\n, i); Note how we ve turned the structure of the while loop upside down We ve put the test at the end There s reasons for this madness Can then convert this very easily into machine code ASM version assumes i is in R1 and j is in R0
41 for LOOP for(i = 0; i < 10; i++) { printf( %d\n, i); i = 0; while(i < 10) { printf( %d\n, i); i++; Note how we ve turned the structure of the while loop upside down We ve put the test at the end There s reasons for this madness Can then convert this very easily into machine code ASM version assumes i is in R1 and j is in R0
42 for LOOP i = 0; while(i < 10) { printf( %d\n, i); i++; Note how we ve turned the structure of the while loop upside down We ve put the test at the end There s reasons for this madness Can then convert this very easily into machine code ASM version assumes i is in R1 and j is in R0
43 for LOOP i = 0; while(i < 10) { printf( %d\n, i); i++; i = 0; goto while_cond; while_loop: printf( %d\n, i); i++; while_cond: if(i < 10) goto while_loop; Note how we ve turned the structure of the while loop upside down We ve put the test at the end There s reasons for this madness Can then convert this very easily into machine code ASM version assumes i is in R1 and j is in R0
44 ADDRESSING Already seen how we can load and store values from memory LDR R0, _a STR R1, _b But this can only load from a fixed address, and the same address every time Okay for global variables, wouldn t work for an array This is known as Absolute Addressing Or at least it would be on most systems
45 ADDRESSING ON ARM Like most CPUs, ARM provides support for various addressing modes for accessing memory At their heart, they are all just mechanisms for automatically calculating the address to be accessed But provide very convenient mechanisms to handle the calculation Unlike most other CPUs, ARM doesn t actually have an Absolute Addressing mode
46 HANDLING LARGE ADDRESSES ARM encodes all instructions in one 32-bit word This encodes the instruction and also what it operates on (registers, immediate values, etc) Different to a CISC chip which will use multiple words to encode the data Much faster to hide numeric constants and data addresses in the instruction themselves
47 ADDRESSING ON ARM But the addresses are 32-bits wide How does ARM hide them inside the the 32-bit instruction when there are only 8- or 12-bits spare? Uses a scheme that generates a useful subset of all the 32-bit values Already seen this with immediate values in MOV instructions amongst others
48 IMMEDIATE VALUE Encoded as an 8-bit value (0-255), and a 4-bit rotation value Rotation shifts the bits around the 32-bits of the register If value cannot be expressed using the above, we can always just load it from memory
49 PSEUDO-INSTRUCTION Assembler recognises a pseudo-instruction which will automatically select whether to use a MOV or to load from memory LDR R1, =0x Gets compiled to either a MOV instruction (if it will fit), or loads it from memory using LDR Assembler designates part of the program a literal pool to store the constants Literal pool must be within ±4KB of the PC But assembler handles it (go demo) Pseudo-instruction because it doesn t exist assembler generates a real instruction based on the program s context
50 USING THE PC TO HELP Rotation isn t the only useful trick in generating a large constant (often intended as an address) Time to think about ADR in more detail Again, ADR is not an ARM instruction, but an assembler pseudo-instruction Assumes that the address to be loaded into a register is near the PC Look at ADR, then see how a similar trick is used by LDR/STR
51 ADR INSTRUCTION If address is in range, then destination register can be set using a singleinstruction by adding/subtracting an offset to the value in PC Offset must be expressible in 8-bits with rotation So ADR R0,one might become SUB R0, PC, #&18 or ADD R0, PC, #&80 Depends on the relationship between the label and the instruction s location
52 ADRL Not all address can be generated by this approach The offset must be expressible as a rotation of 8-bits Also have an ADRL pseudo-instruction This will use two (or more) instructions to generate the address Again usually ADD or SUB instructions Given an example use origin to demo it
53 ADRL IN AASM With aasm, ADRL will only generate a single instruction if possible Otherwise it may need two or more instructions Other assemblers may always generate two instructions The combination of PC-relative addressing with rotated constants is very powerful Can be important when writing code to know exactly how many instructions are executed
54 ORIGIN 0x0100 alpha DEFW 20 ORIGIN 0x1000 beta DEFW 30 ORIGIN 0x1010 ENTRY ADRL R0, alpha ADRL R0, beta ADRL R0, gamma E24F0FC6 SUB R0 PC, #& E2400B03 SUB R0, R0, #&C E24F0020 SUB R0, PC, #& C E28F0EED ADD R0, PC, #&ED E2800A02 ADD R0, R0, #&2000 ORIGIN 0x3EF4 gamma DEFW 40 Various examples of ADRL in action in aasm
55 POSITION INDEPENDENCE One other advantage of writing code like this is it is position-independent That is, providing all the access to addresses are relative to the PC then it doesn t matter where it is loaded in memory As soon as you hard-code an address (e.g. in a variable, or literal pool) then this breaks Doesn t mean the code cannot be loaded anywhere but the thing loading it will need to relocate it to the new memory address
Control Flow and Loops. Steven R. Bagley
Control Flow and Loops Steven R. Bagley Introduction Started to look at writing ARM Assembly Language Saw the structure of various commands Load (LDR), Store (STR) for accessing memory SWIs for OS access
More informationWriting ARM Assembly. Steven R. Bagley
Writing ARM Assembly Steven R. Bagley Introduction Previously, looked at how the system is built out of simple logic gates Last week, started to look at the CPU Writing code in ARM assembly language Assembly
More informationSTEVEN R. BAGLEY ARM: PROCESSING DATA
STEVEN R. BAGLEY ARM: PROCESSING DATA INTRODUCTION CPU gets instructions from the computer s memory Each instruction is encoded as a binary pattern (an opcode) Assembly language developed as a human readable
More informationWriting ARM Assembly. Steven R. Bagley
Writing ARM Assembly Steven R. Bagley Hello World B main hello DEFB Hello World\n\0 goodbye DEFB Goodbye Universe\n\0 ALIGN main ADR R0, hello ; put address of hello string in R0 SWI 3 ; print it out ADR
More informationPhoto David Wright STEVEN R. BAGLEY PIPELINES AND ILP
Photo David Wright https://www.flickr.com/photos/dhwright/3312563248 STEVEN R. BAGLEY PIPELINES AND ILP INTRODUCTION Been considering what makes the CPU run at a particular speed Spent the last two weeks
More informationWhat are the differences between these three ARM instructions: (3 marks) ADD R1, R2, R3 ADDS R1, R2, R3 and ADDEQ R1, R2, R3
OMP15111 Lecture 7 1/41 From last time What are the differences between these three ARM instructions: (3 marks) ADD R1, R2, R3 ADDS R1, R2, R3 and ADDEQ R1, R2, R3 Explain how using S (as for ADDS above)
More informationTopic Notes: MIPS Instruction Set Architecture
Computer Science 220 Assembly Language & Comp. Architecture Siena College Fall 2011 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture.
More informationControl Flow Instructions
Control Flow Instructions CSE 30: Computer Organization and Systems Programming Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1 So Far... v All instructions have
More informationChapter 04: Instruction Sets and the Processor organizations. Lesson 08: Processor Instructions - Part 1
Chapter 04: Instruction Sets and the Processor organizations Lesson 08: Processor Instructions - Part 1 1 Objective Understand the load, store instructions and register transfer instructions Understand
More informationARM Assembly Language. Programming
Outline: ARM Assembly Language the ARM instruction set writing simple programs examples Programming hands-on: writing simple ARM assembly programs 2005 PEVE IT Unit ARM System Design ARM assembly language
More informationControl Structures. Code can be purely arithmetic assignments. At some point we will need some kind of control or decision making process to occur
Control Structures Code can be purely arithmetic assignments At some point we will need some kind of control or decision making process to occur C uses the if keyword as part of it s control structure
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:
More informationCprE 288 Introduction to Embedded Systems ARM Assembly Programming: Translating C Control Statements and Function Calls
CprE 288 Introduction to Embedded Systems ARM Assembly Programming: Translating C Control Statements and Function Calls Instructors: Dr. Phillip Jones 1 Announcements Final Projects Projects: Mandatory
More informationIntel x86 Jump Instructions. Part 5. JMP address. Operations: Program Flow Control. Operations: Program Flow Control.
Part 5 Intel x86 Jump Instructions Control Logic Fly over code Operations: Program Flow Control Operations: Program Flow Control Unlike high-level languages, processors don't have fancy expressions or
More informationIntel x86 Jump Instructions. Part 5. JMP address. Operations: Program Flow Control. Operations: Program Flow Control.
Part 5 Intel x86 Jump Instructions Control Logic Fly over code Operations: Program Flow Control Operations: Program Flow Control Unlike high-level languages, processors don't have fancy expressions or
More informationARM Cortex-M4 Programming Model Flow Control Instructions
ARM Cortex-M4 Programming Model Flow Control Instructions Textbook: Chapter 4, Section 4.9 (CMP, TEQ,TST) Chapter 6 ARM Cortex-M Users Manual, Chapter 3 1 CPU instruction types Data movement operations
More informationC Course. IIT Kanpur. Lecture 3 Aug 31, Rishi Kumar <rishik>, Final year BT-MT, CSE
C Course IIT Kanpur Lecture 3 Aug 31, 2008 Rishi Kumar , Final year BT-MT, CSE 1 Recap Signed and Unsigned data types in C Let s consider signed and unsigned int in C. C allocates 2 bytes(can vary
More informationQuick Review. lw $t0, 4($a0) Registers x Memory. $a0 is simply another name for register 4 $t0 is another name for register (green sheet)
CSE378 Lecture 3 Today: Finish up memory Control-flow (branches) in MIPS if/then loops case/switch (maybe) Start: Array Indexing vs. Pointers In particular pointer arithmetic String representation 1 Quick
More informationAssembly Language Programming
Assembly Language Programming ECE 362 https://engineering.purdue.edu/ee362/ Rick Reading and writing arrays Consider this C code again: int array1[100]; int array2[100]; for(n=0; n
More informationAssembler: Basics. Alberto Bosio October 20, Univeristé de Montpellier
Assembler: Basics Alberto Bosio bosio@lirmm.fr Univeristé de Montpellier October 20, 2017 Assembler Program Template. t e x t / S t a r t o f the program code s e c t i o n /.data / V a r i a b l e s /
More informationComputer Architecture
Computer Architecture Chapter 2 Instructions: Language of the Computer Fall 2005 Department of Computer Science Kent State University Assembly Language Encodes machine instructions using symbols and numbers
More informationChapter 3. Instructions:
Chapter 3 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive e.g., MIPS Arithmetic Instructions We ll be working with
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:
More informationInstructions: Language of the Computer
CS359: Computer Architecture Instructions: Language of the Computer Yanyan Shen Department of Computer Science and Engineering 1 The Language a Computer Understands Word a computer understands: instruction
More informationSupport for high-level languages
Outline: Support for high-level languages memory organization ARM data types conditional statements & loop structures the ARM Procedure Call Standard hands-on: writing & debugging C programs 2005 PEVE
More informationMIPS Memory Access Instructions
MIPS Memory Access Instructions MIPS has two basic data transfer instructions for accessing memory lw $t0, 4($s3) #load word from memory sw $t0, 8($s3) #store word to memory The data is loaded into (lw)
More informationUniversity of California, San Diego CSE 30 Computer Organization and Systems Programming Winter 2014 Midterm Dr. Diba Mirza
Name Student ID University of California, San Diego CSE 30 Computer Organization and Systems Programming Winter 2014 Midterm Dr. Diba Mirza Name of person to your left Name of person to your right Please
More informationMay Saeid Nooshabadi. Overview ELEC2041. Compiler Assembler Linker Loader Example. Microprocessors and Interfacing
Overview ELEC2041 lec24-linker-i.1 ELEC2041 Microprocessors and Interfacing Lectures 24,, Linker and Loader I http//webct.edtec.unsw.edu.au/ May 2006 saeid@unsw.edu.au Linker Loader Example ELEC2041 lec24-linker-i.2
More informationCS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats
CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats Instructors: Vladimir Stojanovic and Nicholas Weaver http://inst.eecs.berkeley.edu/~cs61c/sp16 1 Machine Interpretation Levels of Representation/Interpretation
More informationEE 3170 Microcontroller Applications
Lecture Overview EE 3170 Microcontroller Applications Lecture 7 : Instruction Subset & Machine Language: Conditions & Branches in Motorola 68HC11 - Miller 2.2 & 2.3 & 2.4 Based on slides for ECE3170 by
More informationProcessor Status Register(PSR)
ARM Registers Register internal CPU hardware device that stores binary data; can be accessed much more rapidly than a location in RAM ARM has 13 general-purpose registers R0-R12 1 Stack Pointer (SP) R13
More informationCS1102: Macros and Recursion
CS1102: Macros and Recursion Kathi Fisler, WPI October 5, 2009 This lecture looks at several more macro examples. It aims to show you when you can use recursion safely with macros and when you can t. 1
More informationContents. Slide Set 1. About these slides. Outline of Slide Set 1. Typographical conventions: Italics. Typographical conventions. About these slides
Slide Set 1 for ENCM 369 Winter 2014 Lecture Section 01 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Winter Term, 2014 ENCM 369 W14 Section
More informationCompilers and Interpreters
Compilers and Interpreters Pointers, the addresses we can see Programs that write other programs Managing the details A compiler is a program that, when fed itself as input, produces ITSELF! Then how was
More informationSeptember, Saeid Nooshabadi. Overview COMP Compiler Assembler Linker Loader Example
Overview COMP3221 lec24-linker-i.1 COMP 3221 Microprocessors and Embedded Systems Lectures 24,, Linker and Loader I http//www.cse.unsw.edu.au/~cs3221 September, 2003 saeid@unsw.edu.au Linker Loader Example
More informationLab 3 (All Sections) Prelab: MIPS-Control Instructions
Lab 3 (All Sections) Prelab: MIPS-Control Instructions Name: Sign the following statement: On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic work 1 Objective
More informationTopic 10: Instruction Representation
Topic 10: Instruction Representation CSE 30: Computer Organization and Systems Programming Summer Session II Dr. Ali Irturk Dept. of Computer Science and Engineering University of California, San Diego
More informationChapter 2. Instructions:
Chapter 2 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive e.g., MIPS Arithmetic Instructions We ll be working with
More information1 5. Addressing Modes COMP2611 Fall 2015 Instruction: Language of the Computer
1 5. Addressing Modes MIPS Addressing Modes 2 Addressing takes care of where to find data instruction We have seen, so far three addressing modes of MIPS (to find data): 1. Immediate addressing: provides
More informationELEC / Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2)
ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2) Victor P. Nelson, Professor & Asst. Chair Vishwani D. Agrawal, James J. Danaher Professor Department
More informationUnsigned and signed integer numbers
Unsigned and signed integer numbers Binary Unsigned Signed 0000 0 0 0001 1 1 0010 2 2 0011 3 3 0100 4 4 Subtraction sets C flag opposite of carry (ARM specialty)! - if (carry = 0) then C=1 - if (carry
More informationSTEVEN R. BAGLEY THE ASSEMBLER
STEVEN R. BAGLEY THE ASSEMBLER INTRODUCTION Looking at how to build a computer from scratch Started with the NAND gate and worked up Until we can build a CPU Reached the divide between hardware and software
More informationECE 571 Advanced Microprocessor-Based Design Lecture 7
ECE 571 Advanced Microprocessor-Based Design Lecture 7 Vince Weaver http://www.eece.maine.edu/~vweaver vincent.weaver@maine.edu 9 February 2016 HW2 Grades Ready Announcements HW3 Posted be careful when
More informationThomas Polzer Institut für Technische Informatik
Thomas Polzer tpolzer@ecs.tuwien.ac.at Institut für Technische Informatik Branch to a labeled instruction if a condition is true Otherwise, continue sequentially beq rs, rt, L1 if (rs == rt) branch to
More informationThe Assembly Language of the Boz 5
The Assembly Language of the Boz 5 The Boz 5 uses bits 31 27 of the IR as a five bit opcode. Of the possible 32 opcodes, only 26 are implemented. Op-Code Mnemonic Description 00000 HLT Halt the Computer
More informationLab 3 (Sections 300, 301 and 302) Prelab: MIPS-Control Instructions
Lab 3 (Sections 300, 301 and 302) Prelab: MIPS-Control Instructions Name: Sign the following statement: On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic work
More informationInstructions: Assembly Language
Chapter 2 Instructions: Assembly Language Reading: The corresponding chapter in the 2nd edition is Chapter 3, in the 3rd edition it is Chapter 2 and Appendix A and in the 4th edition it is Chapter 2 and
More informationCISC-124. Casting. // this would fail because we can t assign a double value to an int // variable
CISC-124 20180122 Today we looked at casting, conditionals and loops. Casting Casting is a simple method for converting one type of number to another, when the original type cannot be simply assigned to
More informationControl Structures. Lecture 4 COP 3014 Fall September 18, 2017
Control Structures Lecture 4 COP 3014 Fall 2017 September 18, 2017 Control Flow Control flow refers to the specification of the order in which the individual statements, instructions or function calls
More informationARM Assembler Workbook. CS160 Computer Organization Version 1.1 October 27 th, 2002 Revised Fall 2005
ARM Assembler Workbook CS160 Computer Organization Version 1.1 October 27 th, 2002 Revised Fall 2005 ARM University Program Version 1.0 January 14th, 1997 Introduction Aim This workbook provides the student
More informationARM Assembly Programming
Introduction ARM Assembly Programming The ARM processor is very easy to program at the assembly level. (It is a RISC) We will learn ARM assembly programming at the user level and run it on a GBA emulator.
More informationPrinciples of Computer Science
Principles of Computer Science Lecture 2 Dr. Horia V. Corcalciuc Horia Hulubei National Institute for R&D in Physics and Nuclear Engineering (IFIN-HH) January 27, 2016 Loops: do-while do-while loops do
More informationTransfer of Control. Lecture 10 JMP. JMP Formats. Jump Loop Homework 3 Outputting prompts Reading single characters
Lecture 10 Jump Loop Homework 3 Outputting prompts Reading single characters Transfer of Control The CPU loads and executes programs sequentially. You d like to be able to implement if statements, gotos,
More informationComputer Systems Architecture
Computer Systems Architecture http://cs.nott.ac.uk/ txa/g51csa/ Thorsten Altenkirch and Liyang Hu School of Computer Science and IT University of Nottingham Lecture 05: Comparisons, Loops and Bitwise Operations
More informationOutline. ARM Introduction & Instruction Set Architecture. ARM History. ARM s visible registers
Outline ARM Introduction & Instruction Set Architecture Aleksandar Milenkovic E-mail: Web: milenka@ece.uah.edu http://www.ece.uah.edu/~milenka ARM Architecture ARM Organization and Implementation ARM Instruction
More informationARM Shift Operations. Shift Type 00 - logical left 01 - logical right 10 - arithmetic right 11 - rotate right. Shift Amount 0-31 bits
ARM Shift Operations A novel feature of ARM is that all data-processing instructions can include an optional shift, whereas most other architectures have separate shift instructions. This is actually very
More informationLecture 9: Disassembly
Lecture 9: Disassembly CSE 30: Computer Organization and Systems Programming Winter 2010 Rajesh Gupta / Ryan Kastner Dept. of Computer Science and Engineering University of California, San Diego Instruction
More informationsarm User Guide Note that a space must appear before the operation field because any word beginning in the first column is a label
sarm User Guide The sarm is program that implements an experimental CPU simulator. It is called experimental because it is not yet complete, and it also incorporates facilities that are not conventionally
More informationComputer Science 61C Spring Friedland and Weaver. Instruction Encoding
Instruction Encoding 1 Instruction Formats I-format: used for instructions with immediates, lw and sw (since offset counts as an immediate), and branches (beq and bne) since branches are "relative" to
More informationCMPSCI 201 Fall 2005 Midterm #2 Solution
CMPSCI 201 Fall 2005 Midterm #2 Solution Professor William T. Verts 10 Points Convert the decimal number -47.375 into (a) binary scientific notation (i.e., ±1.xxxx 2 Y ), and (b) the equivalent binary
More informationARM Assembly Programming
ARM Assembly Programming Computer Organization and Assembly Languages g Yung-Yu Chuang with slides by Peng-Sheng Chen GNU compiler and binutils HAM uses GNU compiler and binutils gcc: GNU C compiler as:
More informationCMPSCI 201 Fall 2004 Midterm #1 Answers
CMPSCI 201 Fall 2004 Midterm #1 Answers 10 Points Short Essay Answer The 8088 is primarily a CISC processor design, and the ARM is primarily RISC. The 6502 is such an early design that it is difficult
More informationUniversity of California at Santa Barbara. ECE 154A Introduction to Computer Architecture. Quiz #1. October 30 th, Name (Last, First)
University of California at Santa Barbara ECE 154A Introduction to Computer Architecture Quiz #1 October 30 th, 2012 Name (Last, First) All grades will be posted on the website as a single spreadsheet
More informationDeveloping StrongARM/Linux shellcode
Into my ARMs Developing StrongARM/Linux shellcode by funkysh 16.12.2001 ----{ Introduction This paper covers informations needed to write StrongARM Linux shellcode. All examples presented
More informationUCB CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 6 Introduction to MIPS Data Transfer & Decisions I Sr Lecturer SOE Dan Garcia 2014-02-03 Prof Pieter Abbeel s recent research is in
More informationARM Instruction Set Architecture. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
ARM Instruction Set Architecture Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Condition Field (1) Most ARM instructions can be conditionally
More information101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009
101 Assembly ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 What is assembly? 79 Why are we learning assembly now? 80 Assembly Language Readings: Chapter 2 (2.1-2.6, 2.8, 2.9, 2.13, 2.15), Appendix
More informationCE1921: COMPUTER ARCHITECTURE SINGLE CYCLE PROCESSOR DESIGN WEEK 2
SUMMARY Instruction set architecture describes the programmer s view of the machine. This level of computer blueprinting allows design engineers to discover expected features of the circuit including:
More informationARM Assembly Programming
ARM Assembly Programming Computer Organization and Assembly Languages g Yung-Yu Chuang 2007/12/1 with slides by Peng-Sheng Chen GNU compiler and binutils HAM uses GNU compiler and binutils gcc: GNU C compiler
More informationThis has already been done for you within the School of CS at Nottingham.
AASM Manual (with School of CS, U. of Nottm., additions) ======================================================= (This is more of a set of notes than a true manual.) Beta - release! Compiling the assembler
More informationComparison InstruCtions
Status Flags Now it is time to discuss what status flags are available. These five status flags are kept in a special register called the Program Status Register (PSR). The PSR also contains other important
More informationECE 571 Advanced Microprocessor-Based Design Lecture 8
ECE 571 Advanced Microprocessor-Based Design Lecture 8 Vince Weaver http://web.eece.maine.edu/~vweaver vincent.weaver@maine.edu 16 February 2017 Announcements HW4 Due HW5 will be posted 1 HW#3 Review Energy
More informationWe will study the MIPS assembly language as an exemplar of the concept.
MIPS Assembly Language 1 We will study the MIPS assembly language as an exemplar of the concept. MIPS assembly instructions each consist of a single token specifying the command to be carried out, and
More informationAdvanced Assembly, Branching, and Monitor Utilities
2 Advanced Assembly, Branching, and Monitor Utilities 2.1 Objectives: There are several different ways for an instruction to form effective addresses to acquire data, called addressing modes. One of these
More informationSlide Set 1 (corrected)
Slide Set 1 (corrected) for ENCM 369 Winter 2018 Section 01 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary January 2018 ENCM 369 Winter 2018
More informationArchitecture II. Computer Systems Laboratory Sungkyunkwan University
MIPS Instruction ti Set Architecture II Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Making Decisions (1) Conditional operations Branch to a
More informationCSE A215 Assembly Language Programming for Engineers
CSE A215 Assembly Language Programming for Engineers Lecture 7 MIPS vs. ARM (COD Chapter 2 and Exam #1 Review) October 12, 2012 Sam Siewert Comparison of MIPS32 and ARM Instruction Formats and Addressing
More informationChapter 2. Instruction Set Architecture (ISA)
Chapter 2 Instruction Set Architecture (ISA) MIPS arithmetic Design Principle: simplicity favors regularity. Why? Of course this complicates some things... C code: A = B + C + D; E = F - A; MIPS code:
More informationProcedures, Parameters, Values and Variables. Steven R. Bagley
Procedures, Parameters, Values and Variables Steven R. Bagley Recap A Program is a sequence of statements (instructions) Statements executed one-by-one in order Unless it is changed by the programmer e.g.
More informationLecture 6 Decision + Shift + I/O
Lecture 6 Decision + Shift + I/O Instructions so far MIPS C Program add, sub, addi, multi, div lw $t0,12($s0) sw $t0, 12($s0) beq $s0, $s1, L1 bne $s0, $s1, L1 j L1 (unconditional branch) slt reg1,reg2,reg3
More informationControl Flow. September 2, Indiana University. Geoffrey Brown, Bryce Himebaugh 2015 September 2, / 21
Control Flow Geoffrey Brown Bryce Himebaugh Indiana University September 2, 2016 Geoffrey Brown, Bryce Himebaugh 2015 September 2, 2016 1 / 21 Outline Condition Codes C Relational Operations C Logical
More informationCOMP 303 MIPS Processor Design Project 3: Simple Execution Loop
COMP 303 MIPS Processor Design Project 3: Simple Execution Loop Due date: November 20, 23:59 Overview: In the first three projects for COMP 303, you will design and implement a subset of the MIPS32 architecture
More informationDECISION CONTROL AND LOOPING STATEMENTS
DECISION CONTROL AND LOOPING STATEMENTS DECISION CONTROL STATEMENTS Decision control statements are used to alter the flow of a sequence of instructions. These statements help to jump from one part of
More informationthe SAP-2 I. Intro cmpt-150-arc Sections 8-8, 8-9, 9-4, 9-5, 9.6, We ll do this in bits and pieces, doing the beginning of each section first.
I. Intro the SAP-2 cmpt-150-arc Sections 8-8, 8-9, 9-4, 9-5, 9.6, 9.8 1. We ll do this in bits and pieces, doing the beginning of each section first. 1. The SAP-2 adds a lot of functionality to the SAP-1
More informationAssembly language Simple, regular instructions building blocks of C, Java & other languages Typically one-to-one mapping to machine language
Assembly Language Readings: 2.1-2.7, 2.9-2.10, 2.14 Green reference card Assembly language Simple, regular instructions building blocks of C, Java & other languages Typically one-to-one mapping to machine
More informationCS 107e Lecture 4: From ASM to C Part 1 Friday, October 5, 2018
CS 107e Lecture 4: From ASM to C Part 1 Friday, October 5, 2018 Computer Systems from the Ground Up Fall 2018 Stanford University Computer Science Department Lecturer: Chris Gregg Logistics Assignment
More informationInstruction Set Architecture. "Speaking with the computer"
Instruction Set Architecture "Speaking with the computer" The Instruction Set Architecture Application Compiler Instr. Set Proc. Operating System I/O system Instruction Set Architecture Digital Design
More informationStored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands
Stored Program Concept Instructions: Instructions are bits Programs are stored in memory to be read or written just like data Processor Memory memory for data, programs, compilers, editors, etc. Fetch
More informationARM Instruction Set. Computer Organization and Assembly Languages Yung-Yu Chuang. with slides by Peng-Sheng Chen
ARM Instruction Set Computer Organization and Assembly Languages g Yung-Yu Chuang with slides by Peng-Sheng Chen Introduction The ARM processor is easy to program at the assembly level. (It is a RISC)
More informationDecision Making and Loops
Decision Making and Loops Goals of this section Continue looking at decision structures - switch control structures -if-else-if control structures Introduce looping -while loop -do-while loop -simple for
More informationControl MIPS unconditional branch instruction (i.e., jump)
Control Instruction that potentially changes the flow of program execution MIPS conditional branch instructions bne $s4, $s3, LABEL goto LABEL if $s4!= $s3 beq $s4, $s3, LABEL goto LABEL if $s4 == $s3
More informationInstruction-set Design Issues: what is the ML instruction format(s) ML instruction Opcode Dest. Operand Source Operand 1...
Instruction-set Design Issues: what is the format(s) Opcode Dest. Operand Source Operand 1... 1) Which instructions to include: How many? Complexity - simple ADD R1, R2, R3 complex e.g., VAX MATCHC substrlength,
More information2/5/2018. Learn Four More Kinds of C Statements. ECE 220: Computer Systems & Programming. C s if Statement Enables Conditional Execution
2/5/218 University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 22: Computer Systems & Programming Control Constructs in C (Partially a Review) Learn Four More Kinds
More informationReal instruction set architectures. Part 2: a representative sample
Real instruction set architectures Part 2: a representative sample Some historical architectures VAX: Digital s line of midsize computers, dominant in academia in the 70s and 80s Characteristics: Variable-length
More informationEEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture
EEM 486: Computer Architecture Lecture 2 MIPS Instruction Set Architecture EEM 486 Overview Instruction Representation Big idea: stored program consequences of stored program Instructions as numbers Instruction
More informationControl Structures in Java if-else and switch
Control Structures in Java if-else and switch Lecture 4 CGS 3416 Spring 2016 February 2, 2016 Control Flow Control flow refers to the specification of the order in which the individual statements, instructions
More informationECE 571 Advanced Microprocessor-Based Design Lecture 9
ECE 571 Advanced Microprocessor-Based Design Lecture 9 Vince Weaver http://www.eece.maine.edu/ vweaver vincent.weaver@maine.edu 30 September 2014 Announcements Next homework coming soon 1 Bulldozer Paper
More informationAssembly language Simple, regular instructions building blocks of C, Java & other languages Typically one-to-one mapping to machine language
Assembly Language Readings: 2.1-2.7, 2.9-2.10, 2.14 Green reference card Assembly language Simple, regular instructions building blocks of C, Java & other languages Typically one-to-one mapping to machine
More informationCSCI 2321 (Computer Design), Spring 2018 Homework 3
CSCI 2321 (Computer Design), Spring 2018 Homework 3 Credit: 50 points. 1 Reading Be sure you have read, or at least skimmed, all assigned sections of Chapter 2 and Appendix A. 2 Honor Code Statement Please
More informationToday s lecture. Translating an if-then statement
Today s lecture! Last lecture we started talking about control flow in MIPS (branches)! Finish up control-flow (branches) in MIPS if/then loops case/switch! Array Indexing vs. Pointers In particular pointer
More information