Stage Computation: Arith/Log. Ops

Transcription

1 Stage Computation: Arith/Log. Ops OPl ra, rb Fetch icode:ifun M 1 [PC] ra:rb M 1 [PC+1] Read instruction byte Read register byte back valp PC+2 vala R[rA] valb R[rB] vale valb OP vala Set CC R[rB] vale PC valp Compute next PC Read operand A Read operand B Perform ALU operation Set condition code register back result Update PC Formulate instruction execution as sequence of simple steps Use same general form for all instructions 1 CS:APP

2 Stage Computation: rmmovl Fetch rmmovl ra, D(rB) icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valc M 4 [PC+2] valp PC+6 vala R[rA] valb R[rB] vale valb + valc Read instruction byte Read register byte Read displacement D Compute next PC Read operand A Read operand B Compute effective address back M 4 [vale] vala PC valp value to memory Update PC Use ALU for address computation 2 CS:APP

3 Stage Computation: popl popl ra Fetch icode:ifun M 1 [PC] ra:rb M 1 [PC+1] Read instruction byte Read register byte back valp PC+2 vala R[%esp] valb R [%esp] vale valb + 4 valm M 4 [vala] R[%esp] vale R[rA] valm PC valp Compute next PC Read stack pointer Read stack pointer Increment stack pointer Read from stack Update stack pointer back result Update PC Use ALU to increment stack pointer Must update two registers Popped value New stack pointer 3 CS:APP

4 Stage Computation: Jumps jxx Dest icode:ifun M 1 [PC] Read instruction byte Fetch valc M 4 [PC+1] valp PC+5 Read destination address Fall through address back Bch Cond(CC,ifun) PC Bch? valc : valp Take branch? Update PC Compute both addresses Choose based on setting of condition codes and branch condition 4 CS:APP

5 Stage Computation: call call Dest icode:ifun M 1 [PC] Read instruction byte Fetch back valc M 4 [PC+1] valp PC+5 valb R[%esp] vale valb + 4 M 4 [vale] valp R[%esp] vale PC valc Read destination address Compute return point Read stack pointer Decrement stack pointer return value on stack Update stack pointer Set PC to destination Use ALU to decrement stack pointer Store incremented PC 5 CS:APP

6 Stage Computation: ret ret icode:ifun M 1 [PC] Read instruction byte Fetch back vala R[%esp] valb R[%esp] vale valb + 4 valm M 4 [vala] R[%esp] vale PC valm Read operand stack pointer Read operand stack pointer Increment stack pointer Read return address Update stack pointer Set PC to return address Use ALU to increment stack pointer Read return address from memory 6 CS:APP

7 Computation Steps OPl ra, rb Fetch icode,ifun ra,rb valc valp icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala, srca vala R[rA] valb, srcb valb R[rB] vale vale valb OP vala Cond code Set CC valm dste R[rB] vale back dstm PC PC valp Read instruction byte Read register byte [Read constant word] Compute next PC Read operand A Read operand B Perform ALU operation Set condition code register [ read/write] back ALU result [ back memory result] Update PC All instructions follow same general pattern Differ in what gets computed on each step 7 CS:APP

8 Computation Steps call Dest icode,ifun icode:ifun M 1 [PC] Read instruction byte Fetch ra,rb valc valc M 4 [PC+1] [Read register byte] Read constant word valp valp PC+5 Compute next PC vala, srca valb, srcb valb R[%esp] [Read operand A] Read operand B vale Cond code vale valb + 4 Perform ALU operation [Set condition code reg.] valm dste M 4 [vale] valp R[%esp] vale [ read/write] [ back ALU result] back dstm PC PC valc back memory result Update PC All instructions follow same general pattern Differ in what gets computed on each step 8 CS:APP

9 Computed Values Fetch icode ifun ra rb valc valp srca srcb dste dstm vala valb Instruction code Instruction function Instr. Register A Instr. Register B Instruction constant Incremented PC Register ID A Register ID B Destination Register E Destination Register M Register value A Register value B vale Bch ALU result Branch flag valm Value from memory 9 CS:APP

10 Logic Register File Read ports A, B ports E, M Addresses are register IDs or 8 (no access) vala valb A B M Register file E dste dstm srca srcb dste dstm srca srcb valm vale Control Logic srca, srcb: read port addresses dsta, dstb: write port addresses icode ra rb 10 CS:APP

11 A Source OPl ra, rb vala R[rA] rmmovl ra, D(rB) vala R[rA] popl ra vala R[%esp] jxx Dest call Dest ret vala R[%esp] Read operand A Read operand A Read stack pointer No operand No operand Read stack pointer int srca = [ icode in { IRRMOVL, IRMMOVL, IOPL, IPUSHL } : ra; icode in { IPOPL, IRET } : RESP; 1 : RNONE; # Don't need register ]; 11 CS:APP

12 E Destination -back -back -back -back -back -back OPl ra, rb R[rB] vale rmmovl ra, D(rB) popl ra R[%esp] vale jxx Dest call Dest R[%esp] vale ret R[%esp] vale back result None Update stack pointer None Update stack pointer Update stack pointer int dste = [ icode in { IRRMOVL, IIRMOVL, IOPL} : rb; icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP; 1 : RNONE; # Don't need register ]; 12 CS:APP

13 Logic Units ALU Implements 4 required functions Generates condition code values CC Register with 3 condition code bits bcond Computes branch flag Control Logic Set CC: Should condition code register be loaded? ALU A: Input A to ALU ALU B: Input B to ALU ALU fun: What function should ALU compute? Bch bcond CC Set CC ALU A vale ALU ALU B icode ifun valc vala valb ALU fun. 13 CS:APP

14 ALU A Input OPl ra, rb vale valb OP vala rmmovl ra, D(rB) vale valb + valc popl ra vale valb + 4 jxx Dest call Dest vale valb + 4 Perform ALU operation Compute effective address Increment stack pointer No operation Decrement stack pointer ret vale valb + 4 Increment stack pointer int alua = [ icode in { IRRMOVL, IOPL } : vala; icode in { IIRMOVL, IRMMOVL, IMRMOVL } : valc; icode in { ICALL, IPUSHL } : -4; icode in { IRET, IPOPL } : 4; # Other instructions don't need ALU ]; 14 CS:APP

15 ALU Operation OPl ra, rb vale valb OP vala Perform ALU operation rmmovl ra, D(rB) vale valb + valc popl ra vale valb + 4 jxx Dest call Dest vale valb + 4 Compute effective address Increment stack pointer No operation Decrement stack pointer ret vale valb + 4 Increment stack pointer int alufun = [ icode == IOPL : ifun; 1 : ALUADD; ]; 15 CS:APP

16 Logic valm Reads or writes memory word Control Logic Mem. read: should word be read? Mem. write: should word be written? Mem. addr.: Select address icode Mem. read Mem. write read write Data memory Mem addr vale data out Mem data data in vala valp Mem. data.: Select data 16 CS:APP

17 Address OPl ra, rb No operation rmmovl ra, D(rB) M 4 [vale] vala popl ra valm M 4 [vala] value to memory Read from stack jxx Dest No operation call Dest M 4 [vale] valp ret valm M 4 [vala] return value on stack Read return address int mem_addr = [ icode in { IRMMOVL, IPUSHL, ICALL, IMRMOVL } : vale; icode in { IPOPL, IRET } : vala; # Other instructions don't need address ]; 17 CS:APP

18 Read OPl ra, rb rmmovl ra, D(rB) M 4 [vale] vala popl ra valm M 4 [vala] No operation value to memory Read from stack jxx Dest No operation call Dest M 4 [vale] valp ret valm M 4 [vala] return value on stack Read return address bool mem_read = icode in { IMRMOVL, IPOPL, IRET }; 18 CS:APP

19 PC Update Logic PC New PC Select next value of PC New PC icode Bch valc valm valp 19 CS:APP

20 PC Update OPl ra, rb PC valp rmmovl ra, D(rB) PC valp Update PC Update PC popl ra PC valp Update PC jxx Dest PC Bch? valc : valp Update PC call Dest PC valc Set PC to destination ret PC valm Set PC to return address int new_pc = [ icode == ICALL : valc; icode == IJXX && Bch : valc; icode == IRET : valm; 1 : valp; ]; 20 CS:APP

21 SEQ Operation State PC register Combinational Logic CC Read Read Ports Data memory Register file Ports Cond. Code register Data memory Register file All updated as clock rises Combinational Logic ALU Control logic PC 0x00c reads Instruction memory Register file Data memory 21 CS:APP

22 SEQ Operation #2 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC 100 Read Read Ports Data memory Register file %ebx = 0x100 Ports state set according to second irmovl instruction combinational logic starting to react to state changes PC 0x00c 22 CS:APP

23 SEQ Operation #3 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC Read Read Ports Data memory Register file %ebx = 0x100 Ports state set according to second irmovl instruction combinational logic generates results for addl instruction 0x00e PC 0x00c 23 CS:APP

24 SEQ Operation #4 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC 000 Read Read Ports Data memory Register file %ebx = 0x300 Ports state set according to addl instruction combinational logic starting to react to state changes PC 0x00e 24 CS:APP

25 SEQ Operation #5 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC 000 Read Data memory Read Ports Ports Register file %ebx = 0x300 state set according to addl instruction combinational logic generates results for je instruction 0x013 PC 0x00e 25 CS:APP