Giving credit where credit is due

Transcription

1 CSCE 230J Computer Organization Processor Architecture III: Sequential Implementation Dr. Steve Goddard Giving credit where credit is due Most of slides for this lecture are based on slides created by Dr. Bryant, Carnegie Mellon University. I have modified them and added new slides. 2 Page 1

2 Y86 Instruction Set Byte nop 0 0 halt 1 0 rrmovl ra, rb 2 0 ra rb irmovl V, rb rb V rmmovl ra, D(rB) 4 0 ra rb D mrmovl D(rB), ra 5 0 ra rb D OPl ra, rb 6 fn ra rb jxx Dest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushl ra A 0 ra 8 popl ra B 0 ra 8 addl 6 0 subl 6 1 andl 6 2 xorl 6 3 jmp 7 0 jle 7 1 jl 7 2 je 7 3 jne 7 4 jge 7 5 jg Building Blocks fun Combinational Logic Compute Boolean functions of inputs Continuously respond to input changes Operate on data and implement control A B A L U 0 MUX 1 = Storage Elements Store bits Addressable memories vala srca valb A Register file W valw dstw Non-addressable registers srcb B Clock Loaded only as clock rises Clock 4 Page 2

3 Hardware Control Language Very simple hardware description language Can only express limited aspects of hardware operation Parts we want to explore and modify Data Types bool: Boolean a, b, c, int: words A, B, C, Does not specify word size---bytes, 32-bit words, Statements bool a = bool-expr ; int A = int-expr ; 5 HCL Operations Classify by type of value returned Boolean Expressions Logic Operations a && b, a b,!a Word Comparisons A == B, A!= B, A < B, A <= B, A >= B, A > B Set Membership A in { B, C, D }» Same as A == B A == C A == D Word Expressions Case expressions [ a : A; b : B; c : C ] Evaluate test expressions a, b, c, in sequence Return word expression A, B, C, for first successful test 6 Page 3

4 SEQ Hardware Structure State Program counter register () Condition code register (CC) Register File Memories Access same space Data: for reading/writing program data Instruction: for reading instructions Instruction Flow Read instruction at address specified by Process through stages Update program counter back icode, ifun ra, rb Instruction new vale, valm Addr, Data Bch CC alua, alub srca, srcb dsta, dstb valm Data valp vale vala, valb increment A B Register M file E 7 SEQ Stages back new vale, valm valm Read instruction from instruction Read program registers Compute value or address Read or write data Back program registers Update program counter icode, ifun ra, rb Instruction Addr, Data Bch CC alua, alub srca, srcb dsta, dstb Data valp vale vala, valb increment A B Register M file E 8 Page 4

5 Instruction Decoding Optional Optional 5 0 ra rb D icode ifun ra rb Instruction Format Instruction byte Optional register byte Optional constant word icode:ifun ra:rb 9 Executing Arith./Logical Operation OPl ra, rb 6 fn ra rb Read 2 bytes Read operand registers Perform operation Set condition codes Do nothing back Update register Update Increment by 2 10 Page 5

6 Stage Computation: Arith/Log. Ops back update OPl ra, rb icode:ifun M 1 [] ra:rb M 1 [+1] valp +2 vala R[rA] valb R[rB] vale valb OP vala Set CC R[rB] vale valp Read instruction byte Read register byte Compute next Read operand A Read operand B Perform operation Set condition code register back result Update Formulate instruction execution as sequence of simple steps Use same general form for all instructions 11 Executing rmmovl rmmovl ra, D(rB) 4 0 ra rb D Read 6 bytes Read operand registers Compute effective address to back Do nothing Update Increment by 6 12 Page 6

7 Stage Computation: rmmovl back update rmmovl ra, D(rB) icode:ifun M 1 [] ra:rb M 1 [+1] M 4 [+2] valp +6 vala R[rA] valb R[rB] vale valb + M 4 [vale] vala valp Read instruction byte Read register byte Read displacement D Compute next Read operand A Read operand B Compute effective address value to Update Use for address computation 13 Executing popl popl ra b 0 ra 8 Read 2 bytes Read stack pointer Increment stack pointer by 4 Read from old stack pointer back Update stack pointer result to register Update Increment by 2 14 Page 7

8 Stage Computation: popl popl ra icode:ifun M 1 [] ra:rb M 1 [+1] Read instruction byte Read register byte back update valp +2 vala R[%esp] valb R [%esp] vale valb + 4 valm M 4 [vala] R[%esp] vale R[rA] valm valp Compute next Read stack pointer Read stack pointer Increment stack pointer Read from stack Update stack pointer back result Update Use to increment stack pointer Must update two registers Popped value New stack pointer 15 Executing Jumps jxx Dest 7 fn Dest fall thru: XX XX Not taken target: XX XX Taken Read 5 bytes Increment by 5 Do nothing Determine whether to take branch based on jump condition and condition codes Do nothing back Do nothing Update Set to Dest if branch taken or to incremented if not branch 16 Page 8

9 Stage Computation: Jumps jxx Dest icode:ifun M 1 [] M 4 [+1] valp +5 Read instruction byte Read destination address Fall through address back update Bch Cond(CC,ifun) Bch? : valp Take branch? Update Compute both addresses Choose based on setting of condition codes and branch condition 17 Executing call call Dest 8 0 Dest return: XX XX target: XX XX Read 5 bytes Increment by 5 Read stack pointer Decrement stack pointer by 4 incremented to new value of stack pointer back Update stack pointer Update Set to Dest 18 Page 9

10 Stage Computation: call back update call Dest icode:ifun M 1 [] M 4 [+1] valp +5 valb R[%esp] vale valb + 4 M 4 [vale] valp R[%esp] vale Read instruction byte Read destination address Compute return point Read stack pointer Decrement stack pointer return value on stack Update stack pointer Set to destination Use to decrement stack pointer Store incremented 19 Executing ret ret 9 0 return: XX XX Read 1 byte Read stack pointer Increment stack pointer by 4 Read return address from old stack pointer back Update stack pointer Update Set to return address 20 Page 10

11 Stage Computation: ret ret icode:ifun M 1 [] Read instruction byte back update vala R[%esp] valb R[%esp] vale valb + 4 valm M 4 [vala] R[%esp] vale valm Read operand stack pointer Read operand stack pointer Increment stack pointer Read return address Update stack pointer Set to return address Use to increment stack pointer Read return address from 21 Computation Steps OPl ra, rb icode,ifun icode:ifun M 1 [] Read instruction byte ra,rb ra:rb M 1 [+1] Read register byte [Read constant word] valp valp +2 Compute next vala, srca valb, srcb vala R[rA] valb R[rB] Read operand A Read operand B vale Cond code vale valb OP vala Set CC Perform operation Set condition code register valm [ read/write] dste R[rB] vale back result back dstm [ back result] update valp Update All instructions follow same general pattern Differ in what gets computed on each step 22 Page 11

12 Computation Steps back update icode,ifun ra,rb valp vala, srca valb, srcb vale Cond code valm dste dstm call Dest icode:ifun M 1 [] M 4 [+1] valp +5 valb R[%esp] vale valb + 4 M 4 [vale] valp R[%esp] vale Read instruction byte [Read register byte] Read constant word Compute next [Read operand A] Read operand B Perform operation [Set condition code reg.] [ read/write] [ back result] back result Update All instructions follow same general pattern Differ in what gets computed on each step 23 Computed Values icode ifun ra rb valp srca srcb dste dstm vala valb Instruction code Instruction function Instr. Register A Instr. Register B Instruction constant Incremented Register ID A Register ID B Destination Register E Destination Register M Register value A Register value B vale result Bch Branch flag valm Value from 24 Page 12

13 SEQ Hardware Key Blue boxes: predesigned hardware blocks E.g., memories, Gray boxes: control logic Describe in HCL White ovals: labels for signals Thick lines: 32-bit word values Thin lines: 4-8 bit values Dotted lines: 1-bit values Bch CC icode ifun ra Mem. control A Instruction new New rb read write vale Data Addr B valm valp data out Data vala increment fun. valb A B Register M file E dste dstm srca srcb dste dstm srca srcb back 25 Logic icode ifun ra rb valp Instr valid Need Need regids increment Split Byte 0 Instruction Align Bytes 1-5 Predefined Blocks : Register containing Instruction : Read 6 bytes ( to +5) Split: Divide instruction byte into icode and ifun Align: Get fields for ra, rb, and 26 Page 13

14 Logic icode ifun ra rb valp Instr valid Need Need regids increment Split Align Byte 0 Instruction Bytes 1-5 Control Logic Instr. Valid: Is this instruction valid? Need regids: Does this instruction have a register bytes? Need : Does this instruction have a constant word? 27 Control Logic nop 0 0 halt 1 0 rrmovl ra, rb 2 0 ra rb irmovl V, rb rb V rmmovl ra, D(rB) 4 0 ra rb D mrmovl D(rB), ra 5 0 ra rb D OPl ra, rb 6 fn ra rb jxx Dest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushl ra A 0 ra 8 popl ra B 0 ra 8 bool need_regids = icode in { IRRMOVL, IOPL, IPUSHL, IPOPL, IIRMOVL, IRMMOVL, IMRMOVL }; bool instr_valid = icode in { INOP, IHALT, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL, IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL }; 28 Page 14

15 Logic Register File Read ports A, B ports E, M Addresses are register IDs or 8 (no access) vala valb A B Register M file E dste dstm srca srcb dste dstm srca srcb valm vale Control Logic srca, srcb: read port addresses dsta, dstb: write port addresses icode ra rb 29 A Source OPl ra, rb vala R[rA] rmmovl ra, D(rB) vala R[rA] popl ra vala R[%esp] jxx Dest call Dest Read operand A Read operand A Read stack pointer No operand No operand ret vala R[%esp] Read stack pointer int srca = [ icode in { IRRMOVL, IRMMOVL, IOPL, IPUSHL } : ra; icode in { IPOPL, IRET } : RESP; 1 : RNONE; # Don't need register ]; 30 Page 15

16 E Destination -back -back -back -back -back OPl ra, rb R[rB] vale rmmovl ra, D(rB) popl ra R[%esp] vale jxx Dest call Dest R[%esp] vale back result None Update stack pointer None Update stack pointer -back ret R[%esp] vale int dste = [ icode in { IRRMOVL, IIRMOVL, IOPL} : rb; icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP; 1 : RNONE; # Don't need register ]; Update stack pointer 31 Logic Units Implements 4 required functions Generates condition code values CC Register with 3 condition code bits bcond Computes branch flag Control Logic Set CC: Should condition code register be loaded? A: Input A to B: Input B to fun: What function should compute? Bch bcond CC Set CC A vale B icode ifun vala valb fun. 32 Page 16

17 A Input OPl ra, rb vale valb OP vala rmmovl ra, D(rB) vale valb + popl ra vale valb + 4 jxx Dest call Dest vale valb + 4 Perform operation Compute effective address Increment stack pointer No operation Decrement stack pointer ret vale valb + 4 Increment stack pointer int alua = [ icode in { IRRMOVL, IOPL } : vala; icode in { IIRMOVL, IRMMOVL, IMRMOVL } : ; icode in { ICALL, IPUSHL } : -4; icode in { IRET, IPOPL } : 4; # Other instructions don't need ]; 33 Operation OPl ra, rb vale valb OP vala Perform operation rmmovl ra, D(rB) vale valb + popl ra vale valb + 4 jxx Dest call Dest vale valb + 4 Compute effective address Increment stack pointer No operation Decrement stack pointer ret vale valb + 4 Increment stack pointer int alufun = [ icode == IOPL : ifun; 1 : ADD; ]; 34 Page 17

18 Logic Reads or writes word Control Logic Mem. read: should word be read? Mem. write: should word be written? Mem. addr.: Select address Mem. data.: Select data Mem. read Mem. write read write Data Mem addr valm data out Mem data data in icode vale vala valp 35 Address OPl ra, rb No operation rmmovl ra, D(rB) M 4 [vale] vala popl ra valm M 4 [vala] jxx Dest call Dest M 4 [vale] valp ret valm M 4 [vala] value to Read from stack No operation return value on stack Read return address int mem_addr = [ icode in { IRMMOVL, IPUSHL, ICALL, IMRMOVL } : vale; icode in { IPOPL, IRET } : vala; # Other instructions don't need address ]; 36 Page 18

19 Read OPl ra, rb rmmovl ra, D(rB) M 4 [vale] vala popl ra valm M 4 [vala] jxx Dest call Dest M 4 [vale] valp ret valm M 4 [vala] No operation value to Read from stack No operation return value on stack Read return address bool mem_read = icode in { IMRMOVL, IPOPL, IRET }; 37 Update Logic New Select next value of New icode Bch valm valp 38 Page 19

20 Update update update OPl ra, rb valp rmmovl ra, D(rB) valp Update Update update popl ra valp Update update jxx Dest Bch? : valp Update update call Dest Set to destination update ret valm Set to return address int new_pc = [ icode == ICALL : ; icode == IJXX && Bch : ; icode == IRET : valm; 1 : valp; ]; 39 SEQ Operation Combinational Logic CC 0x00c Read Read Ports Data Register file Ports State register Cond. Code register Data Register file All updated as clock rises Combinational Logic Control logic reads Instruction Register file Data 40 Page 20

21 SEQ Operation #2 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC 100 Read Read Ports Data Register file %ebx = 0x100 Ports state set according to second irmovl instruction combinational logic starting to react to state changes 0x00c 41 SEQ Operation #3 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC Read Read Ports Data Register file %ebx = 0x100 Ports state set according to second irmovl instruction combinational logic generates results for addl instruction 0x00c 0x00e 42 Page 21

22 SEQ Operation #4 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC 000 Read Read Ports Data Register file %ebx = 0x300 Ports state set according to addl instruction combinational logic starting to react to state changes 0x00e 43 SEQ Operation #5 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC 000 Read Data Read Ports Ports Register file %ebx = 0x300 state set according to addl instruction combinational logic generates results for je instruction 0x00e 0x Page 22

23 SEQ Summary Implementation Express every instruction as series of simple steps Follow same general flow for each instruction type Assemble registers, memories, predesigned combinational blocks Connect with control logic Limitations Too slow to be practical In one cycle, must propagate through instruction, register file,, and data Would need to run clock very slowly Hardware units only active for fraction of clock cycle 45 Page 23