Computer Science 104:! Y86 & Single Cycle Processor Design!

Transcription

1 Computer Science 104: Y86 & Single Cycle Processor Design Alvin R. Lebeck Slides based on those from Randy Bryant CS:APP Administrative HW #4 Due tomorrow tonight HW #5 up soon ing: Today Review Y86 & datapath Control 2 CS:APP

2 Y86 Instruction Set Byte nop 0 0 halt 1 0 rrmovl ra, rb 2 0 ra rb irmovl V, rb rb V addl 6 0 subl 6 1 andl 6 2 xorl 6 3 rmmovl ra, D(rB) 4 0 ra rb D jmp 7 0 mrmovl D(rB), ra 5 0 ra rb D jle 7 1 OPl ra, rb 6 fn ra rb jl 7 2 jxx Dest 7 fn Dest je 7 3 call Dest 8 0 Dest jne 7 4 ret 9 0 jge 7 5 pushl ra A 0 ra 8 jg 7 6 popl ra B 0 ra 8 3 CS:APP Building Blocks fun Combinational Logic n Compute Boolean functions of inputs n Continuously respond to input changes n Operate on data and implement control A B A L U 0 MUX 1 = Storage Elements n Store bits n Addressable memories vala srca valb A Register file valw W dstw n Non-addressable registers srcb B Clock n Loaded only as clock rises Clock 4 CS:APP

3 SEQ Stages back new vale, valm valm Fetch n instruction from instruction n program registers n Compute value or address Memory n or write data Back n program registers n Update program counter Memory Fetch icode, ifun ra,rb valc Instruction increment 5 CS:APP Addr, Data Bch CC alua, alub srca, srcb dsta, dstb Data valp vale ALU vala, valb Register A B M file E Executing Arith./Logical Operation OPl ra, rb Fetch n 2 bytes n operand registers n Perform operation n Set condition codes 6 fn rarb Memory n Do nothing back n Update register Update n Increment by 2 6 CS:APP

4 Stage Computation: Arith/Log. Ops Fetch OPl ra, rb icode:ifun M 1 [] ra:rb M 1 [+1] valp +2 vala R[rA] valb R[rB] vale valb OP vala Set CC instruction byte register byte Compute next operand A operand B Perform ALU operation Set condition code register Memory R[rB] vale back result back update valp Update n Formulate instruction execution as sequence of simple steps n Use same general form for all instructions 7 CS:APP Executing call call Dest 8 0 Dest return: XX XX target: XX XX Fetch n 5 bytes n Increment by 5 n stack pointer n Decrement stack pointer by 4 Memory n incremented to new value of stack pointer back n Update stack pointer Update n Set to Dest 8 CS:APP

5 Stage Computation: call call Dest icode:ifun M 1 [] instruction byte Fetch valc M 4 [+1] valp +5 valb R[%esp] vale valb + 4 destination address Compute return point stack pointer Decrement stack pointer Memory M 4 [vale] valp return value on stack R[%esp] vale Update stack pointer back update valc Set to destination n Use ALU to decrement stack pointer n Store incremented 9 CS:APP Executing ret ret 9 0 return: XX XX Fetch n 1 byte n stack pointer n Increment stack pointer by 4 Memory n return address from old stack pointer back n Update stack pointer Update n Set to return address 10 CS:APP

6 Stage Computation: ret ret icode:ifun M 1 [] instruction byte Fetch Memory back update vala R[%esp] valb R[%esp] vale valb + 4 valm M 4 [vala] R[%esp] vale valm operand stack pointer operand stack pointer Increment stack pointer return address Update stack pointer Set to return address n Use ALU to increment stack pointer n return address from 11 CS:APP Computed Values Fetch icode ifun Instruction code Instruction function ra Instr. Register A rb Instr. Register B valc valp Instruction constant Incremented srca Register ID A srcb Register ID B dste Destination Register E dstm Destination Register M vala Register value A valb Register value B n vale n Bch Memory ALU result Branch flag n valm Value from 12 CS:APP

7 Computation Steps OPl icode,ifun OPl ra, rb icode:ifun M 1 [] instruction byte Fetch ra,rb ra:rb M 1 [+1] register byte valc [ constant word] valp valp +2 Compute next vala, srca vala R[rA] operand A valb, srcb valb R[rB] operand B vale vale valb OP vala Perform ALU operation Cond code Set CC Set condition code register Memory valm [Memory read/write] back dste dstm R[rB] vale back ALU result [ back result] update valp Update n All instructions follow same general pattern n Differ in what gets computed on each step 13 CS:APP Computation Steps Call Fetch Memory back update icode,ifun ra,rb valc valp vala, srca valb, srcb vale Cond code valm dste dstm call Dest icode:ifun M 1 [] valc M 4 [+1] valp +5 valb R[%esp] vale valb + 4 M 4 [vale] valp R[%esp] vale valc instruction byte [ register byte] constant word Compute next [ operand A] operand B Perform ALU operation [Set condition code reg.] [Memory read/write] [ back ALU result] back result Update n All instructions follow same general pattern n Differ in what gets computed on each step 14 CS:APP

8 Control for Datapath Need to design the logic to compute values Break into stages of instruction execution Fetch, Decode, Execute, Memory, back, update Lectures, text, some homework use Y86 Some homework / project will use a different instruction set (RISC) 15 CS:APP Hardware Control Language n Very simple hardware description language n Can only express limited aspects of hardware operation l Parts we want to explore and modify Data Types n n bool: Boolean l a, b, c, int: words l A, B, C, Statements l Does not specify word size---bytes, 32-bit words, n bool a = bool-expr ; n int A = int-expr ; 16 CS:APP

9 HCL Operations n Classify by type of value returned Boolean Expressions n Logic Operations l a && b, a b, a n Word Comparisons l A == B, A = B, A < B, A <= B, A >= B, A > B n Set Membership l A in { B, C, D }» Same as A == B A == C A == D Word Expressions n Case expressions l [ a : A; b : B; c : C ] l Evaluate test expressions a, b, c, in sequence l Return word expression A, B, C, for first successful test 17 CS:APP SEQ Hardware Key n Blue boxes: predesigned hardware blocks l E.g., memories, ALU n Gray boxes: control logic l Describe in HCL n White ovals: labels for signals n Thick lines: 32-bit word values n Thin lines: 4-8 bit values n Dotted lines: 1-bit values Memory Execute Decode Fetch Bch CC icode ifun ra Mem. control ALU A Instruction new New rb read write vale ALU valc Data Addr ALU B valm data out Data valp vala increment ALU fun. valb A B Register M file E dste dstm srca srcb dste dstm srca srcb back 18 CS:APP

10 Fetch Logic icode ifun ra rb valc valp Instr valid Need valc Need regids increment Split Byte 0 Instruction Align Bytes 1-5 Predefined Blocks n : Register containing n Instruction : 6 bytes ( to +5) n Split: Divide instruction byte into icode and ifun n Align: Get fields for ra, rb, and valc 19 CS:APP Fetch Logic icode ifun ra rb valc valp Instr valid Need valc Need regids increment Split Byte 0 Instruction Align Bytes 1-5 Control Logic n Instr. Valid: Is this instruction valid? n Need regids: Does this instruction have a register byte? n Need valc: Does this instruction have a constant word? 20 CS:APP

11 Fetch Control Logic nop 0 0 halt 1 0 rrmovl ra, rb 2 0 ra rb irmovl V, rb rb V rmmovl ra, D(rB) 4 0 ra rb D mrmovl D(rB), ra 5 0 ra rb D OPl ra, rb 6 fn ra rb jxx Dest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushl ra A 0 ra 8 popl ra B 0 ra 8 bool need_regids = icode in { IRRMOVL, IOPL, IPUSHL, IPOPL, IIRMOVL, IRMMOVL, IMRMOVL }; bool instr_valid = icode in { INOP, IHALT, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL, IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL }; 21 CS:APP Decode Logic Register File n ports A, B n ports E, M n Addresses are register IDs or 8 (no access) vala valb A B Register M file E dste dstm srca srcb dste dstm srca srcb valm vale Control Logic n srca, srcb: read port addresses n dsta, dstb: write port addresses icode ra rb 22 CS:APP

12 A Source OPl ra, rb vala R[rA] operand A rmmovl ra, D(rB) vala R[rA] operand A popl ra vala R[%esp] jxx Dest call Dest stack pointer No operand No operand ret vala R[%esp] stack pointer int srca = [ icode in { IRRMOVL, IRMMOVL, IOPL, IPUSHL } : ra; icode in { IPOPL, IRET } : RESP; 1 : RNONE; # Don't need register ]; 23 CS:APP E Destination -back -back -back -back -back OPl ra, rb R[rB] vale rmmovl ra, D(rB) popl ra R[%esp] vale jxx Dest call Dest R[%esp] vale back result None Update stack pointer None Update stack pointer -back ret R[%esp] vale Update stack pointer int dste = [ icode in { IRRMOVL, IIRMOVL, IOPL} : rb; icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP; 1 : RNONE; # Don't need register ]; 24 CS:APP

13 Execute Logic Units n ALU n CC l Implements 4 required functions l Generates condition code values l Register with 3 condition code bits n bcond Control Logic l Computes branch flag n Set CC: Should condition code register be loaded? n ALU A: Input A to ALU n ALU B: Input B to ALU n ALU fun: What function should ALU compute? 25 CS:APP Bch bcond CC Set CC ALU A vale ALU ALU B icode ifun valc vala valb ALU fun. ALU A Input OPl ra, rb vale valb OP vala Perform ALU operation rmmovl ra, D(rB) vale valb + valc popl ra vale valb + 4 jxx Dest call Dest vale valb + 4 Compute effective address Increment stack pointer No operation Decrement stack pointer ret vale valb + 4 Increment stack pointer int alua = [ icode in { IRRMOVL, IOPL } : vala; icode in { IIRMOVL, IRMMOVL, IMRMOVL } : valc; icode in { ICALL, IPUSHL } : -4; icode in { IRET, IPOPL } : 4; 26 # Other instructions don't need ALU CS:APP ];

14 ALU Operation OPl ra, rb vale valb OP vala Perform ALU operation rmmovl ra, D(rB) vale valb + valc popl ra vale valb + 4 jxx Dest call Dest vale valb + 4 Compute effective address Increment stack pointer No operation Decrement stack pointer ret vale valb + 4 Increment stack pointer int alufun = [ icode == IOPL : ifun; 1 : ALUADD; 27 ]; CS:APP Memory Logic Memory n s or writes word Control Logic n Mem. read: should word be read? n Mem. write: should word be written? n Mem. addr.: Select address n Mem. data.: Select data icode Mem. read Mem. write read write Data Mem addr vale valm data out Mem data data in vala valp 28 CS:APP

15 Memory Address OPl ra, rb Memory No operation rmmovl ra, D(rB) Memory M 4 [vale] vala value to popl ra Memory valm M 4 [vala] from stack jxx Dest Memory No operation call Dest Memory M 4 [vale] valp return value on stack Memory ret valm M 4 [vala] return address int mem_addr = [ icode in { IRMMOVL, IPUSHL, ICALL, IMRMOVL } : vale; icode in { IPOPL, IRET } : vala; # Other instructions don't need address 29 CS:APP ]; Memory Memory OPl ra, rb No operation rmmovl ra, D(rB) Memory M 4 [vale] vala value to popl ra Memory valm M 4 [vala] from stack jxx Dest Memory No operation call Dest Memory M 4 [vale] valp return value on stack Memory ret valm M 4 [vala] return address bool mem_read = icode in { IMRMOVL, IPOPL, IRET }; 30 CS:APP

16 Update Logic New n Select next value of New icode Bch valc valm valp 31 CS:APP Update update update update update update update OPl ra, rb valp rmmovl ra, D(rB) valp popl ra valp jxx Dest Bch? valc : valp call Dest valc ret valm Update Update Update Update Set to destination Set to return address int new_pc = [ icode == ICALL : valc; icode == IJXX && Bch : valc; icode == IRET : valm; 1 : valp; ]; 32 CS:APP

17 SEQ Operation Combinational Logic CC 0x00c Data Register file State n register n Cond. Code register n Data n Register file All updated as clock rises Combinational Logic n ALU n Control logic n Memory reads l Instruction l Register file l Data 33 CS:APP SEQ Operation #2 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC 100 Data Register file %ebx = 0x100 n state set according to second irmovl instruction n combinational logic starting to react to state changes 0x00c 34 CS:APP

18 SEQ Operation #3 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC Data Register file %ebx = 0x100 n state still set according to second irmovl instruction n combinational logic generates results for addl instruction 0x00e 0x00c 35 CS:APP SEQ Operation #4 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC 000 Data Register file %ebx = 0x300 n state set according to addl instruction n combinational logic starting to react to state changes 0x00e 36 CS:APP

19 SEQ Operation #5 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic Data n state set according to addl instruction CC 000 n combinational logic generates Register results for je file %ebx = 0x300 instruction l y to take 0x013 effect at rising edge 0x00e 37 CS:APP SEQ Summary Implementation n Express every instruction as series of simple steps n Follow same general flow for each instruction type n Assemble registers, memories, predesigned combinational blocks n Connect with control logic Limitations n Too slow to be practical n In one cycle, must propagate through instruction, register file, ALU, and data n Would need to run clock very slowly n Hardware units only active for fraction of clock cycle 38 CS:APP