CISC Fall 2009

Transcription

1 Michela Taufer October 20, 2009 Powerpoint Lecture Notes for Computer Systems: A Programmer's Perspective, R. Bryant and D. O'Hallaron, Prentice Hall, 2003 Y86 Instruction Set Byte nop 0 0 halt 1 0 rrmovl ra, rb 2 0 ra rb irmovl V, rb rb V addl 6 0 subl 6 1 andl 6 2 xorl ra rb D jmp 7 0 mrmovl D(rB), ra 5 0 ra rb D jle fn ra rb jl fn Dest je Dest jne jge 7 5 pushl ra A 0 ra 8 jg 7 6 B 0 ra 8 2 CS:APP Building Blocks fun Hardware Control Language A B A L U 0 MUX = 1 vala srca valb A W valw dstw srcb B 3 CS:APP 4 CS:APP

2 HCL Operations SEQ Hardware Structure new, Addr, Bch alua, alub vala, valb icode, ifun ra, rb Instruction srca, srcb dsta, dstb increment A B M E 5 CS:APP 6 CS:APP SEQ Stages new, Instruction Decoding Addr, Optional Optional 5 0 ra rb D Bch icode, ifun ra, rb Instruction alua, alub srca, srcb dsta, dstb vala, valb increment A B M E icode ifun ra rb 7 CS:APP 8 CS:APP

3 Executing Arith./al Operation 6 fn rarb Stage Computation: Arith/Log. Ops icode:ifun M 1 [] ra:rb M 1 [+1] instruction byte register byte +2 vala R[rA] valb R[rB] valb OP vala Set R[rB] update Compute next operand A operand B Perform operation Set condition code register result Update Formulate instruction execution as sequence of simple steps Use same general form for all instructions 9 CS:APP 10 CS:APP Executing rmmovl 4 0 rarb D Stage Computation: rmmovl icode:ifun M 1 [] ra:rb M 1 [+1] M 4 [+2] +6 vala R[rA] valb R[rB] valb + instruction byte register byte displacement D Compute next operand A operand B Compute effective address M 4 [] vala update value to Update Use for address computation 11 CS:APP 12 CS:APP

4 Executing popl b 0 ra 8 Stage Computation: popl icode:ifun M 1 [] ra:rb M 1 [+1] instruction byte register byte +2 vala R[%esp] valb R [%esp] valb + 4 Compute next stack pointer stack pointer Increment stack pointer M 4 [vala] R[%esp] R[rA] update from stack result Update 13 CS:APP Use to increment stack pointer Must update two registers Popped value 14 New stack pointer CS:APP Executing Jumps 7 fn Dest fall thru: XX XX target: XX XX Not taken Taken Stage Computation: Jumps icode:ifun M 1 [] M 4 [+1] +5 instruction byte destination address Fall through address Bch Cond(,ifun) update Bch? : Take branch? Update 15 CS:APP Compute both addresses Choose based on setting of condition codes and branch condition 16 CS:APP

5 Executing call 8 0 Dest urn: XX XX target: XX XX Stage Computation: call icode:ifun M 1 [] M 4 [+1] +5 valb R[%esp] valb + 4 instruction byte destination address Compute urn point stack pointer Decrement stack pointer M 4 [] R[%esp] update urn value on stack Set to destination Use to decrement stack pointer Store incremented 17 CS:APP 18 CS:APP Executing 9 0 Stage Computation: icode:ifun M 1 [] instruction byte urn: XX XX vala R[%esp] valb R[%esp] operand stack pointer operand stack pointer valb + 4 Increment stack pointer M 4 [vala] R[%esp] update urn address Set to urn address Use to increment stack pointer urn address from 19 CS:APP 20 CS:APP

6 Computation Steps update icode,ifun ra,rb vala, srca valb, srcb Cond code dste dstm icode:ifun M 1 [] ra:rb M 1 [+1] +2 vala R[rA] valb R[rB] valb OP vala Set R[rB] instruction byte register byte [ constant word] Compute next operand A operand B Perform operation Set condition code register [ read/write] result [ result] Update Computation Steps update icode,ifun ra,rb vala, srca valb, srcb Cond code dste dstm icode:ifun M 1 [] M 4 [+1] +5 valb R[%esp] valb + 4 M 4 [] R[%esp] instruction byte [ register byte] constant word Compute next [ operand A] operand B Perform operation [Set condition code reg.] [ read/write] [ result] result Update All instructions follow same general pattern Differ in what gets computed on each step All instructions follow same general pattern Differ in what gets computed on each step 21 CS:APP 22 CS:APP Computed Values SEQ Hardware new New read Mem. control write data out Addr Bch fun. A B vala valb dste dstm srca srcb dste dstm srca srcb A B M E icode ifun ra rb Instruction increment 23 CS:APP 24 CS:APP

7 icode ifun ra rb icode ifun ra rb Instr valid Split Byte 0 Align Instruction Bytes 1-5 Need Need regids increment Instr valid Split Byte 0 Align Instruction Bytes 1-5 Need Need regids increment 25 CS:APP 26 CS:APP Control nop halt 2 0 rrmovl ra, rb ra rb rb irmovl V, rb V vala valb 4 0 ra rb D mrmovl D(rB), ra 5 0 ra rb D 6 fn ra rb A B M E dste dstm srca srcb 7 fn Dest 8 0 Dest 9 0 dste dstm srca srcb pushl ra A 0 ra 8 B 0 ra 8 icode ra rb bool need_regids = icode in { IRRMOVL, IOPL, IPUSHL, IPOPL, IIRMOVL, IRMMOVL, IMRMOVL }; bool instr_valid = icode in { INOP, IHALT, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL, IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL }; 27 CS:APP 28 CS:APP

8 A Source vala R[rA] operand A E Destination - R[rB] result vala R[rA] operand A - None vala R[%esp] stack pointer - R[%esp] No operand - None No operand - R[%esp] vala R[%esp] stack pointer int srca = [ icode in { IRRMOVL, IRMMOVL, IOPL, IPUSHL } : ra; icode in { IPOPL, IRET } : RESP; 1 : RNONE; # Don't need register 29 CS:APP - R[%esp] int dste = [ icode in { IRRMOVL, IIRMOVL, IOPL} : rb; icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP; 1 : RNONE; # Don't need register 30 CS:APP A Input valb OP vala Perform operation valb + Compute effective address Bch valb + 4 Increment stack pointer bcond 31 CS:APP Set A B icode ifun vala valb fun. valb + 4 Decrement stack pointer valb + 4 Increment stack pointer int alua = [ icode in { IRRMOVL, IOPL } : vala; icode in { IIRMOVL, IRMMOVL, IMRMOVL } : ; icode in { ICALL, IPUSHL } : -4; icode in { IRET, IPOPL } : 4; 32 # Other instructions don't need CS:APP

9 Operation valb OP vala valb + valb + 4 Perform operation Compute effective address Increment stack pointer Mem. read Mem. write read write data out data in Mem addr Mem data valb + 4 Decrement stack pointer icode vala valb + 4 Increment stack pointer int alufun = [ icode == IOPL : ifun; 1 : ADD; 33 CS:APP 34 CS:APP Address M 4 [] vala M 4 [vala] M 4 [] M 4 [vala] value to from stack urn value on stack urn address int mem_addr = [ icode in { IRMMOVL, IPUSHL, ICALL, IMRMOVL } : ; icode in { IPOPL, IRET } : vala; # Other instructions don't need address 35 CS:APP M 4 [] vala value to M 4 [vala] from stack M 4 [] urn value on stack M 4 [vala] urn address bool mem_read = icode in { IMRMOVL, IPOPL, IRET }; 36 CS:APP

10 Update Update update update Update Update New icode Bch update update Bch? : update update Update Update Set to destination Set to urn address 37 CS:APP int new_pc = [ icode == ICALL : ; icode == IJXX && Bch : ; icode == IRET : ; 1 : ; 38 CS:APP SEQ Operation Combinational SEQ Operation #2 Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 < x00e: je dest # Not taken 0x00c Combinational 100 %ebx = 0x100 state set according to second irmovl instruction combinational logic starting to react to state changes 39 CS:APP 0x00c 40 CS:APP

11 SEQ Operation #3 Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 < x00e: je dest # Not taken SEQ Operation #4 Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 < x00e: je dest # Not taken Combinational %ebx = 0x100 state set according to second irmovl instruction combinational logic generates results for addl instruction Combinational 000 %ebx = 0x300 state set according to addl instruction combinational logic starting to react to state changes 0x00e 0x00c 41 CS:APP 0x00e 42 CS:APP SEQ Operation #5 Cycle 1: Cycle 2: Cycle 3: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 < SEQ Summary Cycle 4: 0x00e: je dest # Not taken Combinational 000 %ebx = 0x300 state set according to addl instruction combinational logic generates results for je instruction 0x013 0x00e 43 CS:APP 44 CS:APP