CS:APP Chapter 4 Computer Architecture Sequential Implementation

Transcription

1 CS:APP Chapter 4 Computer Architecture Sequential Implementation Randal E. Bryant Carnegie Mellon University CS:APP

2 Y86 Instruction Set Byte ra rb ra rb V rb rb V ra D rb ra rb D D rb ra ra rb D ra rb fn ra rb Dest fn Dest Dest Dest ra ra ra ra 2 CS:APP

3 Building Blocks fun Combinational Logic Compute Boolean functions of inputs Continuously respond to input changes Operate on data and implement control A B A L U 0 MUX 1 = Storage Elements Store bits Addressable memories vala srca valb A Register file W valw dstw Non-addressable registers srcb B Clock Loaded only as clock rises Clock 3 CS:APP

4 Hardware Control Language Very simple hardware description language Can only express limited aspects of hardware operation Parts we want to explore and modify Data Types : Boolean,,, : words,,, Statements Does not specify word size---bytes, 32-bit words, 4 CS:APP

5 HCL Operations Classify by type of value returned Boolean Expressions Logic Operations,, Word Comparisons,,,,, Set Membership Word Expressions» Same as Case expressions Evaluate test expressions,,, in sequence Return word expression,,, for first successful test 5 CS:APP

6 SEQ Hardware Structure new vale, valm Write back valm State Program counter register () Condition code register (CC) Register File Memories Access same memory space Data Data memory memory Addr, Data vale Bch CC CC alua, alub Data: for reading/writing program data Instruction: for reading instructions Instruction Flow Read instruction at address specified by Process through stages Update program counter ALU ALU vala, valb srca, srcb dsta, dstb A B Register RegisterM file file E icode ifun ra, rb valc valp, Fetch Instruction Instruction memory memory increment increment 6 CS:APP

7 new SEQ Stages vale, valm Write back valm Fetch Read instruction from instruction memory Data Data memory memory Addr, Data Read program registers vale Bch CC CC alua, alub Compute value or address vala, valb Read or write data icode ifun ra, rb valc B valp, Fetch A Register RegisterM file file E Write program registers srca, srcb dsta, dstb Write Back ALU ALU Instruction Instruction memory memory increment increment Update program counter 7 CS:APP

8 Instruction Decoding Optional Optional ra rb D icode ifun ra rb valc Instruction Format Instruction byte Optional register byte Optional constant word icode:ifun ra:rb valc 8 CS:APP

9 Executing Arith./Logical Operation ra rb fn ra rb Fetch Read 2 bytes Read operand registers Perform operation Set condition codes Do nothing Write back Update register Update Increment by 2 9 CS:APP

10 Stage Computation: Arith/Log. Ops Fetch OPl ra, rb icode:ifun M 1 [] ra:rb M 1 [+1] Read instruction byte Read register byte Write back update valp +2 vala R[rA] valb R[rB] vale valb OP vala Set CC R[rB] vale valp Compute next Read operand A Read operand B Perform ALU operation Set condition code register Write back result Update Formulate instruction execution as sequence of simple steps Use same general form for all instructions 10 CS:APP

11 Executing ra D rb) ra rb D Fetch Read 6 bytes Read operand registers Compute effective address Write to memory Write back Do nothing Update Increment by 6 11 CS:APP

12 Stage Computation: Fetch ra, D(rB) icode:ifun M 1 [] ra:rb M 1 [+1] valc M 4 [+2] valp +6 vala R[rA] valb R[rB] vale valb + valc Read instruction byte Read register byte Read displacement D Compute next Read operand A Read operand B Compute effective address Write back update M 4 [vale] vala valp Write value to memory Update Use ALU for address computation 12 CS:APP

13 Executing ra ra Fetch Read 2 bytes Read stack pointer Increment stack pointer by 4 Read from old stack pointer Write back Update stack pointer Write result to register Update Increment by 2 13 CS:APP

14 Stage Computation: Fetch ra icode:ifun M 1 [] ra:rb M 1 [+1] Read instruction byte Read register byte Write back update valp +2 vala R[ ] valb R [ ] vale valb + 4 valm M 4 [vala] R[ ] vale R[rA] valm valp Compute next Read stack pointer Read stack pointer Increment stack pointer Read from stack Update stack pointer Write back result Update Use ALU to increment stack pointer Must update two registers Popped value New stack pointer 14 CS:APP

15 Executing Jumps Dest fn Dest fall thru: Not taken target: Taken Fetch Read 5 bytes Increment by 5 Do nothing Determine whether to take branch based on jump condition and condition codes Do nothing Write back Do nothing Update Set to Dest if branch taken or to incremented if not branch 15 CS:APP

16 Stage Computation: Jumps jxx Dest icode:ifun M 1 [] Read instruction byte Fetch valc M 4 [+1] valp +5 Read destination address Fall through address Write back update Bch Cond(CC,ifun) Bch? valc : valp Take branch? Update Compute both addresses Choose based on setting of condition codes and branch condition 16 CS:APP

17 Executing Dest Dest return: target: Fetch Read 5 bytes Increment by 5 Read stack pointer Decrement stack pointer by 4 Write incremented to new value of stack pointer Write back Update stack pointer Update Set to Dest 17 CS:APP

18 Stage Computation: Dest icode:ifun M 1 [] Read instruction byte Fetch Write back update valc M 4 [+1] valp +5 valb R[ ] vale valb + 4 M 4 [vale] valp R[ ] vale valc Read destination address Compute return point Read stack pointer Decrement stack pointer Write return value on stack Update stack pointer Set to destination Use ALU to decrement stack pointer Store incremented 18 CS:APP

19 Executing return: Fetch Read 1 byte Read stack pointer Increment stack pointer by 4 Read return address from old stack pointer Write back Update stack pointer Update Set to return address 19 CS:APP

20 Stage Computation: Fetch icode:ifun M 1 [] Read instruction byte Write back update vala R[ ] valb R[ ] vale valb + 4 valm M 4 [vala] R[ ] vale valm Read operand stack pointer Read operand stack pointer Increment stack pointer Read return address Update stack pointer Set to return address Use ALU to increment stack pointer Read return address from memory 20 CS:APP

21 Computation Steps Fetch Write back update icode,ifun ra,rb valc valp vala, srca valb, srcb vale Cond code valm dste dstm OPl ra, rb icode:ifun M 1 [] ra:rb M 1 [+1] valp +2 vala R[rA] valb R[rB] vale valb OP vala Set CC R[rB] vale valp Read instruction byte Read register byte [Read constant word] Compute next Read operand A Read operand B Perform ALU operation Set condition code register [ read/write] Write back ALU result [Write back memory result] Update All instructions follow same general pattern Differ in what gets computed on each step 21 CS:APP

22 Computation Steps Dest icode,ifun icode:ifun M 1 [] Read instruction byte Fetch ra,rb valc valc M 4 [+1] [Read register byte] Read constant word valp valp +5 Compute next vala, srca valb, srcb valb R[ ] [Read operand A] Read operand B vale Cond code vale valb + 4 Perform ALU operation [Set condition code reg.] Write valm dste M 4 [vale] valp R[ ] vale [ read/write] [Write back ALU result] back update dstm valc Write back memory result Update All instructions follow same general pattern Differ in what gets computed on each step 22 CS:APP

23 Computed Values Fetch icode ifun ra rb valc valp srca srcb dste dstm vala valb Instruction code Instruction function Instr. Register A Instr. Register B Instruction constant Incremented Register ID A Register ID B Destination Register E Destination Register M Register value A Register value B vale Bch ALU result Branch flag valm Value from memory 23 CS:APP

24 SEQ Hardware Key Blue boxes: predesigned hardware blocks E.g., memories, ALU Gray boxes: control logic Describe in HCL White ovals: labels for signals Thick lines: 32-bit word values Thin lines: 4-8 bit values Dotted lines: 1-bit values Fetch Bch CC icode ifun ra Mem. control ALU A Instruction memory new New rb read write vale ALU valc Data memory Addr ALU B valm data out Data valp vala increment ALU fun. valb A B M Register file E dste dstm srca srcb dste dstm srca srcb Write back 24 CS:APP

25 Fetch Logic icode ifun ra rb valc valp Instr valid Need valc Need regids increment Split Byte 0 Align Bytes 1-5 Instruction memory Predefined Blocks : Register containing Instruction memory: Read 6 bytes ( to +5) Split: Divide instruction byte into icode and ifun Align: Get fields for ra, rb, and valc 25 CS:APP

26 Fetch Logic icode ifun ra rb valc valp Instr valid Need valc Need regids increment Split Byte 0 Align Bytes 1-5 Instruction memory Control Logic Instr. Valid: Is this instruction valid? Need regids: Does this instruction have a register bytes? Need valc: Does this instruction have a constant word? 26 CS:APP

27 Fetch Control Logic ra rb ra rb V rb rb V ra D rb ra rb D D rb ra ra rb D ra rb fn ra rb Dest fn Dest Dest Dest ra ra ra ra 27 CS:APP

28 Logic Register File Read ports A, B Write ports E, M Addresses are register IDs or 8 (no access) vala valb A B M Register file E dste dstm srca srcb valm vale dste dstm srca srcb Control Logic srca, srcb: read port addresses icode ra rb dsta, dstb: write port addresses 28 CS:APP

29 A Source OPl ra, rb vala R[rA] ra, D(rB) vala R[rA] ra vala R[ ] jxx Dest Dest vala R[ ] Read operand A Read operand A Read stack pointer No operand No operand Read stack pointer 29 CS:APP

30 E Destination Write-back Write-back Write-back Write-back Write-back Write-back OPl ra, rb R[rB] vale ra, D(rB) ra R[ ] vale jxx Dest Dest R[ ] vale R[ ] vale Write back result None Update stack pointer None Update stack pointer Update stack pointer 30 CS:APP

31 Logic Units ALU CC Implements 4 required functions Generates condition code values Register with 3 condition code bits bcond Control Logic Computes branch flag Set CC: Should condition code register be loaded? ALU A: Input A to ALU ALU B: Input B to ALU ALU fun: What function should ALU compute? 31 CS:APP Bch bcond CC Set CC ALU A vale ALU ALU B icode ifun valc vala valb ALU fun.

32 ALU A Input OPl ra, rb vale valb OP vala ra, D(rB) vale valb + valc ra vale valb + 4 jxx Dest Dest vale valb + 4 Perform ALU operation Compute effective address Increment stack pointer No operation Decrement stack pointer vale valb + 4 Increment stack pointer 32 CS:APP

33 ALU Operation OPl ra, rb vale valb OP vala Perform ALU operation ra, D(rB) vale valb + valc ra vale valb + 4 jxx Dest Dest vale valb + 4 Compute effective address Increment stack pointer No operation Decrement stack pointer vale valb + 4 Increment stack pointer 33 CS:APP

34 Logic valm Reads or writes memory word Control Logic Mem. read: should word be read? Mem. write: should word be written? Mem. addr.: Select address icode Mem. read Mem. write read write Data memory Mem addr vale data out Mem data data in vala valp Mem. data.: Select data 34 CS:APP

35 Address OPl ra, rb No operation ra, D(rB) M 4 [vale] vala ra valm M 4 [vala] jxx Dest Dest M 4 [vale] valp valm M 4 [vala] Write value to memory Read from stack No operation Write return value on stack Read return address 35 CS:APP

36 Read OPl ra, rb ra, D(rB) M 4 [vale] vala ra valm M 4 [vala] jxx Dest Dest M 4 [vale] valp valm M 4 [vala] No operation Write value to memory Read from stack No operation Write return value on stack Read return address 36 CS:APP

37 Update Logic New Select next value of New icode Bch valc valm valp 37 CS:APP

38 Update update update OPl ra, rb valp ra, D(rB) valp Update Update ra update valp Update update jxx Dest Bch? valc : valp Update Dest update valc Set to destination update valm Set to return address 38 CS:APP

39 SEQ Operation State register Combinational Logic CC Read Read Ports Data memory Register file Write Write Ports Cond. Code register Data memory Register file All updated as clock rises Combinational Logic ALU Control logic reads Instruction memory Register file Data memory 39 CS:APP

40 SEQ Operation #2 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 Combinational Logic CC Read Read Ports Data memory Register file Write Write Ports state set according to second instruction combinational logic starting to react to state changes 40 CS:APP

41 SEQ Operation #3 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 Combinational Logic CC Read Read Ports Data memory Register file Write Write Ports state set according to second instruction combinational logic generates results for instruction 41 CS:APP

42 SEQ Operation #4 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 Combinational Logic CC Read Read Ports Data memory Register file Write Write Ports state set according to instruction combinational logic starting to react to state changes 42 CS:APP

43 SEQ Operation #5 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 Combinational Logic CC Read Write Data memory Read Write Ports Ports Register file state set according to instruction combinational logic generates results for instruction 43 CS:APP

44 SEQ Summary Implementation Express every instruction as series of simple steps Follow same general flow for each instruction type Assemble registers, memories, predesigned combinational blocks Connect with control logic Limitations Too slow to be practical In one cycle, must propagate through instruction memory, register file, ALU, and data memory Would need to run clock very slowly Hardware units only active for fraction of clock cycle 44 CS:APP