2. [3 marks] Show your work in the computation for the following questions involving CPI and performance.

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1 CS230 Spring 2018 Assignment 3 Due Date: Wednesday, July 11, 2017, 11:59 p.m. Weight: 7% of the course grade 1. (a) [3 marks] Write a MIPS program that takes a string as input from the user. Assume that the string ends when the program sees the period symbol (.). Assume there are only a-z and A-Z characters in the input string and a period at the end. The program then prints out the characters of the string separated by spaces. Only use the noargs frontend to test the code the code that does not work with noargs will not receive any marks. Eg. upon running the program, the program waits for user input. If the user enters HelloWorld. without the quotes, the MIPS program outputs: H e l l o W o r l d Submit the program as a MIPS file only: a3q1a.asm (b) [3 marks] Write a MIPS program that takes up to 20 integers as input from the user using the array frontend and outputs the integers in descending order of value separated by spaces. The code that does not work with the array frontend will not receive any marks. (Hint: Look at the Selection Sort example in lecture slides) For example, if the user enters integers 7, 29, 34, 1, 3 one by one using the array front end, the program outputs: Make sure you think about corner cases when writing your code. Submit the program as a MIPS file only: a3q1b.asm 2. [3 marks] Show your work in the computation for the following questions involving CPI and performance. a) [1.5 marks] Suppose you have two processors with the following specifications: Processor A runs at 2.5 GHz. Its CPI for instructions that involve memory access is twice that of instructions that do not involve memory access. Processor B runs at 3.1 GHz. Its CPI for instructions that involve memory access is thrice that of instructions that do not involve memory access. Both A and B have the same CPI for instructions that do not involve memory access. Which processor will perform better for an instruction set in which 25% of the instructions involve memory access? Show all steps involved in arriving at your answer. Solution: Using CPU Time = Instruction*CPI/Clock Rate: Suppose the instructions involving memory access was n, and the CPI for instructions that do not involve memory access is k. Then, CPU time A = (n*2k + 3n*k)/2.5 = 2nk CPU time B = (n*3k + 3n*k)/3.1 = 1.94nk So processor B has the better performance for this instruction set (or is faster).

2 b) [1.5 marks] The 5 stages of the processor have the following latencies: Fetch Decode Execute Memory Writeback a. 300ps 400ps 350ps 550ps 100ps Consider the following MIPS code: add $1, $2, $3 lw $4, 0($5) i. Non-pipelined processor: How long does the above MIPS code take to execute for a non-pipelined processor? Show your work. ii. Pipelined processor: How long does the above MIPS code take to execute for a pipelined processor? Show your work. Solutions: 1. ( )*2 = 3400ps [0.5 marks] *5+550 = 3300ps [0.5 for taking the largest value 550 as the cycle time. And 0.5 for calculating the answer correctly] However, you may assume that the add instruction does not require the memory access step and in that situation, the answer for part 2 will be: 550*4+550 = 2750ps, which is also correct given the assumption.

3 3. [5 marks] addi $4,$4,7 IF ID lw $8,0($4) IF ID add $7,$8,$7 IF ID lw $9,0($2) IF ID mult $8,$9 IF ID mflo $8 IF ID bne $7,$0,L1 IF ID add $2, $5, $5 IF ID jr $31 IF ID L1:sw $8,0($3) Stall IF ID For the above pipelined execution: (a) [1 mark] Explain where a control hazard may occur. By looking at the pipelining sequences, explain how the control hazard is being minimized. In that context, also explain the position of the IF step for the instruction labeled L1. The control hazard occurs when the branching instruction takes place and the program does not know which instruction to fetch. Control Hazard is minimized above by fetching the next instruction assuming that the branch is not taken. If the branch is indeed taken, then the branching instruction will compute results early in ID stage and fetch L1, which would mean that L1 will be fetched after the ID stage of bne, thus introducing a Stall.

4 (b) [2 marks] The in the 3 rd instruction indicates a Data Hazard pertaining to register $8 in the ID step. Similarly indicate other places in the pipelined execution above where a data hazard may occur. Assume that there is no forwarding/bypassing and therefore all data hazards have to be listed. (The best way to do this would be to submit a pdf containing a table with D $x in the appropriate places) Solution addi $4,$4,7 IF ID lw $8,0($4) IF ID D $4 add $7,$8,$7 IF ID lw $9,0($2) IF ID mult $8,$9 IF ID D $9 mflo $8 IF ID bne $7,$0,L1 IF ID add $2, $5, $5 IF ID jr $31 IF ID L1:sw $8,0($3) Stall IF ID The hazard occurs because $8 may not be written before it is read in L1.

5 (c) [2 marks] Now look at a modified pipelined execution of the same program below which solves the data hazards from above. For example,, in the third instruction is solved by adding one stall/bubble to the third instruction and forwarding () the output of MEM in the second instruction to the input of EX in the third instruction as indicated by the line. Similarly indicate the fixes for the other data hazards that you identified in Step (b). Note that some data hazards may only involve Forwarding without any Stall. (Again, the best way to do this would be to submit a pdf containing a table with the s, the connecting lines, and the Stalls in the appropriate places) Solution: addi $4,$4,7 IF ID EX MEM WB lw $8,0($4) IF ID EX MEM WB add $7,$8,$7 Stall IF ID lw $9,0($2) IF ID EX MEM WB mult $8,$9 Stall IF ID mflo $8 IF ID bne $7,$0,L1 IF ID add $2, $5, $5 IF ID jr $31 IF ID L1:sw $8,0($3) Stall IF ID The last indicates that the value of $8 needs to be written in WB before it is read in ID in L1.