4. What is the average CPI of a 1.4 GHz machine that executes 12.5 million instructions in 12 seconds?

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1 Chapter 4: Assessing and Understanding Performance 1. Define response (execution) time. 2. Define throughput. 3. Describe why using the clock rate of a processor is a bad way to measure performance. Provide a concrete example using the performance equation to back up your assertion. 4. What is the average CPI of a 1.4 GHz machine that executes 12.5 million instructions in 12 seconds? 5. What is the CPI of a program execution that consists of the following instruction types (classes) and CPI: Instruction class CPI Percentage A % B % C 2 5% 6. Suppose one machine, A, executes a program with an average CPI of 1.9. Suppose another machine, B (with the same instruction set and an enhanced compiler), executes the same program with 20% less instructions and with a CPI of 1.1 at 800MHz. In order for the two machines to have the same performance, what does the clock rate of the first machine need to be? 7. Use Amdahl s Law to compute the new execution time for an architecture that previously required 20 seconds to execute a program, where 20% of the instructions executed were load/stores, if the time required for a load/store operation is reduced by 30% (amount of improvement for load/stores = 1/.70 = 1.44). 8. What s the best way to measure performance of a machine? Clock rate, CPI, MIPS, FLOPS (floating-point operations per second), memory latency, or average execution time? Why?

2 9. This problem compares the performance of the single-cycle MIPS architecture, the multi-cycle MIPS architecture, and the pipelined MIPS architecture. Assume it requires 10 ns to perform any of the following operations: main memory access, register file access, and arithmetic operation. Assume the delay for multiplexors, registers (i.e. setup/hold time), and lookup tables is negligible. a. What is the minimum clock period and frequency for each of the three implementations? b. What is the CPI for each of the implementations, assuming a program execution with the following instruction mix: Execution Instruction Frequency r-type arithmetic, logical, comparison 60% branch 15% load 15% store 5% jump 5% Assume the pipelined CPU performs forwarding, that the compiler schedules the code to contain no load hazards, branches have a fixed 3-cycle latency (requires 2 trailing no-ops), and you may disregard the time required to fill the pipeline. c. Assume the program from part b executed 10 million instructions. What is the speedup of the pipelined processor versus both the single-cycle processor and the multi-cycle processor? Chapter 5: The Processor: Datapath and Control 1. Describe the differences between single-cycle and multi-cycle processor architectures. 2. Describe in detail everything that is needed in order to add the addi, subi, andi, and ori instructions to the processor design above. 3. Design a datapath for the R-type sll, sra, and srl instructions. Don t worry about control signals. 4. For a multicycle processor design, describe what steps of the instruction execution are performed in each clock cycle for a load instruction (Hint: there are 5 clock cycles).

3 5. Provide all control signals for a LW instruction using the following processor design. Assume ALUOp is 10 for interpretation of instruction function code, 00 for add, and 01 for subtract. RegDst Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite 6. Describe briefly why the MIPS designers use a separate ALU controller rather than centralize all control in the main control unit?

4 7. Draw the design of a simple datapath that multiplies the contents of register A by 3 and latches the value into another register B. This datapath can be represented by the following RTL: B <- (A) * 3 You are provided with a library of the following components: register a combinational logic block named shift-left by one, that provides an output whose value is the input value shifted to the left by one bit adder Assume these components may be scaled to any arbitrary bit width, so you may abstract away the size of each of the signals. Chapter 6: Enhancing Performance with Pipelining 1. List and describe the pipeline hazards. 2. For the following segment of code, indicate all data dependences for the 5-stage MIPS pipeline, and show the state of the pipeline for each cycle. Assume a fixed 3-cycle branch latency. add $6,$5,$2 lw $7,0($6) addi $7,$7,10 add $6,$4,$2 sw $7,0($6) addi $2,$2,4 blt $2,$3,loop add $6,$5,$2 3. Describe the disadvantage of moving branch resolution to the decode stage, thus reducing branch latency (mis-prediction penalty). 4. Describe a reason why a 2-bit branch predictor can be more effective than a 1-bit branch predictor. 5. Describe why predicting a branch taken still incurs at least one cycle penalty? 6. Assume an architecture has a branch predictor that correctly predicts a branch 60% of the time. A correctly predicted branch requires a 1 cycle latency (2 cycles in total), and a mis-predicted branch requires a 3 cycle latency (4 cycles in total). Suppose a program requires 100 seconds to run, and 30 seconds are spent executing branches. If you enhance the design of the branch predictor such that it correctly predicts branches 90% of the time, what is the new execution time? 7. For the following segment of code, show the RAW data dependences for the five-state MIPS pipeline. add $2, $3, $4 sub $3, $2, $4 slt $4, $3, $2 sw $3, 0($2)

5 8. Assume the following instructions are in the following pipeline stages: add $2, $3, $4 or $2, $5, $6 sub $4, $2, $7 in WB in MEM in EXECUTE Show or describe which forwarding paths are currently in use. 9. For the following program: main: addi $2, $0, 0 loop: lw $3, vals($2) addi $2, $2, 4 beqz $3, done j loop done: addi $2, $2, -4 sra $3, $2, 2 jr $31 Assume we want to run this program on an architecture that has a branch delay slot. How must we modify the code such that it behaves exactly as it would on a machine without a branch delay slot, without introducing any additional pipeline stalls resulting from the new instruction ordering?