Co-Simulation of Hybrid SDL and VHDL Specifications

Transcription

1 Co-Simulation of Hybrid SDL and VHDL Specifications Maciej Wasowski, Dorota Witaszek, Joachim Fischer, Eckhardt Holz, Stefanie Lau, Olaf Kath Humboldt-University of Berlin - Department of Computer Science Unter den Linden 6, Berlin wasowski@informatik.hu-berlin.de, witaszek@informatik.hu-berlin.de Abstract The co-simulation is the chosen method within the ESPRIT Project INSYDE for the validation of hybrid SDL and VHDL specifications. This paper presents a concept for the integrated SDL and VHDL simulator and its realization in C++. The INSYDE concept for the co-simulation is based on the connection of two existing commercial simulators by the Coupling Module. The Integrated Simulator presented in this document aims at studying the functionality of this Coupling Module and the general principles of co-simulation. 1 INTRODUCTION In the past years methods for the design of hybrid hardware/software systems have been searched for and investigated intensively. The development of such a method is the main objective of the INSYDE project. Stages in the INSYDE methodology are analysis, system design, detailed design and validation [5]. OMT is chosen as the analysis notation technique. The languages for the detailed design are SDL and VHDL. The method chosen for the validation of hybrid SDL and VHDL specifications is the Co-Simulation. In the following, SDL, VHDL and the SDL/VHDL Co-Simulation as a validation technique, are briefly presented (the detailed presentation is given in [5]. The formal specification language SDL is an international standard language, which was developed by the CCITT for the description of complex distributed communication systems [2]. By means of SDL it is possible to describe both the structure of a system and the system behaviour on different abstraction levels. The behaviour description is based on the concept of extended finite state machines communicating asynchronously by message exchange. The data description concepts of SDL base on algebraic data types. SDL'92 [3] is an objectoriented extension of SDL. The new facilities of SDL'92 result from a strict distinction between types (classes) and instances (objects). VHDL (Very High Speed Integrated Circuit Hardware Description Language) is technique for the design and the description of hardware systems [7]. In December 1987 VHDL formally became the IEEE (Institute of Electrical and Electronic Engineers) standard hardware description language (IEEE-STD-1076). VHDL was consciously based on the ADA language. Many features, such as the use of packages, basic syntax, etc. were taken from ADA. The language supports hierarchical description of hardware from system to gate Co-Simulation of Hybrid SDL and VHDL Specifications 1 of 11

2 or even switch level. 1.1 Purposes of the Validation of Hybrid SDL and VHDL Specifications Two aspects have to be investigated by the validation: validation of the self-consistency of the specification (e.g. absence of deadlocks, stability in error cases) validation of consistency with other specifications (on other stages of the development process or w.r.t. requirements or environment specifications) The validation of a system specification/description comprises two stages, the check of syntactical and semantical correctness and the proof that the specification fulfils the requirements which are imposed on the system. In the scope of SDL and VHDL there are two main approaches implemented in tools: Specification Execution (Prototyping, Next-Event-Simulation, etc.) State-Space-Exploration (Proof checker, Petri-Net-Analyser, etc.) The State-Space-Exploration is an exhaustive method, i.e. all possible situations which may occur during any execution of the specification will be considered. The specification execution on the other side is a non-exhaustive method. It will select only some (usually typical and important) situations and will verify that the specified behaviour is indeed the intended behaviour. Although the non-exhaustiveness is a major drawback of the simulation, this method is the only one which can be applied to real life specifications. All techniques based on a statespace exploration suffer from the state explosion problem. The capacities needed for the application of such a method are so large that they exceed the capabilities of the computer systems. 1.2 Approaches for the Validation of hybrid VHDL and SDL Specifications The following three techniques for a validation of hybrid SDL/VHDL specifications were investigated in the INSYDE project ([4]): Translation Approach:Transformation of the hybrid specification into a homogeneous specification using only one specification language i.e. translation of the SDL parts to VHDL or translation of the VHDL parts to SDL. Single Base Approach: Use of dedicated simulators for each language basing on a common underlying simulation systems. A single simulator or a physical distributed simulator are possible. Heterogeneous Approach: Use of two specialized off-the-shelf simulators, which cooperate for the simulation of the whole specification and communicate through a special interface. In the INSYDE Methodology the validation phase is realized by a co-simulation of the hybrid system specification (Heterogeneous Approach): An SDL simulator (GEODE) and a VHDL simulator (an component of the Mentor Graphics toolset) are used to simulate the SDL and VHDL part of the system specification. Both simulators are connected by a special Coupling Module. The Integrated Simulator (Single Base Approach) is an experimental variant, which aims at studying the functionality of this Coupling Module and the general principles of co-simulation Co-Simulation of Hybrid SDL and VHDL Specifications 2 of 11

3 2 REQUIREMENTS ON A SDL/VHDL CO-SIMULATION In the following the problems, which have to be solved in order to realize the cosimulation of hybrid SDL/VHDL specifications are considered. These problems are related to the general problems of the simulator s coupling and to the semantical divergence between both languages. Location of Coupling Module The special Coupling Module is required for the connection between the SDL parts and the VHDL parts of the system specification. One must decide: which language structures should be connected by the Coupling Module. The possible solutions are e.g.: SDL process with VHDL process or SDL block with VHDL entity. whether one central Coupling Module for the whole hybrid specification, or one Coupling Module for each pair of SDL and VHDL structures which communicate with each other should exist. Information Exchange SDL as well as VHDL use the term signal to denote information carriers. However the signal concept as well as the data type concept are different in each language. The SDL signals can be seen as messages that are exchanged between processes. The VHDL signals have hardware significance and are more static wires between hardware components rather than dynamical messages. The SDL concept of abstract data types (ACT ONE) is open, i.e. each data type has an interface part (a signature), which defines which literals and operators can be used for this data type and how to use them, and a behaviour part, that defines the semantics of the operators and literals. Furthermore, the user can specify new abstract data types using another data type specification technique such as ASN.1. VHDL does not support concepts of abstract data types. There are four groups of data types in VHDL: scalar types, composite types (arrays, records), access types (pointers) and file types. In order to make the exchange of information possible between SDL and VHDL parts of the hybrid specification, the method has to be defined so that it provides: the semantical transformation of SDL signals into VHDL signals (and vice versa), and the transformation of information carried by the SDL signals (i.e. the SDL data types) into VHDL data types (and vice versa). Synchronization Mechanisms In SDL the communication is realized by signal exchange that is asynchronous in comparison to VHDL where the signal exchange is synchronous. Therefore, an algorithm for the signal exchange between SDL and VHDL parts has to be defined. The next problem to be solved is the progress of the simulation time. In VHDL the time model is an internal one, as compared to SDL, where the time model is external. The SDL time semantics allows for different (semantically correct) realizations of the time progress. In order to make the co-simulation possible, the common time progress model has to be defined so that it does not contradict either the SDL nor the VHDL time semantics. Specification Requirements In SDL time can only be accessed by the predefined expression NOW, e.g. by setting of timers. The delay time of a signal transmission is arbitrary. For each value, that represents Co-Simulation of Hybrid SDL and VHDL Specifications 3 of 11

4 time in SDL expressions, it has to be declared, what time unit will be used for this value. The signal assignments in VHDL can be specified with any delay. The unit of time is Nunoseconds. The consumption of time has to be introduced into the SDL part during the simulation in order to make the activation of VHDL components possible. The time consumption can be introduced for the transport of signals by channels and/or execution of transitions. 3 The Integrated SDL and VHDL Simulation The co-simulation has to be considered at two levels - the language level and the simulator level (cf. Fig 1). The language level comprises an SDL specification part and a VHDL specification part both with additional definitions (replacement units). A replacement unit expresses in a very abstract way the existence of the VHDL (SDL) part in the SDL (VHDL) specification in form of an interface description. At the language level the signal exchange between both parts is described abstractly. The simulator level describes the implementation concepts, i.e. the connection between the VHDL signals defined in the replacement unit of the SDL part and the SDL signals defined in the replacement unit of the VHDL part as well as the realization of the synchronization of the simulators. Introducing replacement units at the language level allows the separate simulation and verification of the SDL and VHDL part. If the interface between both parts is not modified the separate development and refinement of one part does not influence the other part. SDL Part Replacement Block for the VHDL Part Replacement entity for the SDL Part VHDL Part Language Level SDL Part Coupling Module VHDL Part Simulator Level Coupling Library FIGURE 1. The Architecture of a Hybrid SDL and VHDL Specification on the Language and Simulator Level Moreover, the resulting specifications do not depend on the realization of the co-simulation. 3.1 The Language Level In the INSYDE Methodology the whole hybrid specification as well as the replacement units are semi-automatically generated from the OMT system description [4][5]. At the language level the signal exchange between the SDL part and the VHDL part is specified abstractly, i.e. it is considered which signals are exchanged, but it is not important, how they Co-Simulation of Hybrid SDL and VHDL Specifications 4 of 11

5 are sent/received. The semantics of signal exchange between SDL and VHDL part are defined at the simulator level. The SDL part and the VHDL part can be considered as separate specifications. For that reason at the language level in each specification appears a replacement unit which abstractly models that part of the system which is specified in the respective other language (SDL or VHDL). The following paragraphs give an overview of the approach of modelling the replacement units for the hybrid specification, that is presented in Fig 2. SDLs1 VHDLs1 SDL SDLsk SDLr1 Coupling Module VHDLsk VHDLr1 VHDL SDLrk VHDLrk FIGURE 2. An Example of the Signal Exchange between SDL and VHDL part Modelling the VHDL part in SDL. In the SDL specification the VHDL part is modelled by one block (cf. Fig. 3) with two local processes: the process to_vhdl (cf. Fig. 4), which abstractly models the receiving of signals from the SDL part and the sending of signals to the VHDL part, and the process from_vhdl (cf. Fig. 4), which abstractly models the receiving of signals from the VHDL part and the sending of signals to the SDL part. Block Replacement Module remote VARs1 TYPEs1 nodelay,...,varsk TYPEsk nodelay, VARr1 TYPEr1 nodelay,...,varr2 TYPErk nodelay SDLs1,...,SDLsk to_vhdl(1,1) SDLr1,...SDLrk from_vhdl(1,1) FIGURE 3. The Specification in SDL of the Block Representing the VHDL Part It is assumed, that all signals, which the SDL part sends to this block, should be sent to the VHDL part. Both processes work concurrently. From the SDL point of view the VHDL signals can be seen as exported variables. The block contains variables corresponding to all signals sent to the VHDL part and to all signals, which can be received from the VHDL part. Co-Simulation of Hybrid SDL and VHDL Specifications 5 of 11

6 These variables are defined as remote nodelay variables (exported and imported) to express, that they represent something outside the SDL part, available without any delay. The assignment of a new value to a VHDL signal is represented by the assignment of the new value to the corresponding SDL variable and the export of this new value. Process to_vhdl; dcl exported VARr1 TYPEr1,..., VARrk TYPErk; dcl exported VARs1 TYPEs1,...,VARsk TYPEsk; start; state wait; input SDLs1(VARs1); export(vars1);... input SDLsk(VARsk); export(varsk); stop; Process from_vhdl; dcl imported VARr1 TYPEr1,...,VARrk TYPErk; dcl old_varr1 TYPEr1,... old_varrk TYPErk; dcl imported VARs1 TYPEs1,..., VARsk TYPEsk; start; task old_varr1:= import(varr1);... task old_varrk:= import(varrk); state wait; provided old_varr1 /= import(varr1); task old_varr1:= import(varr1); output SDLr1(old_VARr1);.. ṗrovided old_varrk /= import(varrk); task old_varrk:= import(varrk); output SDLrk(old_VARrk); stop; FIGURE 4. The Specification in SDL of the Processes within the Block Representing the VHDL Part Modelling the SDL part in VHDL. In the VHDL specification the SDL part is represented by one entity with an architecture containing concurrent signal assignments, which write/read the VHDL signals connected to the SDL specification (cf. Fig. 5). It is assumed, that all signals, sent by the VHDL part to this entity, shall be sent to the SDL part. The port of the entity contains the VHDL signals, which the VHDL part sends to the SDL part (in-signals), and VHDL signals, which the VHDL part receives from the SDL part (out-signals). The SDL signals are represented by local VHDL signals in the architecture of the entity (to express that they represent something from outside the VHDL part): For each SDL signal, which can be sent/received to/from the SDL part, a local VHDL signal in the architecture of the entity is declared. entity replacementofsdl is port ( VHDLs1: out T1; VHDLsk: out T2; VHDLr1: in T3; VHDLrk: in T4 ) end replacementofsdl; architecture behav of replacementofsdl is signal locs1: T5; signal locsk: T6; signal locr1: T7; signal locrk: T8; begin -- concurrent signal assignments VHDLs1 <= locs1; VHDLsk <= locsk; locr1 <= VHDLr1; locrk <= VHDLrk; end behav; FIGURE 5. The Specification in VHDL of the Entity Representing the SDL Part The reception of VHDL signals and their sending to the SDL part are represented by concurrent signal assignments. The target of such an assignment is a local VHDL signal representing the SDL signal, the expression is the corresponding in-signal in the port of the Co-Simulation of Hybrid SDL and VHDL Specifications 6 of 11

7 entity. Similarly, the reception of SDL signals and their sending to the VHDL part are represented in VHDL by concurrent signal assignments. The target of such an assignment is the outsignal in the port of the entity, the expression is the local VHDL signal representing the SDL signal. All the signal assignments are specified with delta delay. 3.2 Simulator Level The concept for the Integrated SDL/VHDL simulator derives from the Single Base Approach, introduced in [4], where a common basic simulation system is proposed, supporting the simulation of VHDL as well as of SDL specifications. The implementation of a simulation system in a programming language, requires an appropriate process management realized in this language. For that reason ODEM (Object Oriented Discrete Event Modelling [1]) has been used as underlying Basic Simulation System. ODEM can be used for quasi-parallel execution of programs described as a set of parallel processes. It provides a simulation clock modul as well as a scheduler. For the simulation of SDL 92 specifications an SDL Runtime system was developed [6]. In order to simulate the VHDL specifications a separate VHDL Runtime System was implemented. Both Systems base on ODEM and can be used as separate Simulators. The Integrated Simulation System for SDL and VHDL is implemented in C++ and consist of the SDL Runtime System, the VHDL Runtime System, and a Coupling Module (cf. Fig. 6) and provides: models for all SDL and VHDL constructs with their structure and behaviour, and models for the communication between SDL and VHDL parts. VHDL Runtime Library ODEM Coupling Module SDL Runtime Library The Central List of Active System Components VHDL Process t 1 SDL Process t 2 SDL Timer t 3 VHDL Process t 4 FIGURE 6. The Architecture of the Integrated SDL and VHDL Simulation System The simulation method will be characterized by a pseudo-parallel execution of active system components: SDL processes, SDL channels, SDL timers, VHDL processes, and VHDL signals. The global clock module will be used for the synchronization of the time progress by the different components The SDL Runtime System The SDL Runtime Library supports all constructs of SDL [6]. Most of the corresponding C++ types are derived from basic types defined in the process library ODEM. Thus the Co-Simulation of Hybrid SDL and VHDL Specifications 7 of 11

8 simulation of a SDL specification can be executed in the simulated-time-mode and base on the discrete process oriented next event simulation technique. The active objects in SDL are processes, channels and timers. The SDLprocess class is a subclass of the ODEM-class process and defines a general behaviour of an process of SDL. The SDLprocess class is a base class for all classes representing specified SDL processes. Specific behaviour - a state-transition-graph of a SDL process is coded in derivations of the SDLprocess class in a redefined virtual function. Classes for SDL timers and channels are defined as derivations of the ODEM-class timer The VHDL Runtime System The VHDL Runtime System contains the structures/classes, which are the foundation for different VHDL structures and handles the execution of the VHDL behaviour in simulation time. Most of the correspondind C++ types are derived from basic types defined in the process library ODEM. The following C++ classes are base classes for VHDL structures: Class entity for entities (classes for architectures are derivated from the corresponding entity classes) Class VHDL_process for processes; VHDL_Process is derived from the ODEM class process; Classes which represent VHDL processes are containers of corresponding classes for architectures. Class Signal for signals (base class of signal is the ODEM class timer) The Coupling Module The Coupling Module realizes the cooperation between the SDL part and the VHDL part of the system. For that reason it contains two interfaces: one to the SDL part, and one to the VHDL part. The SDL interface is an C++ structure which represents an SDL block; the VHDL interface is a C++ structure which represents a VHDL entity (cf. Fig. 7). SDL block VHDL entity Data type Transformation Synchronisation process SDL gates VHDL port FIGURE 7. The Architecture of the Coupling Module The Coupling Module is responsible for: the connection between SDL and VHDL part, the exchange of information between SDL and VHDL part (including the transformation of data types), and the synchronization between SDL and VHDL part. Co-Simulation of Hybrid SDL and VHDL Specifications 8 of 11

9 Connection between SDL and VHDL part The connection of SDL and VHDL part is a realisation of signal connections defined in the replacement units. Information Exchange The information exchange between both languages is realized by the exchange of signals between an SDL block and a VHDL entity. Discrete SDL signals, which are sent sequentially, have to be constructed from continuous VHDL signals, which are sent simultaneously, and vice versa. For all signal types, which can be transformed automatically from one language into the other, the appropriate transformation function will be defined. For other signal types the designer can define such a transformation (cf. Fig. 8). Set SDL data types Integer Time DataType Predefined transformation functions VHDL data types Time Integer Record User-defined transformation functions FIGURE 8. The Representation of Data Types in C++ for SDL and VHDL. Synchronization Since the VHDL specification represents hardware parts of the system which work faster than the software parts described in SDL, at any point of the simulation time first the VHDL parts are activated (i.e. VHDL active statements are executed). After the VHDL simulation cycle has been completed i.e. the VHDL signals get stable state, they can be delivered to the SDL part. The SDL part always has to wait until the VHDL part has been executed. All signals, that appear in the Coupling Module from the SDL part, are immediately sent to the VHDL part, and vice versa, i.e. the signals are passed without any time delay. 4 An Example for the Hybrid SDL and VHDL Specification In this paragraph a small example for a hybrid SDL and VHDL specification and its cosimulation is presented. 4.1 Description The VHDL-part is fulladder which works on the bit-level (cf. Fig. 9). It is specified as an entity with corresponding architecture. This architecture contains three components (two halfadder and an or-gate) which are specified also as entities with corresponding Co-Simulation of Hybrid SDL and VHDL Specifications 9 of 11

10 architecture. A B Halfadder U0 Temp_sum Carry Halfadder U1 Temp_carry_2 A+B Temp_carry_1 Orgate U2 Carry_out FIGURE 9. The Structure of the Fulladder The SDL-part comprises two SDL-blocks (cf. Fig. 10). Each of them contains one SDL process. The SDL process SDL-proc1 sends signals A, B, and Carry to the entity fulladder. After the sending of these signals the process waits until the signal add_ok from the SDLproc2 is received. Then the SDL-proc1 starts again. The SDL process SDL-proc2 in the block SDL-block-2 waits for the signals A+B and Carry-out which are sent by the entity fulladder. Then it sends the signal add_ok to the SDL-process SDL-proc1 in the first SDLblock. SDL-block-1 Coupling Module SDL-proc1 A B Carry to-vhdl A B VHDL-processes A B add_ok Carry Carry fulladder SDL-block-2 SDL-proc2 A+B Carry_out from-vhdl A+B Carry_out A+B Carry_out SDL-Block VHDL-entity SDL-blocks Containerclass, including an SDL-Blocks VHDL-entity and a VHDL-entity SDL-signals VHDL-signals FIGURE 10. An Example of Hybrid SDL and VHDL Specification 5 Conclusions The Single Base Approach as an experimental variant for the SDL and VHDL co-simulation aims at studying the functionality of the Coupling Module and the general principles of co-simulation. Since the SDL and VHDL Runtime Systems which are developed at the Humboldt University are used for this purpose, the complete C++ code of both Systems is accessible and their interfaces can be used to implement the Coupling Module. In this case the whole implementation can be tested with C++ development tools as debugger etc. Moreover, most commercial simulators do not provide the possibility of accessing the internal simulation clock. Co-Simulation of Hybrid SDL and VHDL Specifications 10 of 11

11 The coupling of the SDL simulator GEODE, and a VHDL simulator which is an component of the Mentor Graphics toolset, required the consideration of additional aspects related to the distributed simulations. However, the co-simulation s principles as signal exchange and synchronisation, which are investigated and implemented in the Single Base Approach can be used. The theoretical problems for the co-simulation have already been solved. Currently the implementation and examples are tested. Acknowledgements This work was supported by the European Community within the ESPRIT III Project 8641 INSYDE. We want to thank our project partners, especially Jean-Philippe Delpiroux and Nicolas Dervaux, for their helpful discussions and contributions. References [1] K. Ahrens, J. Fischer, D. Witaszek: Object-oriented simulation of processes in C++ (in german). Informatik-Preprint of the Humboldt-University Berlin, [2] CCITT: CCITT Specification and Description Language SDL, Recommendation Z.100 (Blue Book). Genf [3] CCITT: CCITT Specification and Description Language SDL, Recommendation Z.100 (SDL 92). Genf [4] E. Holz, D. Witaszek, M. Wasowski, S.Lau, J. Fischer, P. Roques, L. Cuypers, V. Mariatos, N. Kyrloglou: INSYDE Deliverable D1.1: Technology Assessment. ESPRIT P8641 Report, [5] E. Holz, D. Witaszek, M. Wasowski, S.Lau, J. Fischer, P. Roques, L. Cuypers, V. Mariatos, N. Kyrloglou, J. Heirbaut, K. Verschaeve, V. Jonckers: INSYDE Deliverable D1.1: Ad - Hoc Document. ESPRIT P8641 Report, [6] J. Fischer, E. Holz, M. v. Löwis, D. Witaszek: A Run Time Library for the Simulation of SDL 92 - Specifications. Proceedings of the Sixth SDL Forum Darmstadt, Germany, October, [7] IEEE: IEEE Standard VHDL Language Reference Manual. IEEE standard [8] Z. Navabi: VHDL Analysis and Modeling of Digital Systems. McGraw-Hill, Inc., Co-Simulation of Hybrid SDL and VHDL Specifications 11 of 11