Hardware/Software Co-design

Transcription

1 Hardware/Software Co-design Zebo Peng, Department of Computer and Information Science (IDA) Linköping University Course page: 1 of 52

2 Lecture 1/2: Outline : an Introduction Course Content Schedule, Organization, etc. 2 of 52

3 : the Goal Computer aided hardware/software engineering of embedded systems Produce heterogeneous (hardware/software) systems which meet certain system-level objectives. Reduce system development time. 3 of 52

4 Topics of the Early Days Implementation independent specification and modeling Hardware/Software partitioning Concurrent design refinement of hardware and software components: coordination consistency control Cosimulation, Coverification 4 of 52

5 Traditional Design Flow Informal Specification, Requirements Software model Hardware model Scheduling, Software Generation Testing Hardware Synthesis Software blocks Communication Synthesis Hardware blocks Prototyping Product Fabrication 5 of 52

6 Hw/Sw Co-Design Flow System specification Hardw/Softw Partitioning Partitioned model Scheduling Part. model, Schedule Communication Synthesis Hardw./Softw. Cosimulation System Level Software model Hardw./Softw. Cosimulation Hardware model Software Generation Software blocks Hardw./Softw. Cosimulation Emulation, Prototyping Hardware Synthesis Hardware blocks Lower Levels Product Fabrication 6 of 52

7 A Typical Target Architecture - The Early Days µprocessor Hardware Accelerator Memory Specification: a simple program Main goal: software acceleration Architecture is simple Main issues Hardw./Softw. partitioning Communication Synthesis Cosimulation 7 of 52

8 Particularly Interesting: Reconfigurable Systems Programmable Hardware Circuits: They implement arbitrary combinational or sequential circuits and can be configured by loading a local memory that determines the interconnection among logic blocks. Reconfiguration can be applied an unlimited number of times. Main applications: Software acceleration Prototyping 8 of 52

9 Temporal&Spacial Partitioning at t 3 at t 4 at t 1 at t 2 µprocessor FPGA Accelerator temporally partitioned Memory 9 of 52

10 Reconfigurable Processors System on Chip with dynamically reconfigurable datapath C code On chip mem. CPU Reconfigurable datapath Profiling & Kernel extraction Kernels Hw/Sw partitioning Datapath synthesis C code 10 of 52

11 It Can Be more Complicated Applications are heterogeneous and complex; specifications as well. Not only! Specification: a simple program Main goal: acceleration Architecture is simple Architecture is very complex! 11 of 52

12 Distributed Embedded System (Automotive Application) Actuators Sensors Input/Output FPGA RAM TASKS CPU FLASH OS CACHE Network Interf. Gateway Gateway 12 of 52

13 System on Chip (Telecommunication Component) application program & I/O drivers set of tasks & real-time kernel RF A/D & D/A DSP core RAM RISC core RAM High-Speed DSP Blocks Control Logic Interface LAN 13 of 52

14 The Typical Embedded Application Applications are heterogeneous: hardware and software components are mixed; in both hardware and software:control dominated and dataflow components; digital and analog components interact. Specifications are multi-language/multi-model. Target architectures are complex (often distributed). 14 of 52

15 Design Constraints/Requirements Legacy hardware/software Time constraints Quality of service Fault tolerance Cost Power consumption Flexibility Time to Market of 52

16 System Design Flow Informal Specification, Constraints System Level Arch. Selection System architecture Estimation not OK Modeling System model Mapping Scheduling Mapped and scheduled model OK not OK Functional Formal Verification Formal Verification Softw. model Hardw. model Softw. Generation Hardw. Synthesis Lower Levels Softw. blocks not OK Testing OK Prototype Hardw. blocks Fabrication 16 of 52

17 System Design (cont d) Given a certain application, perform design space exploration and find an efficient implementation in terms of underlying architecture and the software running on it. Hw/Sw codesign design of embedded systems. 17 of 52

18 Some Issues Distributed Systems & System on chip Processor design & Reconfigurable systems Compiling (software synthesis) Low power IP-based design (reuse) System specification Formal methods Verification and testing Real-time Systems 18 of 52

19 Distributed Real-Time Systems Classical real-time research Covers only a limited part of the design flow Assumptions are often unrealistic Task models are too simple The underlying architecture is assumed fixed and is not considered as part of the global design/optimization problem; The same for the communication infrastructure. Emphasis on the worst case of 52

20 System on Chip Analog and digital on the same chip µprocessor Cache DMA Memory Interconnection Network Problems related to interconnections are becoming dominant. Timing closure. Bus-based architectures will be AD/DA Reconfigurable logic Peripheral replaced by networks on chip. Customized cashes and memories. Testability! of 52

21 Processor Design Partitioning across the horizontal line, as opposed to... see next slide Profiling, Analysis Software Hardware (ASIP) Instruction set A main issue: compilers and programming environments! 21 of 52

22 Processor Design (cont d) Partitioning across the vertical line Partitioning &mapping Software (µprocessor) Software (µprocessor) Software (µprocessor) Hardware (ASIC) Hardware (ASIC) 22 of 52

23 Parameterized Platforms Application development (on ref. chip) µprocessor Cache DMA Memory Bridge Detailed structural model System bus Peripheral bus Reconfigurable logic Peripheral Parameter optimization (sim. & estim.) New System generation Product 23 of 52

24 Software Synthesis What makes software synthesis for embedded systems different? The need of highly optimized code in order to make use of the particular features of the underlying architecture. Large compilation times can be tolerated. Time constraints have to be considered during compilation. Scheduling aspects: at instruction level; at task level. The need of performant easy-to-use retargetable compilers. 24 of 52

25 Software Synthesis (cont d) What makes it a Hardware/Software problem? The hardware support has to be considered during software generation. Efficient retargetable compilers are important tools for concurrent development of software and of the underlying hardware (for example ASIPs). Hardware Specification is an important aspect of retargetable compiling. 25 of 52

26 Low Power order of magnitude order of magnitude energy consumed high med. low GP proc. ASIP FPGA ASIC Trade-offs: flexibility, power, performance, time to market. There is an obvious trend towards software implementation. Because of power/performance, part of the functionality is implemented with ASIC/FPGA/ASIP. This makes the difference! low med. high flexibility 26 of 52

27 Low Power (cont d) Power optimization at circuit and gate level Power optimization at system level Dynamic power management - shutdown of idle resources - variable supply voltage Mapping and scheduling with power optimization Code generation for low power Customized cache memory (to reduce memory access and bus traffic) Information encoding 27 of 52

28 Reuse - IP Based Design IP based design is the process of composing a new system design by reusing existing components. Problem: How to specify an existing core for the reuse library? functionality timing interface properties power consumption,... Some essential design issues in this context: specification, simulation, estimation, exploration integration (interfaces) verification, testing 28 of 52

29 System requirements Hardware model Preliminary specification Executable model Functional test (refine model) DESIGN SPACE EXPLORATION Architecture & mapping Define interfaces Hardw./Softw. Cosimulation Arch. selection Partitioning Scheduling Estimation Component library (hardware/software cores) Software model Specify -new blocks- Instantiate -lib. blocks- Develop -new modules- Instantiate -lib. modules- Block level synthesis& verification Hardware blocks Hardw./Softw. Cosimulation Emulation& Prototyping Product Fabrication Block level synthesis& verification Software modules 29 of 52

30 Reuse - IP Based Design (cont d) Interface (Communication) - Based Design Interfaces Design Behaviours 30 of 52

31 Specification/Modeling/Verification Embedded systems are inherently heterogeneous Specification imperative FSMs dataflow discrete event Refinement partitioning compiling softw. synth HLS LS Lower level of abstraction SW processor model SW processor model ASIC glue logic 31 of 52

32 Specification/Modeling/Verification (cont d) A formal model (possibly more) has to be part of a design methodology. Allows unambiguous specification and analysis of the design. The effect of transformations on the design is well-defined. It is possible to formally reason about correctness. Complexity! 32 of 52

33 Specification/Modeling/Verification (cont d) Co-design Finite State Machines (CFSM) is a realistic FSM-based model for Hardware/Software systems [Balarin et al, Kluwer 1997]: One CFSM is an extended FSM; a system is described as a network of communicating CFSMs. The CFSM model is locally synchronous and globally asynchronous. Ptolemy is an environment which accepts specifications of complex systems which are designed heterogeneously [Buck et al, Int. Jrn. of Comp. Sim. 94]: Different parts of the system can be specified according to different computation models: data-flow, finite-state, communicating sequential processes, event-driven, etc. 33 of 52

34 Specification Languages A single specification language can be used for the whole system; does not necessarily mean that we have a homogeneous specification: Several languages can be used for system specification specific languages for the hardware and software part; different languages can be used, depending on the selected model of computation or because of other reasons. How to perform (co)simulation? 34 of 52

35 Specification Languages (cont d) General purpose languages (Ada, C, C++, SystemC, Java, UML, Matlab) Hardware description languages (VHDL, Verilog) Synchronous languages (FSM based): Esterel, Lustre, Signal, StateCharts. Networks of communicating processes: CSP, Lotos, SDL. Data-flow languages: Silage Functional programming languages: Haskell, SML. Algebraic notations: VDM, Z, B. Will we get the System Specification Language? Will multi-language specification become (remain) the standard? 35 of 52

36 Verification and Testing System specification Hardware synthesis System-level synthesis model_h Ref_step_h 1 model_h 1 Ref_step_h m model_h m Ref_step 1 model 1 Ref_step 2 model 2 Ref_step n system architecture model_s Ref_step_s 1 model_s 1 Ref_step_s k model_s k Software synthesis DESIGN VALIDATION formal verification & simulation (looks for errors in specification&design) Fabrication PRODUCT PRODUCT TESTING looks for: design errors fabrication defects physical failures 36 of 52

37 Verification and Testing Informal Specification, Constraints System Level Arch. Selection System architecture Estimation not OK Modeling System model Mapping Scheduling Mapped and scheduled model OK not OK Functional Formal Verification Formal Verification Softw. model Hardw. model Softw. Generation Hardw. Synthesis Lower Levels Softw. blocks not OK Testing OK Prototype Hardw. blocks 37 of 52

38 Final Remarks The real issue here is design of embedded systems Start from the specification at high abstraction level Consider complex trade-offs Concentrate on early design steps Hardware architecture and software are jointly developed Keep a global view and master heterogeneity Important progress has been achieved on certain particular aspects. Some progress towards a methodology and supporting tools. 38 of 52

39 Lecture 1&2 of Embedded Systems: Introduction and Course Organization Difficulties with the design of heterogeneous Hw/Sw systems Requirements of modern embedded systems Embedded system design flow Research issues Course topics 39 of 52

40 Lecture 3&4 System Modelling. Models of Computation and System Specification Languages Models of Computation - Basic models, specific features, comparison - Multimodel specification Specification Languages - Spec. Languages and their relation to models of computation - Multilanguage specification and Cosimulation Formal verification - Formal verification approaches - Model checking 40 of 52

41 Lecture 3&4 Informal Specification, Constraints System Level Arch. Selection System architecture Estimation not OK Modeling System model Mapping Scheduling Mapped and scheduled model OK not OK Functional Formal Verification Formal Verification Softw. model Hardw. model Softw. Generation Hardw. Synthesis Lower Levels Softw. blocks not OK Testing OK Prototype Hardw. blocks 41 of 52

42 Lecture 5&6 Processors and Architectures for Embedded Systems General Purpose vs. Application Specific Processors - Instruction set, Memory, Interconnect and control - DSPs, Microcontrollers, VLIW processors - Design Challenges Core (IP) - based design - Reusable components - Communication-based design - Platform-based design Reconfigurable Systems - Hardware/Software partitioning with reconfigurable processors - Dynamically reconfigurable systems 42 of 52

43 Lecture 5&6 Informal Specification, Constraints System Level Arch. Selection System architecture Estimation not OK Modeling System model Mapping Scheduling Mapped and scheduled model OK not OK Functional Formal Verification Formal Verification Softw. model Hardw. model Softw. Generation Hardw. Synthesis Lower Levels Softw. blocks not OK Testing OK Prototype Hardw. blocks 43 of 52

44 Lecture 7&8 Code Generation and Retargetable Compilers Compiler Generators and Retargetable Compilers - Front end processing - Back end processing - Processor modeling Specific issues related to embedded processor architectures - DSP processors - SIMD instructions - VLIW processors 44 of 52

45 Lecture 7&8 Informal Specification, Constraints System Level Arch. Selection System architecture Estimation not OK Modeling System model Mapping Scheduling Mapped and scheduled model OK not OK Functional Formal Verification Formal Verification Softw. model Hardw. model Softw. Generation Hardw. Synthesis Lower Levels Softw. blocks not OK Testing OK Prototype Hardw. blocks 45 of 52

46 Lecture 9 Software Performance Estimation by Static Analysis Program path analysis Microarchitecture modeling - Cache memory - Pipeline architecture - Branch prediction 46 of 52

47 Lecture 9 Informal Specification, Constraints System Level Arch. Selection System architecture Estimation not OK Modeling System model Mapping Scheduling Mapped and scheduled model OK not OK Functional Formal Verification Formal Verification Softw. model Hardw. model Softw. Generation Hardw. Synthesis Lower Levels Softw. blocks not OK Testing OK Prototype Hardw. blocks 47 of 52

48 Lecture 10&11 System-Level Power/Energy Optimization Main issues in system-level power/energy optimization - System modeling - Hardware and software implementation - Dynamic power management - Computing, memory, communication Dynamic power management - Modeling issues - Predictive, adaptive, and stochastic techniques Power estimation and low power software generation Low power/energy scheduling for real-time systems - Variable voltage systems - Static and dynamic approaches - Energy efficient priority-based scheduling 48 of 52

49 Lecture 10&11 Informal Specification, Constraints System Level Arch. Selection System architecture Estimation not OK Modeling System model Mapping Scheduling Mapped and scheduled model OK not OK Functional Formal Verification Formal Verification Softw. model Hardw. model Softw. Generation Hardw. Synthesis Lower Levels Softw. blocks not OK Testing OK Prototype Hardw. blocks 49 of 52

50 Lecture 12&13 Environments The Cosyma System The Cosmos Environment The SpecSyn Environment Synthesis of Distributed Embedded Systems The POLIS Environment The CoWare Environment 50 of 52

51 Lecture X (X 14) Guest Lecturer from Ericsson 51 of 52

52 Requirements for the 4 Points Participation at the lectures Presentation at one of the lectures Reading of the mandatory literature indicated for each topic and preparation of an one page position report to be handed in before (at) the lecture. 52 of 52