RTL Implementation. Introduction to Structured VLSI Design. Concurrent Statements and Processes. Combinational and Sequential Logic.

Transcription

1 RTL Implementation 32 Introduction to Structured VLSI Design Recap on Processes, Signals, and Variables A Y Y=A*B+C B C 48 Joachim Rodrigues We have complete control (active chioice) over the registers: inferred by the RTL developer if (clock='1' and clock'event) then The content of the cloud is misty: we can specify functionality but we do not know how it will be realized, e.g., logic gates or LUTs Combinational and Sequential Logic Concurrent Statements and Processes Combinational circuit: No internal state Output is a function of inputs only No latches/ffs or closed feedback loop Sequential circuit: With internal state Output is a function of inputs and internal state Concurrent statements (simple processes): a <= b; c <= a + b; d <= a And B; VHDL process : a language construct to encapsulate sequential semantics Process consist of Label Sensitivity list Optional declarative part (before keyword ) Statement part (between keywords and end)

2 VHDL Process A process with a sensitivity list Contains a set of sequential statements to be executed sequentially The whole process is a concurrent statement Can be interpreted as a circuit part enclosed inside a black box Two types of process A process with a sensitivity list A process with wait statement A process is like a circuit part, which can be active (activated) inactive (suspended). A process is activated when a signal in the sensitivity list changes its value Process statements will be executed sequentially until the end of the process Syntax Sensistivity list will be ignored during synthesis process(sensitivity_list) declarations; sequential statement; sequential statement;... Process Example Process with wait statement 3-input and circuit Good: process(a,b,c) y <= a and b and c; bad: process(a) y <= a and b and c; For a combinational circuit, all inputs need to be included in the sensitivity list Process has no sensitivity list Process continues the execution until a wait statement is reached and then suspended Forms of wait statement: wait on signals; wait until boolean_expression; wait for time_expression; Often used in the testbench process y <= a and b and c; wait on a, b, c; A process can have multiple wait statements Process with sensitivity list is preferred for synthesis

3 Architecture body Concurrency Simplified syntax Concurrency Statements in the architecural body are concurrent Ordering of these statements NOT important Example of statements Signal assignment» a <= b and c» d <= not a Processes are concurrent Statements within a process are sequential An entity declaration can be associated with multiple architecture bodies Processes Signals Processes in an architecture body are concurrent Ordering of processes NOT important Statements within a process are sequential Declared in the architecture body's declaration section Signal declaration: Process consist of Label Sensitivity list Optional declarative part (before keyword ) Statement part (between keywords and end) dff: process (clk) if clk event and clk= 1 then if (Reset = '0') then Q <= '0'; else Q <= D; end if; end if; end process dff; signal signal_name, signal_name,... : data_type Signal assignment: signal_name <= projected_waveform; Ports in entity declaration are considered as signals

4 Signals cont d Signals cont d Entities are connected by signals (wires). Syntax: signal signal_names : signal_type; The value of a signal is given by the voltage level of the wire (technology dependent). Signals are metal wires of arbitrary length. Metal has inductive, resistive, and capictive parasitics which introduce delay. Real parasitics are known after routing Signals connect the gates in a design Value of a signal is determined by evaluating an expression Result of the evaluation must match the type of the signal A <= b and c; Q <= '0'; Q <= D; y <= a + b + 1 after 10 ns; Timing info ignored in synthesis and δ delay (simulation) is used Sequential signal assignment statement Syntax sig_name <= value_expression; Syntax is identical to the simple concurrent signal assignment Caution: Inside a process, a signal can be assigned multiple times, but only the last assignment takes effect process(a,b,c,d) -- y entry := y y <= a or c; -- y exit := a or c; y <= a and b;-- y exit := a and b; y <= c and d;-- y exit := c and d; -- y <= y exit is equal to process(a,b,c,d) y <= c and d; What happens if the 3 statements are concurrent statements? Delta delay architecture behav of encoder is signal abar_s,bbar_s : std_logic; CASE: event on b at time T Target signals on (1,3,6) updated after T+Δ Thus, event on bbar_s will trigger (2,4) and target signals are updated after T+2Δ (5) will not be triggered at all -- behav z(3) <= not (a and b and enable); --(1) z(0) <= not (abar_s and bbar_s and enable); --(2) bbar_s <= not b; --(3) Z(2) <= not (a and bbar_s and enable); --(4) abar_s <= not a; --(5) Z(1) <= not (abar_s and b and enable) --(6) end behav;

5 Delta delay cont d Variables Signals are updated after 0ns, or after delta delay: A delta delay represents a infinitesimally small delay Models HW where a minimal amount of time is needed for a change to occur. Allows for ordering od events that occur at the same simulation time during a simulation Each unit of simulation time consists of an infinite number of delta delays An event always occurs at simulation time + a multiple of delta delays Behaviour differs from signal: A new value is assigned instantaneously Variabales declared and used inside a process are local Variables declared outside a process may be shared by several processes (shared variables) Retain their value throughout simulation Used as in traditional PL: a symbolic memory location where a value can be stored and modified Example: No direct hardware counterpart process (...) variable index :integer := 0; index := index +1; Variables Variables cont d Declared and used inside a process Variable declaration: variable variable_name,... : data_type Variable assignment: variable_name := value_expression; Contains no timing info (immediate assignment) No direct hardware counterpart Variables declared and used inside a process are local Variables declared outside a process may be shared by several processes (shared variables) Retain their value throughout simulation Example: process (...) variable index :integer :=0; index:=index +1;

6 Variable assignment statement Variable assignment statement Interpretation Syntax var_name := value_expression; Assignment takes effect immediately No time dimension (i.e., no delay) Behave like variables in C Difficult to map to hardware (depending on context) process(a,b,c) variable tmp: std_logic; tmp := '0'; tmp := tmp or a; tmp := tmp or b; y <= tmp; We need to rephrase the code from the previous slide process(a,b,c) variable tmp0, tmp1, tmp2: std_logic; tmp0 := '0'; tmp1 := tmp0 or a; tmp2 := tmp1 or b; y <= tmp2; The presented slides are integrated in the 2nd VHDL lecture