DESIGN AND PERFORMANCE ANALYSIS OF A NONVOLATILE MEMORY CELL

Transcription

1 DESIGN AND PERFORMANCE ANALYSIS OF A NONVOLATILE MEMORY CELL 1 M. Vasudha, 2 B. Sri Pravallika, 3 Ch. Sai Kiran, 4 P. Subhani, 5 G. Rakesh Chowdary, 6 M Durga Prakash, 7 K Hari Kishore, 8 T.V. Ramakrishna VLSI Research Group, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, AP, India * vasudhareddy96@gmail.com, saikiranchivukula@kluniversity.in ABSTRACT This paper is used to understand the design and structure of a nonvolatile memory cell. Charge injection was improved by reducing the effective oxide thickness of the gate dielectric. Metal/ Al 2 O 3 /SiN/SiO 2 /Si structure was designed to determine the charge trapping properties. High programming and erasing speed as well as large shift of the threshold voltage with high endurance were obtained by scaled down dimensions. Index Terms- Charge Trapping, Threshold Voltage, Al 2 O 3 I. INTRODUCTION Semiconductor digital logic devices are major key components in major key computing and information technologies and they have transformed many aspects of human society over the past few decades. Semiconductor devices are partially responsible for the speed of operation and also for the massive data storage capabilities exhibited by modern computers, portable electronics and many other important commercial applications. The semiconductor technology industry has been engaged in an aggressive trend of down scaling components in pursuit of the high speed, high density for both device and data and for lower power consumption and increased functionality of electronic systems and products [1]. Consequently, non-volatile memory (NVM) products has been developed and manufactured down to a ~16nm critical dimension. However, a few the serious challenges face scaling to the <10nm dimension in order to achieve the higher data and code storage capabilities. As one possible solution for these challenges is alternate memory technologies based on material systems which demonstrate programmable resistance or memristive characteristics are being researched and, in some cases, they are developed also [1]. JARDCS Special Issue On Environment, Engineering & Energy 2320

2 Computer memory can be broadly classified in to two types: volatile and non-volatile memory. Volatile memory can store the data only when the device has power connection once the power connection is gone then the data will be lost. Two forms of volatile memories are available they are Dynamic random-access memory and static random-access memory. Dynamic random-access memory achieves a very high memory density because of storing information in the form of bits on individual capacitors with in an integrated circuit. Static random-access memory has very fast reading as well as writing capabilities, so it can store a single bit of information on multiple transistors at a time. On the other hand, Nonvolatile memory will generally exhibit reduced performance capabilities compared to volatile memory, but it can store the data permanently even when the power off state also because of that it is very desirable form of data storage for a wide range of the electronics application which includes consumer, automotive, computing and communication. Over the past few decades there is an explosion in the market, particularly in the portable electronics market which driven the success of Nonvolatile memory called Flash memory which can store the one or more bits of information on each and every single floating gate transistor. Flash memory has an excellent compromise between cost, programming speed, data retention and data density and reliability [2]. In recent years, Non-volatile memory is mostly used as universal memory which is used in almost every device for memory storage. Less leakage power, higher density and fast read and write speed are the advantages which leads them to use as universal memory, Besides the advantages asymmetric read and write speed and energy cost poses a new confront while using Non-volatile memory [3]. Non-volatile memory (NVM) or non-volatile storage is one of the computer memories which are used to fetch Non-volatile memory stored information even after the device is turned off and back on. This is Non- volatile memory is quite opposite to volatile memory which does not require any constant power supply. Even there is inconsistent power supply it can be used to retrieve the data without any loss in storage. Read only memory, ferroelectric RAM, flash memory is most types of magnetic computer storage devices (e.g. hard and floppy disks, and magnetic tape). Data storage in nonvolatile memory is classified in to 2 types: Mechanically addressed systems Electrically addressed systems JARDCS Special Issue On Environment, Engineering & Energy 2321

3 The contact structure is used to write and read on a selected storage medium in mechanically addressed systems, in these mechanically addressed systems it stores more data compared to Electrically addressed systems. Hard disks, Magnetic tapes, Optical disks are the few examples of Mechanical addressed systems. Electrically addressed systems are classified based on the write mechanism. They are costly but faster in working compared to the Mechanical addressed systems, which are affordable with less cost. FRAM and MRAM are the examples of the electrically addressed systems. The proposed MONOS structure is a electrically addressed system which is faster than other memory devices based on writing mechanism. This MONOS structure is simulated using SILVACO software. Now a day s most of the semiconductor devices development is done using computer modelling. This type of approach is known as TCAD (Technology Computer Aided Design). Usage of these TCAD tools reduces the development cost and time for manufacturing. SILVACO is a TCAD software which can be used as a computer simulation software of silicon processing technology. Using SILVACO software can perform 2-D simulation of various fabrication processing steps like oxidation, diffusion, etching, ion implantation and comparison with the 1-D analytical models. The simulation and implementation of 2-D devices is mainly based on different tools present in SILVACO software like Athena, Atlas. II. NON VOLATILE MEMORY CELL DESIGN The charge trapping characteristics of Metal-Al 2 O 3 -SiN-Oxide-Silicon (MONOS) is observed. The metal is aluminum and the Al 2 O 3 is used as the blocking oxide SIN is used as charge trapping layer. The thickness of O/N/O is 8/5/2nm. Here the size of the memory cell is reduced to the Nano scale [5]. The charge trapping nonvolatile memory structures based on SiN storage layers are used to extend floating gate technologies. SiN plays a fundamental role on the both the reliability and performance of the memory cells. The main advantage of nonvolatile memory is its low cost and the high density in storage is because of physical scaling. During the physical scaling the main attention is attracted by charge trapping layer because of their advantages like high scalability, low program/erase voltage and endurance. However, the traditional MONOS structure designed based on charge trapping layer has difficulty in double win between the switching and the reliability. So as to overcome this difficulty here we have proposed a model in that the blocking layer in MONOS structure is JARDCS Special Issue On Environment, Engineering & Energy 2322

4 replaced with the high dielectric materials like aluminum oxide (Al 2 O 3 ). The advantage of using high-k material as blocking layer is mainly we can restrict the gate injection and also to induce the fast erase speed [5]. Figure: 1 A Schematic Diagram Of MONOS Structure In the Fig 1 the diagram shows the schematic structure of MONOS using Metal-Al2O3-SiN- Oxide-Silicon. Nonvolatile memory (NVM) with SiN as charge-trapping layer has more advantages compared to the conventional floating-gate based memory, some of them are good scalability, lower program/erase voltage, improved endurance, and more robust to stress-induced leakage current [4]. III. RESULTS AND DISCUSSIONS Figure: 2 Proposed Monos Structure Implemented Using Silvaco In Fig 2 MONOS structure is designed using SiO 2 as tunneling oxide over which a thin layer of SiN used as charge trapping layer. Above the trapping layer we have the high dielectric material Al 2 O 3 which acts as a blocking layer for the charges flowing from source to drain and vice versa during writing and erasing of data into the memory. Blocking oxide layer is JARDCS Special Issue On Environment, Engineering & Energy 2323

5 covered by Al metal which acts as a control gate. This control gate is protected with a thin layer of SiO 2. Figure: 3 Charge Trapping Layers In Proposed MONOS Structure From Fig 3 the charge trapping layers helps in programming and erasing of data in the memory. By supplying positive voltage to the source, we can write the data into the memory which is stored in the trapping layer SiN and blocked by the blocking oxide Al 2 O 3. During erasing negative voltage is supplied to erase the data present in the memory. Figure: 4 A Plot Of C Gate Voltage Vs. Drain Current Fig 4 depicts the transfer characteristics of the proposed MONOS nonvolatile memory cell before programming.from this Fig 4 it indicates that the device will turn on at threshold voltage equal to 0.8 V which is less when compared to other Non-volatile devices JARDCS Special Issue On Environment, Engineering & Energy 2324

6 Figure: 5 A Plot Of Transient Time Vs. Substrate Current In Fig 5 MONOS structure under 12v shows a counterclockwise direction of hysteresis during programming. This graph indicates time taken for erasing data when supplying negative voltage as it requires negative voltage for writing and positive voltage for writing data. Figure: 6 A Plot Of C Gate Voltage Vs. Drain Current The figure 6 describes about the comparison between C gate vs. Drain current before and after writing into the memory. It shows that writing into nonvolatile memory cell is faster compared to other types of nonvolatile memories. It also shows that the drain current observed in nonvolatile cell after programming is less which means the nonvolatile cell operates at less current with faster writing and erasing capabilities. IV. CONCLUSIONS In this paper, performance analysis and classification of different layers present in the MONOS nonvolatile memory cell are discussed. It is observed that the proposed structure has JARDCS Special Issue On Environment, Engineering & Energy 2325

7 high programming and erasing speed as well as large shift of the threshold voltage with high endurance as Al 2 O 3 is a high-k material. This is used in Flash memories, as it requires fast erasing speed and writing speed. REFERENCES 1. Ellis, Noah. Design, fabrication, and characterization of nano-scale cross-point hafnium oxide-based resistive random access memory. Diss. Georgia Institute of Technology, Spinelli, Alessandro S., Christian Monzio Compagnoni, and Andrea L. Lacaita. "Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices." Computers 6.2 (2017): Bez, R., and A. Pirovano. "Overview of non-volatile memory technology: markets, technologies and trends." Advances in Non-volatile Memory and Storage Technology He, Wei, et al. "Performance Improvement in Charge-Trap Flash Memory Using Lanthanum-Based High-$\kappa $ Blocking Oxide." IEEE Transactions on Electron Devices (2009): Ji, Hao, et al. "Improvement of Charge Injection Using Ferroelectric Si: HfO 2 As Blocking Layer in MONOS Charge Trapping Memory." IEEE Journal of the Electron Devices Society 6.1 (2018): Dr. Seetaiah Kilaru, Hari Kishore K, Sravani T, Anvesh Chowdary L, Balaji T Review and Analysis of Promising Technologies with Respect to fifth Generation Networks, 2014 First International Conference on Networks & Soft Computing,ISSN: /14,pp ,August Meka Bharadwaj, Hari Kishore "Enhanced Launch-Off-Capture Testing Using BIST Designs Journal of Engineering and Applied Sciences, ISSN No: X, Vol No.12, Issue No.3, page: , April P Bala Gopal, K Hari Kishore, R.R Kalyan Venkatesh, P Harinath Mandalapu An FPGA Implementation of On Chip UART Testing with BIST Techniques, International Journal of Applied Engineering Research, ISSN , Volume 10, Number 14, pp , August 2015 JARDCS Special Issue On Environment, Engineering & Energy 2326

8 9. A Murali, K Hari Kishore, D Venkat Reddy "Integrating FPGAs with Trigger Circuitry Core System Insertions for Observability in Debugging Process Journal of Engineering and Applied Sciences, ISSN No: X, Vol No.11, Issue No.12, page: , December Mahesh Mudavath, K Hari Kishore, D Venkat Reddy "Design of CMOS RF Front-End of Low Noise Amplifier for LTE System Applications Integrating FPGAs Asian Journal of Information Technology, ISSN No: , Vol No.15, Issue No.20, page: , December JARDCS Special Issue On Environment, Engineering & Energy 2327