Part 4: VHDL for sequential circuits. Introduction to Modeling and Verification of Digital Systems. Memory elements. Sequential circuits

Transcription

1 M1 Informatique / MOSIG Introduction to Modeling and erification of Digital Systems Part 4: HDL for sequential circuits Laurence PIERRE / Sequential circuits Memory elements! In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the sequence of past inputs, the input history Wikipedia! Synchronous sequential circuit: the changes in the state of memory elements are synchronized by a (periodic) signal, the clock signal

2 Memory elements Memory elements Data Enable Data Enable Memory elements Synchronous sequential circuits! Toy example (logic diagram) The D flip-flop is widely used. It captures the value of its D input on the rising edges of the clock Obtained by logic synthesis (see later) Combinational parts Flip-flops

3 HDL HDL! The is a concurrent statement, commonly used in RTL descriptions of sequential circuits.! The is a concurrent statement, commonly used in RTL descriptions of sequential circuits. (sensitivity-list) HDL and or sequential circuits with the content of the sensitivity list with the wait statement(s) (sensitivity-list) or The "" statement combinational, sequential? with the content of the sensitivity list with the wait statement(s) HDL Process activation! The is a concurrent statement, commonly used in RTL descriptions of sequential circuits. (sensitivity-list) or with the content of the sensitivity list with the wait statement(s)! With a sensitivity list! The sensitivity list is a list of signals. The will be reactivated and evaluated whenever the value of one of these signals changes (event)! When it is activated, the sequential statements are executed. After it has executed the last statement, the suspends again! In that case, the cannot include wait statements! With wait statement(s)! The activation of the is determined by its wait statement(s) 90 91

4 Wait statement Wait statement! Used to suspend the execution! The sequential statements are executed up to the first wait statement. The suspends until the activation condition holds. Then the is activated again, and the sequential statements are executed up to the next wait statement,! Syntax (each clause is optional) wait on signal-list until condition for time;! on: the suspends until a change (event) occurs on one or more of the signals! until: the suspends until the condition holds! for: timeout clause! Used to suspend the execution! The sequential statements are executed up to the first wait statement. The suspends until the activation condition holds. Then the is activated again, and the sequential statements are executed up to the next wait statement,! Syntax (each clause is optional) Example: wait on signal-list until condition for time;! on: the suspends wait until on a change A,B until (event) Enable occurs = '1'; on one or more of the signals T <= A and B after 5 ns;! until: the suspends ; until the condition holds! for: timeout clause Combinational statement / Clocked statements! Note: combinational statements are equivalent to es.! Example: a concurrent signal assignment statement is equivalent to a that has a sensitivity list made of the signals of its right-hand side! What about flip-flop updates?! The activation condition is a clock (rising) edge! This induces a unique wait statement (as first statement of the ), that can be of the form: Output <= A or B;! Simple example of shift register entity shifter is port(clk : in std_logic; Data_in : in std_logic; Data_out : out std_logic_vector(3 downto 0); end shifter; 94 96

5 Clocked statements Clocked statements! What about flip-flop updates?! The activation condition is a clock (rising) edge! This induces a unique wait statement (as first statement of the ), that can be of the form wait until clk'event and clk='1';! Simple example of shift register entity shifter is port(clk : in std_logic; Data_in : in std_logic; Data_out : out std_logic_vector(3 downto 0); end shifter;! What about flip-flop updates?! The activation condition is a clock (rising) edge architecture arch1 of shifter is! This signal induces shift_reg a unique wait : std_logic_vector(3 statement (as first statement downto 0) of the ), that can be of the form := (others<='0'); wait until clk'event and clk='1';! Simple example of shift register entity shifter wait until is clk'event and clk='1'; port(clk shift_reg : in std_logic; <= shift_reg(2 downto 0) & Data_in; end Data_in ; : in std_logic; Data_out Data_out <= : shift_reg; out std_logic_vector(3 downto 0); end end shifter; arch1; Sequential conditional statement Sequential conditional statement! The sequential conditional statement is as follows if condition 1 then statements 1 elsif condition 2 then statements 2 elsif condition 3 then statements 3 else statements N! The elsif and else clauses are optional! The conditions condition i are Boolean expressions! The statements statements i are (series of) sequential statements! The sequential conditional statement is as follows if condition 1 then statements 1 elsif condition 2 then statements 2 elsif condition 3 then statements 3 else statements Example: N! The elsif and else if clauses In1 = '0' are or optional In2 = '0' then Output <= '0' after 5 ns;! The conditions condition i are Boolean expressions elsif In1 = 'X' or In2= 'X' then! The statements statements Output i <= are 'X' (series after of) 5 sequential ns; statements else Output <= '1' after 5 ns; wait on In1, In2;

6 Sequential case statement Sequential case statement! The case statement is as follows case expression is when choice 1 => statements 1 when choice 2 => statements 2 when choice N => statements N end case;! The expression is of a discrete type! Each choice i can be of the form: a-choice 1 a-choice 2 a-choice 3 and the value others for choice N means otherwise! The statements statements i are (series of) sequential statements! The case statement is as follows case expression is when choice 1 => statements 1 when choice 2 => statements 2 when choice N Example: => statements N end case;! The expression is of a discrete type case X is! Each choice i can be of the when form: 1 => Output <= 0; a-choice 1 a-choicewhen 2 a-choice 2 3 => 3 Output <= 1; when others => Output <= 2; and the value others end for choice case; N means otherwise! The statements statements wait on i are X; (series of) sequential statements Example Example! BCD code recognizer! Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by 4 bits! Simple implementation of a BCD code recognizer! BCD code recognizer entity BCD is port(i,clk: in std_logic; o: out std_logic); end BCD; architecture RTL of BCD is signal S1, S2, S3, S4 : std_logic := '0'; Such an initial value is only meaningful for simulation. The description wait until clk'event and clk='1'; should take into account S1 <= i; the reset signal (see later) S2 <= S1; S3 <= not S3; S4 <= (not S3 and S4) or (not S4 and S3); end RTL;

7 Example - Simulation Synthesis interpretation! BCD code recognizer! The testbench entity must "generate" the clock signal! Example entity testbcd is end testbcd;! Clocked statements infer flip-flops, combinational statements are interpreted as combinational blocks! Example: what are the interpretations of these pieces of HDL code? architecture Struct1 of testbcd is component BCD is port(i,clk: in std_logic; o: out std_logic); end component; signal X1,ck,Z1 : std_logic := '0'; B1: BCD port map(x1,ck,z1); ck <= not ck after 30 ns; X1 <= '0', '1' after 80 ns, '0' after 120 ns, '1' after 200 ns, '0' after 228 ns, '1' after 300 ns, '0' after 340 ns, '1' after 502 ns, '0' after 725 ns; end Struct1; wait until ck'event and ck='1'; x <= a xor y; y <= a and c; z <= y; wait until ck'event and ck='1'; x <= a xor y; y <= a and c; z <= y; Synthesis interpretation What should I remember! A latch will be inferred when a signal is not assigned a value explicitly in all branches of a conditional statement! Example: what are the interpretations of these pieces of HDL code? (a, c, r) if (a ='1' or c='0') then x <= r xor a; (a, c, r) if (a ='1' or c='0') then x <= r xor a; else x <= r or c;