Hardware Synthesis from Bluespec

Transcription

1 Hardware Synthesis from Bluespec Silvina Hanono Wachman Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology Happy! Day! L11-1

2 Guarded interfaces Modules with guarded interfaces are a new way of expressing sequential circuits Every method has a guard ( wire) For some methods guard is always true The value returned by a method is meaningful only if its guard is true Every action method has an enable signal (en wire) and it can be invoked (en can be set to true) only if its guard is true Every method can have input data Value and ActionValue methods have output data interface Fifo#(numeric type size, type t); method Action enq(t x); notice, en and method Action deq; wires are method t first; implicit endinterface en en enq deq first FIFO L11-2

3 GCD Interface interface GCD; method Action start (Bit#(32) a, Bit#(32) b); method ActionValue#(Bit#(32)) getresult; endinterface a b en start GCD getresult en module mkgcd (GCD); Reg#(Bit#(32)) x <- mkreg(0); Reg#(Bit#(32)) y <- mkreg(0); Reg#(Bool) busy_flag <- mkreg(false); rule gcd; if (x >= y) begin x <= x y; end //subtract else if (x!= 0) begin x <= y; y <= x; end //swap endrule method Action start(bit#(32) a, Bit#(32) b) if(!busy_flag); x <= a; y <= b; busy_flag <= True; method ActionValue#(Bit#(32)) getresult if(busy_flag&&(x==0)); busy_flag <= False; return y; endmodule L11-3

4 Power of Abstraction: Another GCD implementation start turni start start gcd1 gcd2 getresult getresult turno getresult A GCD module with the same interface but with twice the throughput; uses two gcd modules in parallel turni is used by the start method to direct the input to the gcd whose turn it is and then turni is flipped Similarly, turno is used by getresult to get the output from the appropriate gcd, and then turno is flipped interface GCD; method Action start (Bit#(32) a, Bit#(32) b); method ActionValue#(Bit#(32)) getresult; endinterface L11-4

5 High-throughput GCD code module mkmultigcd (GCD); GCD gcd1 <- mkgcd(); GCD gcd2 <- mkgcd(); Reg#(Bool) turni <- mkreg(false); Reg#(Bool) turno <- mkreg(false); method Action start(bit#(32) a, Bit#(32) b); if (turni) gcd1.start(a,b); else gcd2.start(a,b); turni <=!turni; method ActionValue (Bit#(32)) getresult; Bit#(32) y; if (turno) y <- gcd1.getresult else y <- gcd2.getresult; turno <=!turno return y; endmodule interface GCD; method Action start (Bit#(32) a, Bit#(32) b); method ActionValue#(Bit#(32)) getresult; endinterface L11-5 start turni start start gcd1 gcd2 getresult getresult turno getresult

6 Hardware Synthesis How is Bluespec code synthesized into hardware? March 14, 2019 MIT Spring 2019 L11-6

7 A new mux-like structure to deal with multiple sources x1 v1 x2 v2 x = (v1 & x1) (v2 & x2) v = v1 v2 x v x1 v1 x2 v2 x If x is n bits, this structure is repeated n times v xi has a meaningful value only if its corresponding vi is true Compiler has to ensure that at most one vi input to the mux is true at any given time; the circuit will behave unpredictably if multiple input signals are valid L11-7

8 FIFO Circuit module mkfifo (Fifo#(1, t)); Reg#(t) d <- mkregu; Reg#(Bool) v <- mkreg(false); method Action enq(t x) if (!v); v <= True; d <= x; method Action deq if (v); v <= False; method t first if (v); return d; endmodule I/O: Interface Instantiate state For every register with multiple assignments, insert a mux Compile enq Compile deq Compile first enq deq first True False interface Fifo#(numeric type size, type t); method Action enq(t x); method Action deq; method t first; endinterface L11-8 d v

9 Redrawing the FIFO Circuit enq.data d first.data enq.en deq.en True False v enq. deq. first. A module is a sequential circuit with input and output wires corresponding to its interface methods This is a sequential circuit because it has state elements; however, it has no cycles L11-9

10 Next state transition Partial Truth Table An aside next inputs state state outputs enq. en enq. data deq. en d t v t d t+1 v t+1 enq. deq. first. 0 x 0 x 0 x d 0 x 0 d x 0 d 1 d d 0 x 1 d d first. data Illegal inputs Tedious! L11-10

11 Streaming a function: Circuit inq f outq rule stream; outq.enq(f(inq.first)); inq.deq; endrule This is a sequential machine too! enq deq first inq f outq enq deq first Connect the datapath Collect the ready signals Enable the called methods Notice that enq.en cannot be True unless enq. is true; deq.en cannot be True unless deq. is true L11-11

12 Redrawing the sequential circuit Input wires deq enq deq inq outq first deq enq first deq f Notice: Output wires All input wires are red and blue All output wires are green and blue enq enq L11-12

13 Hierarchical sequential circuits sequential circuits containing modules Each module represents a sequential machine Module 1 Module 2 Module n Declared in the module Input Combinational logic (no cycles, no clock) Output Defined by the Module type (Interface) Defined by the rules and methods of the module L11-13

14 Hardware Synthesis High-level idea Every module represents a sequential machine Register is a primitive module its implementation is outside the language Register bit width is derived from its type Each Register and module is instantiated explicitly Input/Output wires of a module are derived from its interface, i.e., type Rules and methods define the combinational logic to connect registers and modules The resulting hardware is a collection of sequential machines, which itself behaves like a sequential machine L11-14

15 Register: The Primitive module interface Reg#(type t); method Action _write(t x); method t _read; endinterface en Implementation is defined outside the language A register is created using mkreg or mkregu The guards of _write and _read are always true and not generated Special syntax x <= e instead of x._write(e) x instead of x._read in expressions _write Reg _read Always true L11-15

16 Interface defines input/output wires Inputs and outputs are defined by the type of the module, i.e., its interface definition Each method has a output ready wire Each method may have 0 or more input data wires Each Action method and ActionValue method has an input enable wire Each value method and ActionValue method has an output data wire An Action method has no output data wire interface GCD; method Action start (Bit#(32) a,bit#(32) b); method ActionValue(Bit#(32)) getresult; endinterface en start GCD getresult en L11-16

17 Compiling Guards Bluespec design specifies the guard for each method and rule The guard may be stated explicitly; If there is no guard then it is assumed to be true But the guard also implicitly inherits the guards of the called methods The compiler generates the ready signal from these explicit and implicit guards L11-17

18 Guards define the ready signals module mkfifo (Fifo#(1, t)); Reg#(t) d <- mkregu; Reg#(Bool) v <- mkreg(false); method Action enq(t x) if (!v); v <= True; d <= x; method Action deq if (v); v <= False; method t first if (v); return d; endmodule enq deq True False d v first L11-18

19 Combined Guards start turni multigcd start start gcd1 gcd2 getresult getresult turno getresult method Action start(bit#(32) a, Bit#(32) b); if (turni) gcd1.start(a,b); else gcd2.start(a,b); Implicit guard turni <=!turni; turni gcd1.start. gcd2.start. multigcd.start. L11-19

20 Generating enable signals and associated data Bluespec design implicitly specifies the enable signal for each of the called Action and ActionValue method It does so by propagating the incoming enable signals of the calling method or rule body for each called method guard L11-20

21 Rules and methods define the combinational logic and enables module mkex1 (...); Reg#(t) x <- mkregu; method Action f(t a); x <= e; endmodule module mkex2 (...); Reg#(t) x <- mkregu; method Action f(t a); if (b) x <= e; endmodule a f.en a f.en f f e e b x.data x.en x.data x.en x x module mkex3 (...); Reg#(t) x <- mkregu; method Action f(t a); if (b) x <= e1; else x <= e2; endmodule Not shown: f. = True a f.en f e1 e2 b T F x.data x.en x L11-21

22 Synthesis of multiple sources for register assignments module mkex4 (...); Reg#(t) x <- mkregu; method Action f(t a); x <= e1; method Action g(t a); x <= e2; endmodule f.data f.en g.data g.en f g e1 e2 x Compiler has to ensure that both f and g can t be enabled together This information is provided by the compiler in the form of a conflict matrix (CM) for each module L11-22

23 Conflict Matrix for an Interface Conflict Matrix (CM) defines which methods of a module can be called concurrently CM for a register: reg.r reg.w reg.r CF < reg.w > C Two reads can be performed concurrently (CF Conflict Free) Two concurrent writes conflict (C) and are not permitted A read and a write can be performed concurrently and it behaves as if the read happened before the write (r<w) CM of a register is used systematically to derive the CM for the interface of a module CM can also be defined for any set of rules L11-23

24 One-Element FIFO module mkfifo (Fifo#(1, t)); Reg#(t) d <- mkregu; Reg#(Bool) v <- mkreg(false); method Action enq(t x) if (!v); v <= True; d <= x; method Action deq if (v); v <= False; method t first if (v); return d; endmodule We don t care about conflicts between mutually exclusive rules or methods because they can never be ready at the same time L11-24 enq deq first n n enq deq first FIFO enq deq first C ME ME ME C < ME > CF ME = mutually exclusive a<b = a precedes b

25 Take-home problem: Draw the circuit for this GCD interface GCD; method Action start (Bit#(32) a,bit#(32) b); method ActionValue(Bit#(32)) getresult; endinterface module mkgcd (GCD); Reg#(Bit#(32)) x <- mkreg(0); Reg#(Bit#(32)) y <- mkreg(0); Reg#(Bool) busy <- mkreg(false); rule gcd; if (x >= y) begin x <= x y; end //subtract Assume b!= 0 else if (x!= 0) begin x <= y; y <= x; end //swap endrule method Action start(bit#(32) a, Bit#(32) b) if (!busy); x <= a; y <= b; busy <= True; method ActionValue (Bit#(32)) getresult if (busy && (x==0)); busy <= False; return y; endmodule en start GCD getresult en L11-25