Administrivia. Expect new HW out today (functions in assembly!)

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Brianna Perkins
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1 Caching 1/25/19

2 Administrivia Expect new HW out today (functions in assembly!)

3 Memory so far Big array indexed by the memory address accessed by load and store of various types Implicitly assumed: One memory, all of which is available to every program Every cell equally fast to access

4 It s all lies!!! Several different types of memory Some parts are much faster to access than others Memory addresses as used by the program are not the same as physical addresses Every program lives in its own address space (possibly with shared regions)

5 Types of memory access time (ns) $ / GiB SRAM ,000 DRAM Flash 5,000 50, magnetic disk 5 million 20 million Source: Patterson & Hennessy, Computer organization and design, 2014 Numbers from 2012

6 Types of memory access time (ns) $ / GiB SRAM ,000 DRAM Flash 5,000 50, magnetic disk 5 million 20 million Source: Patterson & Hennessy, Computer organization and design, 2014 Numbers from 2012 Idea of caching: Use different kinds of memory in layers of increasing size and decreasing speed so that some of memory is fast

7 Effects actually visible to user int[][] array = new int[size][size]; for(int i=0; i < size; i++) for(int j=0; j < size; j++) /* DO SOMETHING */ Version 1: array[i][j] *= 2; Version 2: array[j][i] *= 2;

8 Version Time (s) Version Size

Locality: temporal: Likely to reuse memory addresses soon spatial: Likely to

9 Idea of caching (take 2) Store data near the processor to get speed close to that of fast memory, but cost and size close to that of cheap memory Locality: temporal: Likely to reuse memory addresses soon spatial: Likely to use memory addresses near those we use now Processor L1 cache L2 cache L3 cache RAM

10 Caching: So cool it s not just for the processor Web browser caches pages that you ve viewed Name servers cache translations they ve recently done between names and IP addresses (e.g. cs.knox.edu becomes )

11 First: A quick intro to binary numbers 16s bit 8s bit 4s bit 2s bit 1s bit = = The i th bit from the right (starting with 0) is worth 2 i Dividing by 2 is equivalent to shifting 1 place to the right Multiplying by 2 is equivalent to adding a 0 on the right

12 What is the value of the binary number ? A. 42 B. 78 C. 108 D. 214 E. None of the above

13 What is the value of the binary number ? A. 42 B. 78 C. 108 D. 214 E. None of the above

14 Cache terminology Hit: Cache delivers the data and saves trip to to memory Miss: Cache doesn t have the data

15 Cache organization Slot: unit of storage in the cache Able to store a contiguous chunk of memory Line: Chunk of data that goes into a slot

16 Direct-mapped cache Memory address determines slot for each line

17 Direct-mapped cache Memory address determines slot for each line Which address bits should determine the slot? A. High-order bits (left part of #) B. Low-order bits (right part of #) C. Doesn t matter

18 Direct-mapped cache Memory address determines slot for each line Which address bits should determine the slot? A. High-order bits (left part of #) B. Low-order bits (right part of #) C. Doesn t matter

19 Caveat: Cache lines contain multiple addresses

20 Caveat: Cache lines contain multiple addresses What does this allow the cache to exploit? A. Temporal locality B. Spatial locality C. Both of these D. Neither of these E. The proletariat

21 Caveat: Cache lines contain multiple addresses What does this allow the cache to exploit? A. Temporal locality B. Spatial locality C. Both of these D. Neither of these E. The proletariat

22 Direct-mapped cache Each address has one possible position in the cache, determined by its middle bits tag cache position offset slot in which this address can be stored where addr falls in cache line

23 How many bits would the tag occupy in a system with a 32-bit address space where the cache has 1024=2 10 slots, each holding 4 bytes? A. 10 B. 14 C. 18 D. 22 E. None of the above or cannot be determined

24 How many bits would the tag occupy in a system with a 32-bit address space where the cache has 1024=2 10 slots, A. 10 B. 14 C. 18 D. 22 each holding 4 bytes? E. None of the above or cannot be determined (20 = )

Fundamentals of Computer Systems

Fundamentals of Computer Systems Caches Martha A. Kim Columbia University Fall 215 Illustrations Copyright 27 Elsevier 1 / 23 Computer Systems Performance depends on which is slowest: the processor or