Computer Organization and Assembly Language (CS-506)

Transcription

1 Computer Organization and Assembly Language (CS-506) Muhammad Zeeshan Haider Ali Lecturer ISP. Multan Lecture 2 Memory Organization and Structure The CPU

2 Today s Agenda: Memory Bit byte and Word Bit Position Memory Operation Memory Hierarchy Types of memory Memory organization The CPU ALU in CPU Registers in CPU CPU Control Unit The CPU Organization.

3 Memory Information processed by the computer Is stored In Its memory. A memory circuit can store one bit of data. Two possible values in memory circuit to be store 0 or 1 Memory circuit are organized tin groups to store eight bit of data called Byte and two bytes are organized to form a Word. Each Byte of a memory has address that starts from 0, 1, 2. Data stored in memory byte is called content of memory.

4 Memory

5 Bit Position Bit Positions are numbered from left to right Starts from 0 Byte bit positions. (lower bits) Word Bit position (high bits)

6 Memory Operations Read To fetch data Write To store new data on memory

7 Memory Hierarchy Registers In CPU Internal or Main memory May include one or more levels of cache RAM External memory Backing store

8 Internal Memory Types Memory Type Category Erasure Write Mechanism Volatility Random-access memory (RAM) Read-write memory Electrically, byte-level Electrically Volatile Read-only memory (ROM) Read-only memory Not possible Masks Programmable ROM (PROM) Erasable PROM (EPROM) UV light, chip-level Nonvolatile Electrically Electrically Erasable PROM (EEPROM) Read-mostly memory Electrically, byte-level Flash memory Electrically, block-level

9 External Memory Types HDD Magnetic Disk(s) SDD (Solid State Disk(s)) Optical CD-ROM CD-Recordable (CD-R) CD-R/W DVD Magnetic Tape

10 Random Access Memory (RAM) Misnamed as all semiconductor memory is random access Read/Write Volatile Temporary storage Static or dynamic

11 Types of RAM Dynamic RAM (DRAM) are like leaky capacitors; initially data is stored in the DRAM chip, charging its memory cells to maximum values. The charge slowly leaks out and eventually would go to low to represent valid data; before this happens, a refresh circuitry reads the contents of the DRAM and rewrites the data to its original locations, thus restoring the memory cells to their maximum charges Static RAM (SRAM) is more like a register; once the data has been written, it will stay valid, it doesn t have to be refreshed. Static RAM is faster than DRAM, also more expensive. Cache memory in PCs is constructed from SRAM memory.

12 Dynamic RAM Bits stored as charge in capacitors Charges leak Need refreshing even when powered Simpler construction Smaller per bit than SRAM Less expensive Need refresh circuits Slower Used for main memory in computing systems Essentially analogue Level of charge determines value

13 DRAM Refreshing Refresh circuit included on chip Disable memory array chip Count through rows and select each in turn Read contents & write it back (restore) Takes time Slows down apparent performance

14 Static RAM Bits stored as on/off switches No charges to leak No refreshing needed when powered More complex construction Larger per bit More expensive Does not need refresh circuits Faster Cache Digital Uses flip-flops

15 SRAM v DRAM Both volatile Power needed to preserve data Dynamic cell Simpler to build, smaller More dense Less expensive Needs refresh Larger memory units Static Faster Cache

16 Read Only Memory (ROM) Provides permanent storage (nonvolatile) Used for: microprogramming, library subroutines (code) and constant data, systems programs (BIOS for PC or entire application + OS for certain embedded systems) Types Written during manufacture (very expensive for small runs) Programmable (once) PROM (needs special equipment to program) Read mostly Erasable Programmable (EPROM) - Erased by UV Electrically Erasable (EEPROM) - Takes much longer to write than read Flash memory - Erase whole memory electrically

17 This picture shows the CPU performance against memory access time improvements over the years Clearly there is a processor-memory performance gap that computer architects must take care of Memory Hierarchy Design (1) Since 1987, microprocessors performance improved 55% per year and 35% until 1987

18 Memory Hierarchy Design (2) Registers (CPU) Cache (one or more levels) Main Memory Disk Storage Specialized bus (internal or external to CPU) Memory bus I/O bus It is a tradeoff between size, speed and cost and exploits the principle of locality. Register Fastest memory element; but small storage; very expensive Cache Fast and small compared to main memory; acts as a buffer between the CPU and main memory: it contains the most recent used memory locations (address and contents are recorded here) Main memory is the RAM of the system Disk storage - HDD

19 Cache Is the first level of memory hierarchy encountered once the address leaves the CPU Every address reference goes first to the cache; If the desired address is not here, then we have a cache miss; The contents are fetched from main memory into the indicated CPU register and the content is also saved into the cache memory If the desired data is in the cache, then we have a cache hit; The desired data is brought from the cache, at very high speed (low access time) Most software exhibits temporal locality of access, meaning that it is likely that same address will be used again soon, and if so, the address will be found in the cache

20 Cache Organization

21 The Central Processing Unit: manages the instructionexecution cycle FETCH DECODE EXECUTE coordinates the activities of other devices

22 The Central Processing Unit: Brain of the computer Contains the executing program of the computer Each instruction is a bit string Language of 0 s and 1 s is called Machine Language Instructions performed are called instruction set

23 Central Processing Unit: Arithmetic logic unit Performs arithmetic and logical operations Arithmetic operation Unary: increment (+1) and decrement (-1) Binary: add, subtract, multiply, and divide Logical operation Unary: NOT Binary: AND, OR, XOR

24 Central Processing Unit: Registers Registers are fast storage locations that hold data temporarily. Data registers Input data and output data Instruction registers Program counter

25 Central Processing Unit: Control Unit The control unit is like the part of the human brain that controls the operation of each part of the body. Controlling is achieved through wires that can be on (hot) or off (cold).

26 The Central Processing Unit: Organization Execution unit Bus Interface Unit

27 Central Processing Unit: Execution Unit Execute the instructions Contains Registers ALU Temp Registers Flags

28 Central Processing Unit: Bus Interface Unit Manages communication b/w EU and mem or I/O Responsible for transfer data and control signals on buses Contains segment registers for holding address of memory locations Instruction pointer point outs the addres of th enext instruction to be processed. Manages Instructions queue Perfoms instruction prefetch