Final Report For CIF Project Redevelopment of Course Materials for EE 4750

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1 Final Report For CIF Project Redevelopment of Course Materials for EE 4750 Submitted by Gang Feng Department of Electrical Engineering Summary EE4750 (Advanced Digital Design) and EE4720 (Computer Architecture) are the two courses that electrical engineering (EE) students must take in order to graduate in computer emphasis. Due to some historical reasons, there are a lot of materials overlapping between the two courses. In addition, the curriculum rearrangement in the last a couple of years and the advance of new technology in digital circuit area make it imperative (in my opinion) to add much more new contents to EE4750. As such, I propose to redevelop the course materials centered at the adoption of a new circuit development board that uses the latest FPGA (field programmable gate array) technologies. Completed Works Lecture Notes 1) Review materials for EE4750 Attachment 1 includes the review materials for EE4750 that will be covered during the first two lectures. These materials make sure the students have the required knowledge of digital circuit for this course. 2) VHDL lecture notes using ModelSim In previous semesters, VHDL was taught using Altera s software Quartus or Maxplus+II. During this project, these lecture notes were redeveloped using the ModelSim software. Figure 1 shows an example that includes the simulation result obtained from ModelSim. Figure 1. A slide developed using ModelSim software 1

2 3) ModelSim simulation lecture notes A power point file has been developed to teach how to use the ModelSim software. Figure 2 is an example of the slides. Figure 2. A slide developed for teaching ModelSim software 4) A quick-start instruction sheet has been developed to help the students learn how to use Xilinx Project Navigator software. See Attachment 2. 5) VHDL test bench lecture notes A power point file has been developed to teach how to write VHDL test bench. An example slide is shown in Figure 3. Figure 3. A slide developed for teaching VHDL test bench 6) A power point file has been developed to teach how to use Spartan-3 memory modules. See example slide in Figure 4. 2

3 Figure 4. A slide developed for teaching Spartan-3 memory modules 7) A power point file has been developed to teach how to design 8051 CPU using VHDL and Xilinx Spartan-3 board. An example slide is shown in Figure 5. Notice the 8051 CPU design schematic has been tested on the Spartant-3 board. Figure 5. A slide developed for teaching how to design an 8051 CPU using VHDL 8) A power point file has been developed to teach how to use the RS-232 port on the Spartan-3 board. See Figure 6 for example slide. Notice that the schematic has been tested on the board. 9) A power point file has been developed to teach how to use the external fast asynchronous memory on the Spartan-3 board. See Figure 7 for example slide. Notice that the schematic has been tested on the board. 3

4 Figure 6. A slide developed for teaching how to use the RS-232 port on Spartan-3 board Figure 7. A slide developed for teaching how to use the asynchronous memory on Spartan-3 board 10) A power point file has been developed to teach how to write test bench in Verilog. See Figure 8 for example slide. 11) Several files have been developed to teach how to use the VGA display on Spartan-3 board. See Figure 9 for example slide. 4

5 Figure 8. A slide developed for teaching how to write test bench in Verilog Figure 9. A slide developed for teaching how to use the VGA display on Spartan-3 board NOTE: (1) A total number of 20 Power Point files have been redeveloped based on the ModelSim software and Xilinx Spartan-3 board. Each file contains as many as 30 slides. These documents take a total of 60MB disk space. It s impossible to include all of these materials in this report, but all of these documents are available to any UWP employee upon request. (2) The original plan for this CIF project includes development of materials regarding FPGA based DSP implementation. However, after careful consideration, I feel such materials do not quite fit in this course. Instead, I decided to develop some materials for how to design asynchronous digital circuit. See Attachment 3. 5

6 Lab Project and Homework Assignments 1) Lab projects #2 and #3 have been redeveloped due to change lecture notes and development board to be used. See Attachment 4. 2) Homework assignments have been redeveloped due to change of lecture notes and textbook. See Attachment 5. Sharing of Work with Colleagues The developed materials will be shared with the colleagues in EE department during a department meeting in September All of these materials will be posted on a share drive accessible to EE faculty members (pending the availability of disk space). Conclusion This report demonstrates a successful completion of the CIF project. As a matter of fact, this project took much more time than what was originally planned in the proposal. I expected the materials developed in this project significantly improve the quality of teaching EE4750. Acknowledgement I would like to thank the CIF committee for giving me this opportunity to work on this project. 6

7 Attachment 1: Review Materials # Boolean Identities (1) X + X = 1, XX = 0, X+X = X, XX = X (2) X(Y+Z) = XY + XZ (distribution law), X + YZ = (X+Y)(X+Z) = X + XZ+ XY + YZ = X(1+Z+Y) + YZ (3) Prove XY + X Z = (X+Z)(X +Y) = XY+X Z+YZ = XY + X Z + YZ(X+X ) = XY+XYZ+X Z+X ZY=XY+X Z (Consensus theorem) (4) DeMorgan s laws: (X1+X2+ + Xn) = X1 X2 Xn (X1X2 Xn) = X1 + X2 + + Xn. (5) X 0 = X, X 1 = X, (X Y) = X Y = X Y = XY + X Y = X Y. Example: Simplify (A+BC)(D+E ) + A (B + C )(D+E ) # K-MAP Location of minter determined by the arrangement of variables: (Answer: D + E ) Minterm: A product term that consists of all variables. Prime Implicant : A product term obtained by combining the maximum number of 1 s 7

8 Essential Prime Impicant : If a 1 is covered by only one prime implicant, it is essential. Simplification of logic functions with 5 or more variables Partial truth table of a 6-variable function: A B C D E F G X X X X X x x x x x x x x x X x x x x X x x 1 G(A, B, C, D, E, F) = m0 + m2 + m3 + Em5 + Em7 + Fm9 + m11 + m15 + (don t cares) = Σm(0, 2, 3, 11, 15) + Σd(1, 10, 13) + E(m5 + m7) + Fm9 Form a KMAP of variables A, B, C and D, and enter the variables E and F inside the map. Suppose a 4-varaible map has variables P1, P2, entered into some squares. Find a sum-of-products expression of the form F = MS0 + P1 MS1 + P2 MS2 + where, 8

9 MS0: minimum sum by setting P1 = P2 = = 0 MS1: minimum sum by setting P1 = 1, Pi = 0 ( i 1) and replacing all 1 s in the map with don t cares. MS2: minimum sum by setting P2 = 1, Pi = 0 ( i 2) and replacing all 1 s in the map with don t cares. With the previous example, the above method would give us G= A B + ACD + EA D + FAD # Typical Combinational Circuits Full Adder X Y C in Co ut Su m X Y + Cin Cout Sum 4-1 MUX 9

10 # Latches & Flip-Flops Latches (1) Clocked SR latch (2) D latch Q + = D 10

11 FFs: State changes occur only at active edges (rising or falling edge) (1) DFF (2) SRFF (same as SR latch except a triangle is added) (3) JKFF (falling edge triggered) O >CLK O.W. (4) TFF (rising edge triggered) >CLK O.W. # State Machine Mealy machine vs. Moore Machine 11

12 State machine design Example 1: Sequence detector Use DFFs to design a sequence detector to identify input sequence

13 13

14 Example 2: convert BCD digit to excess-3 coded decimal digit 14

15 Assumption: Only one bit is inputted in each cycle (starting from the LSB); one bit is outputted in each cycle. Hint: At each cycle, there are two different states: (1) there is a carry from previous cycle; (2) there is no carry from previous cycle. 15

16 Attachment 2: Xilinx Project Navigator Quick Start 1. File New Project. Choose the folder where you want to save the project. 2. In the Project Navigator window (upper left), right click on the project title; this allows you to add existing files and create new sources. 3. You should see all of those files in the project navigator window. Click on any of this source file, the lower left window shows all the process that you can operate on that source file. 4. Now click Create Schematic Symbol. The symbol created can be included in an upper level schematic design file. 5. When making schematic file, you can include symbols of instances or basic logic gates. The pins of each block must be connected to wires (use Add wire icon). The wires can be named using the Add net name icon. Same for single-bit signal and bus. The bus index is given by (x:y). A portion of the bus can be referenced by specifying the index range. NOTE: (i) (ii) The GND and VCC symbols are available in the "General" category in the "Symbols" pane in the schematic editor. Click on schematic file and then click on the View VHDL Functional Model allows you to view the VHDL model of a schematic. 6. Once all files have been put together, you can click Assign Package Pin in Process View window. This allows you assign the I/O to specific pins. The best way to do this is type the location directly. Notice this step will generate Constraints file. After creating this file, if you need to change a pin name in the schematic, you need to edit the Constraints file (click Edit Constraints (Txt) ). Alternatively, you can delete the old file and click Assign Package Pin to create a new one. NOTE: (i) (ii) If a bus is used in schematic design, it is required to assign all of them or none of them to ports. Without performing pin assignments, the pin will be automatically assigned. The Pad Report is available under Place and Route directory in Process View. 7. After the pins are assigned, you can generate the programming file by clicking Configure Device (impact). This pops up a window; use the default Boundary scan, and it should automatically locate two chips in tandem. Choose the corresponding bit stream file for each chip (chip can be bypassed if programming is not needed). Click Operation menu in the impact window and choose Program (you must click on the corresponding device before doing this). The chip should be programmed successfully. Sometimes it may take two tries for a success. When programming the board, the jumpers should not be changed. 8. Any file belonging to a project can be compiled, simulated and tested individually. For instance, after you click on certain file, the process view (lower left) can show what processes you can operate on, including ModelSim (for simulation), Assign Package Pin, Configure Device, etc. 16

17 Attachment 3: Xilinx Project Navigator Quick Start # Asynchronous Sequential Circuit Analysis Sync. Seq. Circuit (state machine): state transition is controlled by clock signal. Async. Seq. Circuit: (1) State transition is solely controlled by inputs. (2) An input change should not be applied before the circuit stabilizes due to a previous input change (just like a state machine requires a maximum clock cycle). Example 1: Async. Seq. circuit with an SR latch (not SRFF). Goal: Given a sequence of inputs (we always assume the input changes one at a time), how can we find the sequence of outputs? (1) Next state and output equations: Q1 + = S1 + R1 Q1 = X1X2 + (X1 + X2)Q1 Q2 + = S2 + R2 Q2 = X1X2 + (X1 + X2 )Q2 Z1 = Q1Q2 + X1 (Q1 + Q2) Z2 = Q1Q2 + X2 (Q1 + Q2 ) (2) Compute State Transition Table: Next state is computed using the equations derived in step 1. Present total state: X1X2Q1Q2; Internal State: Q1Q2. A total state might be stable or unstable. 17

18 If present internal state is the same as next internal state, the corresponding total state is stable. Circled states are stable states; others are unstable states. A change of input corresponds to change of column without any row change; if the new state is unstable, a row change takes place until a stable state is reached. Since before a stable state is reached, the circuit might go thru some unstable state, the state table is often called flow table. There is not necessarily at least one stable in each column (as illustrated by the CYCLE example) (3) Flow table and Output table: (This figure illustrates the concepts of internal states and total states) Flow table Output table With the input sequence: The output sequence is The corresponding timing diagram can be drawn based on the above analysis: 18

19 Example 2: Asynchronous Gate Network. Most important thing is to open the loops; define the output before the delay as next state; delayed outputs become present state. Two methods: (1) Open lower-left corner, middle, and the final output (2) Open lower-right corner, and final output. The corresponding equations (for the following circuit) are: 19

20 (Notice that figure (c) is internal state transition table, rather than total state table) Input sequence in the example is: 00, 01, 11, 10. Example 3: How to open the loop? 20

21 Requirement: Use the minimum number of cuts to open all the loops ( a loop exists if the output of a gate can be fed back to the input of the same gate through some path). Answer: cut at c, d, a or c, d, b. # Cycles and Race Conditions: Example 4: Cycle For the following circuit, if Q1Q2 are at 00 state, and X changes from 0 to 1, the circuit would cycle through a series of unstable states. It would never reach a stable state unless X changes back to 0. Example 5: Race condition If X changes to 0 when Q1Q2 = 10, it requires Q1Q2 changes back to 01. There is a race condition since one latch might change faster than the other. The following figure illustrates all possibilities. 21

22 Noncritical race vs. Critical Race If the resulting stable state is the same no matter in what order the latches change, it is called a noncritical race. If it is possible to end up in two or more different stable states depending on the order in which the flip-flops change state, it is a critical race. Example 6: Critical Race (Suppose initial state is 00, X changes to 1, requiring both Q1 and Q2 change) # Derivation of Primitive Flow Tables o o o o o Primitive flow table: exactly one stable total state per row. The table can be reduced to fewer rows. For most problems it is necessary to start with constructing the primitive flow table, rather than constructing reduced table directly. Assumptions: (1) only one input variable changes at a time (2) Each input change must reach a stable state. 22

23 EXAMPLE 7 An asynchronous network has two inputs and one output. The input sequence XI X2 = 00,01, 11causes the output to become 1. The next input change then causes the output to return to 0. No other input sequence will produce a 1 output. Step 1: Step 2: Notice that when input change from 10 to 11, it can not go to state 4. Step 3: (The output is always associated with stable state. There should be only one stable state in each row.) The corresponding state diagram: 23

24 EXAMPLE 8 Design an edge-triggered clocked T flip-flop, which has two inputs, T and P. The flipflop will change state if T = 1 when the clock (P) changes from 1 to 0. Under all other input conditions, Q should remain constant. We will assume that T and P do not change simultaneously. (Note that the output (Q) only changes when the input changes from TP = 11 to 10) 24

25 Attachment 4: Lab Project Assignments EE 475 Lab Project #2: Synchronous Serial Peripheral Interface Design 1 Specification Presentation on Oct. 26, 2007; Report Due Oct. 29, 2007 Design a synchronous serial peripheral interface (SPI) as described on page in the textbook (Digital Systems Design using VHDL by Roth & John). To accomplish this design, carefully read the description in the textbook to make sure you fully understand the requirements. The whole system should be described in VHDL except for the top-level design, which can be described using schematic. The whole system should be broken down to small components, each of which can be put in a single VHDL file. A recommended schematic is shown in Figure 1. MOSI Sysclk CLK rate generator SPR(1:0) SCK_in SPSHR SPDR ENm LDm RDm DB Master MISO SCK SPSHR SPDR ENs LDs RDs DB Slave MOSI MISO SCK SPI Controller DB SPCR SPSR DB WR RD INT Addr(1:0) Figure 1. A schematic for SPI Most signals in this schematic are self-explanatory except a few: ENm : master enable; MOSI and SCK from master should output Hi-Z if disabled. LDm: Load master; the data on the data bus (DB) is written in SPSHR if LDm is 1. RDm: Read master; the data in SPDR is sent to the DB if RDm is 1. There is a similar set of signals (ENs, LDs, and RDs ) for the slave. 25

26 Addr(1:0), WR, and RD are used to write to or read from the registers SPCR, SPSR, SPSHR, and SPDR.. You are encouraged to implement your own unique design. 2 Testing and Demo Each component must be tested using a test bench to make sure the logic is correct. The overall schematic should be tested using behavior modeling and post place & route modeling, respectively. Notice the behavioral modeling conceptually verifies the design, while the post place & route modeling simulate the design using the actual gate delays. The design should be downloaded to FPGA. The on-board LEDs, seven-segment displays, push buttons and switches can be used in your design for demonstration purpose. During check off, you are supposed to present the following: (1) Behavioral modeling simulation result (2) Post place & route modeling simulation result (3) Demo on the development board Successful accomplishment of the behavioral modeling is needed for you to get a grade C or better. Your final grade depends on how much you can accomplish and how unique your design can be. 3 Report (1) Objective (2) Procedure: Explain how you approach and complete the lab. Please include an ASM chart for the master and slave components, the simulation results, and schematic. The simulation results should be briefly explained. (3) Discussion: Discuss any experience you achieved from this project. (4) The report should be written as formal as possible, e.g., any Figure/Table must have a caption, partition a section into several subsections if there is too much information, etc. EE 475 Lab #3: 8051 CPU Design 1 Objective Presentation: Nov. 16, 2007, Report Due Nov. 19, 2007 The objective of this laboratory project is to design a CPU that implements a subset of the Intel 8051 microprocessor instruction set. 2 Specifications Follow the flow chart discussed in class to design the 8051 CPU (Different implementations are allowed if you have better ideas). Basic requirements: 26

27 (1) All the instructions shown in the flow chart must be implemented (2) The op code must be compatible with Intel 8051 processor (3) A ROM must be used to store the program code (4) A RAM must be used to support instructions accessing internal RAM (5) Simulation of each category of instruction (6) The program code should be generated by compiling an 8051 assembly program using any valid 8051 compiler. Additional requirements: (7) Implement an additional category of instructions. For instance, MOVX instructions (an external RAM block is needed), PUSH/POP operations (SP register must be implemented as well), LCALL / RET operations, etc. (8) Demo your design on the development board Successful accomplishment of basic requirements is needed for a grade of C or better. Your final grade depends on how much you can accomplish and how unique your design can be. 3 Report (5) Objective (6) Procedure: Explain how you approach and complete the lab. Include an ASM chart for the additional category of instructions, and the simulation results of typical instructions. (7) Discussion: Discuss any experience you achieved from this project. (8) The report should be written as formal as possible, e.g., any Figure/Table must have a caption, partition a section into several subsections if there is too much information, etc. (9) Attach the assembly program used to test your design. 27

28 Attachment 5: Homework Assignments EE 4750 HW #1 Due Sept. 17, 2007 Textbook Chapter 1 Problems: 1, 2, 4(b), 9, 10, 11(a)(b), 14(a)(b), 19, 22 NOTE: Ignore the NOR-gate implementation for 11(b) and 14(b). EE 4750 HW #2 Due Sep. 26, 2007 Textbook Chapter 2 Problems: 5, 6, 8, 11, 25. (Simulations required for problems 5, 6, 11). EE 4750 HW #3 Due Oct. 10, 2007 Textbook Chapter 2 Problems: 12, 23, 30, 32, 39 (Simulation results are required for each problem). EE 4750 HW #4 Due Oct. 17, 2007 Textbook Chapter 3 Problems: 5(a), 9, 14 Textbook Chapter 6 Problems: 2, 5, 10 28

29 EE 4750 HW #5 Due Oct. 31, 2007 Use CORE generator to generate the following memory modules and then make a test bench and perform simulation for each module: 1. Distributed RAM (1K bytes); Read and Write; non-registered 2. Distributed RAM (1K 16-bit words); Read only; non-registered 3. Block RAM (2K bytes); Read and Write; non-registered input 4. Block RAM (2K bytes); Read only; non-registered input EE 4750 HW #6 Due Nov. 12, 2007 Rework HW#3 in Verilog; Simulations are required. EE 4750 HW #7 Due Nov. 31, 2007 Textbook Chapter 10 Problems: 1, 3, 11, 18 29