Tri-State Bus Implementation

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Kelley Hubbard
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1 Tri-State Bus Implementation Danny Mok Altera HK FAE

2 Sample Code library ieee; use ieee.std_logic_1164.all; library lpm; use lpm.lpm_components.all; entity tri_bus is port (a,b : in std_logic_vector(7 downto 0); aen, ben : in std_logic; q : out std_logic_vector(7 downto 0)); end tri_bus; architecture tri_bus_body of tri_bus is COMPONENT lpm_bustri GENERIC (LPM_WIDTH: POSITIVE); PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0); enabledt: IN STD_LOGIC := '0'; tridata: INOUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)); END COMPONENT; signal temp : std_logic_vector(7 downto 0); begin u1:lpm_bustri generic map (lpm_width => 8) port map (data => a, enabledt=>aen, tridata=>temp); u2:lpm_bustri generic map (lpm_width => 8) port map (data => b, enabledt=>ben, tridata=>temp); q <= temp; end tri_bus_body;

3 Compile with Max+Plus II u1:lpm_bustri generic map (lpm_width => 8) port map (data => a, enabledt=>aen, tridata=>temp); u2:lpm_bustri generic map (lpm_width => 8) port map (data => b, enabledt=>ben, tridata=>temp);

4 How about Graphic Entry

5 Graphic Entry

6 Compile with Max+Plus II (Altera Device can handle this circuit, the problem is the VHDL Compiler!!!!!????)

7 Modify the VHDL Code

8 Sample Coding library ieee; use ieee.std_logic_1164.all; entity tri_bus1 is port (a,b : in std_logic_vector(7 downto 0); aen, ben : in std_logic; q : out std_logic_vector(7 downto 0)); end tri_bus1; architecture tri_bus1_body of tri_bus1 is signal control : std_logic_vector(1 downto 0); begin control(1) <= aen; control(0) <= ben; process(a,b,control) begin CASE control IS WHEN "10" => q <= a; WHEN "01" => q <= b; WHEN OTHERS => q <= (others => 'Z'); END CASE; end process; end tri_bus1_body;

9 Compile with Max+Plus II

10 Old VHDL code library ieee; use ieee.std_logic_1164.all; library lpm; use lpm.lpm_components.all; entity tri_bus is port (a,b : in std_logic_vector(7 downto 0); aen, ben : in std_logic; q : out std_logic_vector(7 downto 0)); end tri_bus; architecture tri_bus_body of tri_bus is COMPONENT lpm_bustri GENERIC (LPM_WIDTH: POSITIVE); PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0); enabledt: IN STD_LOGIC := '0'; tridata: INOUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)); END COMPONENT; signal temp : std_logic_vector(7 downto 0); begin u1:lpm_bustri generic map (lpm_width => 8) port map (data => a, enabledt=>aen, tridata=>temp); u2:lpm_bustri generic map (lpm_width => 8) port map (data => b, enabledt=>ben, tridata=>temp); q <= temp; end tri_bus_body;

11 How about the other VHDL Compiler

12 Input the EDIF to Max+Plus II

13 Altera VHDL Compiler

14 Deeper look at the Code library ieee; use ieee.std_logic_1164.all; library lpm; use lpm.lpm_components.all; entity tri_bus is port (a,b : in std_logic_vector(7 downto 0); aen, ben : in std_logic; q : out std_logic_vector(7 downto 0)); end tri_bus; architecture tri_bus_body of tri_bus is COMPONENT lpm_bustri GENERIC (LPM_WIDTH: POSITIVE); PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0); enabledt: IN STD_LOGIC := '0'; tridata: INOUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)); END COMPONENT; signal temp : std_logic_vector(7 downto 0); begin u1:lpm_bustri generic map (lpm_width => 8) port map (data => a, enabledt=>aen, tridata=>temp); u2:lpm_bustri generic map (lpm_width => 8) port map (data => b, enabledt=>ben, tridata=>temp); q <= temp; end tri_bus_body; What happen when both aen and ben enable????

15 Point of View - Good/Bad Synopsys FPGA Express does not give me any ERROR or Warning - it is good because it works - it is bad, at least the software should warn me that there may be a conflict Good or Bad? Altera VHDL Compiler give me ERROR - it is good because the software point out that there may be a conflict - it is bad, because I know that there is no conflict

16 Conclusion Different VHDL Compiler having different limitation The VHDL Code in standard (IEEE standard), but different VHDL Compiler will handle differently If VHDL Code is correct but Compiler Error try to modify the VHDL Code (refer to the VHDL Compiler Handbook) try to use the other VHDL Compiler to verify the Coding problem or VHDL Compiler problem

Experiment 8 Introduction to VHDL

Experiment 8 Introduction to VHDL Objectives: Upon completion of this laboratory exercise, you should be able to: Enter a simple combinational logic circuit in VHDL using the Quartus II Text Editor. Assign