AIMS Embedded Systems Programming MT 2017 Micro Architectures

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1 AIS Embedded Systems Programming T 7 icro Architectures Outline X86/Y86 Daniel Kroening AR Pipelining University of Oxford, Computer Science Department emory Version., 4 D. Kroening: AIS Embedded Systems Programming T 7 High-Level View of icroarchitectures CPUs CPU Process a sequential assembler program IP eax ecx ZF... registers ebx... memory module memory module I/O (USB,...) Data held in registers Program controls which data is given to which FU, and where the result is stored Float emory FUs L, L caches data address control Program controls transfer of data between registers and memory Caches speed up access to frequently used memory cells D. Kroening: AIS Embedded Systems Programming T 7 3 D. Kroening: AIS Embedded Systems Programming T 7 4 Instruction Set Architectures These summarise the behavior of a CPU from the point of view of the programmer We will study two ISAs:. CISC: specifically the Y86 (academic variant of Intel s x86). RISC: specifically the AR 3 architecture An ISA describes what the CPU does Ideally as little as possible about how the CPU does it One of the goals of this course is to understand the difference D. Kroening: AIS Embedded Systems Programming T 7 D. Kroening: AIS Embedded Systems Programming T 7 6

2 Visible Registers RA Contains data and the program Y86 Assembler Subset of Intel s x86 assembler Data registers Index Name eax ecx edx ebx esp ebp esi edi Instruction Pointer (IP) Points to address of current instruction Flag registers (ZF,...) Store flags for branches You can run a Y86 program on your x86 machine! The reverse does not work in general, as too many instructions are missing (you are welcome to mend this) D. Kroening: AIS Embedded Systems Programming T 7 7 D. Kroening: AIS Embedded Systems Programming T 7 8 Y86 Instructions Y86 Loads and Stores add/sub: Addition/subtraction of the values in two registers; ZF is set appropriately Loads and stores have a Displacement : ea = esi + Displacement RRmov: copies value of one register into another Rmov: copies value of a register into RA Rmov: copies value from RA into a register The displacement is included in the instruction word as immediate constant jnz: Jumps to relative address if ZF = The register esi is used as offset D. Kroening: AIS Embedded Systems Programming T 7 9 D. Kroening: AIS Embedded Systems Programming T 7 Y86 Instruction Formats Example nemonic Semantics add RD RD+RS Opcode RS RD add eax, edx sub RD RD-RS 9 RS RD Intel convention: the target register is always on the jnz if( ZF) IP IP+Distance 7 Distance left-hand side RRmov RD RS 89 RS RD The target register is a source register, too! Rmov E[ea] RS 89 RS Displacement Semantics: Rmov RS E[ea] 8b RS Displacement eax eax + edx hlt D. Kroening: AIS Embedded Systems Programming T 7 f4 D. Kroening: AIS Embedded Systems Programming T 7

3 Example How do Branches Work? Opcode (Rmov) mov edx, [BYTE one+esi] 8B 6 7 }{{} edx Displacement i f ( a==b ) { T ; } else { F ; } mov eax, [BYTE a+esi ] mov ebx, [BYTE b+esi ] sub eax, ebx jnz f ; ; Code f o r T ; mov eax, [BYTE one+esi ] add eax, eax jnz e f ; ; Code for F ; Semantics: e ;... edx E[esi+7] D. Kroening: AIS Embedded Systems Programming T 7 3 D. Kroening: AIS Embedded Systems Programming T 7 4 Assembler Example Address achine Code Assembler using nemonics 9 F6 sub esi, esi 9C sub eax, eax 4 9DB sub ebx, ebx 6 8B 6 7 l mov edx, [BYTE one+esi] 9 D add eax, edx B C3 add ebx, eax D 89C mov ecx, eax F 8B 6 B mov edx, [BYTE ten+esi] 9D sub ecx, edx 4 7 F jnz l 6 F4 hlt 7 one dd B A ten dd The result is in ebx The NAS Assembler Windows: nasm -f win3 my test.asm link /subsystem:console /entry:start my test.obj Linux: nasm -f elf my test.asm ld -s -o my test my test.o acos: nasm -f macho my test.asm ld -arch i386 -o my test my test.o D. Kroening: AIS Embedded Systems Programming T 7 D. Kroening: AIS Embedded Systems Programming T 7 6 Inline Assembler with Visual Studio Debugging with GDB (Part ) int one =, ten =, r e s u l t ; int main ( ) { asm { sub e s i, e s i sub eax, eax sub ebx, ebx l : mov edx, [ one+e s i ] add eax, edx add ebx, eax mov ecx, eax mov edx, [ ten+e s i ] sub ecx, edx j n z l mov [ r e s u l t+e s i ], ebx } p r i n t f ( Result : %d\n, r e s u l t ) ; return ; } run Start execution x/[size] Label Dump a region of the memory x/[sizei] Label Disassemble some memory region, e. g. x/i $pc info registers Show the value of the registers step Execute one instruction D. Kroening: AIS Embedded Systems Programming T 7 7 D. Kroening: AIS Embedded Systems Programming T 7 8

4 Debugging with GDB (Part ) Debugging with Visual Studio break label set breakpoint at label info break show the breakpoints delete breakpoints number well, delete a breakpoint continue resume the execution after a breakpoint D. Kroening: AIS Embedded Systems Programming T 7 9 D. Kroening: AIS Embedded Systems Programming T 7 Debugging with XCode Extensions: Comparisons We would love to have Y86 commands for i f ( a<b ) {... } These obviously depend on the number representation: with sign > 7 twoc() > twoc() without sign < 9 bin() < bin() D. Kroening: AIS Embedded Systems Programming T 7 D. Kroening: AIS Embedded Systems Programming T 7 Reminder: Number Interpretation Binary representation: Two s complement: bin() : {, } n {,..., n } n bin(x) = x i i i= twoc() : {, } n { n,..., n } twoc(x) = n x n + bin(x n,..., x ) Comparing Unsigned Integers Unsigned integers: bin(a) < bin(b) bin(a) bin(b) < Recall: b = ( b) + We get the + for free by setting the carry-in of the adder. Let s pretend we compute with one more bit ( zero extension ): a n... a a + b n... b b c n c n... c (carry bits) = s n s n... s s (sum) Thus: bin(a) bin(b) < s n c n D. Kroening: AIS Embedded Systems Programming T 7 3 D. Kroening: AIS Embedded Systems Programming T 7 4

5 Comparing Signed Integers Two s complement: twoc(a) < twoc(b) twoc(a) twoc(b) < Again, let s pretend we have an extra bit ( sign extension ): a n a n... a a + b n b n... b b c n c n... c (carry bits) = s n s n... s s (sum) Thus: twoc(a) twoc(b) < s n a n b n c n s n c n c n New Flags: CF, SF, OF We introduce three new flags for arithmetic operations: CF: The carry flag (c n in case of additions, c n in case of subtraction) SF: The sign flag (s n ) OF: The overflow flag (c n c n ) meaning Intel did so D. Kroening: AIS Embedded Systems Programming T 7 D. Kroening: AIS Embedded Systems Programming T 7 6 Examples (Part ) Examples (Part )... = +... =... =... =... =... =... =... =... = +... =... =... = ZF =, CF =, SF =, OF = ZF =, CF =, SF =, OF = ZF =, CF =, SF =, OF =... = n +... =... =... = n ZF =, CF =, SF =, OF =... = n... =... =... = n ZF =, CF =, SF =, OF = D. Kroening: AIS Embedded Systems Programming T 7 7 D. Kroening: AIS Embedded Systems Programming T 7 8 Branching Instructions for Comparisons Instruction jz, je jnz, jne jnae, jb jae, jnb jna, jbe ja, jnbe jnge, jl jge, jnl jng, jle jg, jnle jmp near Flags ZF ZF CF CF CF ZF (CF ZF) SF OF (SF OF) ((SF OF) ZF) ((SF OF) ZF) unconditional n = not, z = zero, e = equal, g = greater, l = less, a = above, b = below i.e. jnbe = jump if not (below or equal) Branching Instructions for Comparisons sub ax, bx Jxxx t a r g e t... t a r g e t : branch if with sign without sign ax = bx je je ax bx jne jne ax > bx jg ja ax bx jge jae ax < bx jl jb ax bx jle jbe D. Kroening: AIS Embedded Systems Programming T 7 9 D. Kroening: AIS Embedded Systems Programming T 7 3

6 Example Branching Instructions s t a r t sub esi, esi ; array index mov edx, [BYTE Intmax+esi ] ; inimum mov ecx, [BYTE Top+esi ] ; top index sub ebx, ebx ; counter L mov eax, ebx sub eax, ecx jae end ; counter Top? mov esi, ebx mov edi, [BYTE Array+esi ] ; edi :=array[ebx] mov eax, edi sub eax, edx jge s k i p ; array[ebx] inimum? Example Branching Instructions (Part ) Four dd 4 Top dd 4 Array dd,, 3, 4,, 6, 7, 8, 9, Intmax dd x 7 f f f f f f f mov edx, edi ; inimum:= array[ebx] s k i p sub esi, esi mov eax, [BYTE Four+esi ] add ebx, eax ; counter+=4 D. Kroening: AIS Embedded jmp Systems near Programming L T 7 3 D. Kroening: AIS Embedded Systems Programming T 7 3 end hlt History AR AR Today 98s: Acorn Computers 98: BBC icro (8 bit) 986: AR development kit 99: AR, Advanced RISC achines, founded; owners: Acorn Computers, Apple and VLSI Technology Now primarily licensed as IP, with focus on low-end embedded systems and phones (>9 % market share) Built by Apple, Nvidia, Qualcomm, Samsung, TI 3: 37 billion AR processors produced Early 64-bit prototypes for application in low-power servers D. Kroening: AIS Embedded Systems Programming T 7 33 D. Kroening: AIS Embedded Systems Programming T 7 34 Visible Data Basic Instructions RA, organised in 3-bit words Registers R to R R is a special case: this is the PC R3 is the stack pointer (SP) R4 is used for the return address for function calls (LR) CPSR for various flags (There is another register file for floating-point numbers) ADD R d, R n, R m R d R n + R m SUB R d, R n, R m R d R n R m UL R d, R m, R s R d (R m R s )[3 : ] SUL R dl, R dh, R m, R s R dh, R dl R m R s UUL R dl, R dh, R m, R s R dh, R dl R m R s SDIV R d, R m, R s R d R m /R s UDIV R d, R m, R s R d R m /R s AND R d, R n, R m R d R n & R m B label PC label BL label LR P C +4; PC label BX R m BX R m any variants! D. Kroening: AIS Embedded Systems Programming T 7 3 D. Kroening: AIS Embedded Systems Programming T 7 36

7 Setting Condition Flags Using Condition Flags ost instructions can be given a suffix S. In addition to the usual behaviour, the condition flags (in CPSR) are updated N Z C V ost instructions can be given condition suffixes: EQ equal NE not equal CS/HS carry set CC/LO carry clear I negative PL positive (or zero) VS overflow VC no overflow HI higher LS lower or same GE greater or equal LT less than GT greater than LE less than or equal N = negative, Z = zero, C = carry, V = overflow These use 4 bits in the instruction word. D. Kroening: AIS Embedded Systems Programming T 7 37 D. Kroening: AIS Embedded Systems Programming T 7 38 AR Instruction Formats AR Instruction Formats AR uses a fixed-size instruction word: Cond Opcode S R n R d R m data processing There is a compressed version called Thumb- Instruction Set The instructions have 6 bit Cond L offset branch and branch&link Fewer options, conditions are a separate instruction Aimed at better I-Cache efficiency D. Kroening: AIS Embedded Systems Programming T 7 39 D. Kroening: AIS Embedded Systems Programming T 7 4 Sequential Processors with Pipeline We will start with an implementation that has the form and shape of a pipeline, but processes one instruction at a time processes the instructions in a fixed order of phases These aren t built, but only exist for illustrative purposes. But: The step to a proper pipeline is minimal (will show!) The Instruction Phases (Stages). Instruction Fetch () The instruction is copied from the RA into a register (). Instruction Decode () Loads the values of the operands from the register file into registers A and B; also increments the program counter 3. Execute () Perform any operation (say add/sub), address arithmetic for /store 4. emory () RA access for /store. Write-Back () Store any result in the register file D. Kroening: AIS Embedded Systems Programming T 7 4 D. Kroening: AIS Embedded Systems Programming T 7 4

8 An Implementation: High-level View Sequential Execution IP We first implement a sequential machine: The stages are processed one after the other in the order AR DRw C We execute exactly one instruction at a time In contrast to multi-cycle designs: We stick to this even if an instruction doesn t actually use a particular stage D. Kroening: AIS Embedded Systems Programming T 7 43 D. Kroening: AIS Embedded Systems Programming T 7 44 Sequential Execution Example: Processing add Let I, I,... be the sequence of instructions in program order. time I I I I I I E I I I mov [+esi], edx AR IP DRw C D. Kroening: AIS Embedded Systems Programming T 7 4 D. Kroening: AIS Embedded Systems Programming T 7 46 Example: Processing add () Example: Processing add () mov [+esi], edx AR IP DRw C mov [+esi], edx 9, 6 IP AR DRw C add, 3 D. Kroening: AIS Embedded Systems Programming T 7 47 D. Kroening: AIS Embedded Systems Programming T 7 48

9 Example: Processing add (3) Example: Processing add (4) add add mov [+esi], edx IP 9, 6 3 AR DRw C 3 mov [+esi], edx AR IP DRw C 3 D. Kroening: AIS Embedded Systems Programming T 7 49 D. Kroening: AIS Embedded Systems Programming T 7 Example: Processing add () Example: Processing Rmov add 4 mov [+esi], edx AR IP DRw C 3 mov [+esi], edx AR IP DRw C D. Kroening: AIS Embedded Systems Programming T 7 D. Kroening: AIS Embedded Systems Programming T 7 Example: Processing Rmov () Example: Processing Rmov () mov [+esi], edx AR IP DRw C 6 mov [+esi], edx, 3 Rmov IP AR DRw C 6, D. Kroening: AIS Embedded Systems Programming T 7 3 D. Kroening: AIS Embedded Systems Programming T 7 4

10 Example: Processing Rmov (3) Example: Processing Rmov (4) Rmov Rmov 7 mov [+esi], edx IP, 3 3 AR DRw C 8 mov [+esi], edx AR IP DRw C 3 D. Kroening: AIS Embedded Systems Programming T 7 D. Kroening: AIS Embedded Systems Programming T 7 6 Example: Processing Rmov () Example: Processing jnz Rmov 9 mov [+esi], edx AR IP DRw C jnz l the distance is AR IP DRw C D. Kroening: AIS Embedded Systems Programming T 7 7 D. Kroening: AIS Embedded Systems Programming T 7 8 Example: Processing jnz () Example: Processing jnz () jnz l the distance is AR IP DRw C jnz l the distance is AR IP DRw C jnz D. Kroening: AIS Embedded Systems Programming T 7 9 D. Kroening: AIS Embedded Systems Programming T 7 6

11 Example: Processing jnz (3) Example: Processing jnz (4) jnz jnz jnz l the distance is AR IP DRw C 3 jnz l the distance is AR IP DRw C D. Kroening: AIS Embedded Systems Programming T 7 6 D. Kroening: AIS Embedded Systems Programming T 7 6 Example: Processing jnz () Pipelining Increases the performance using the assembly-line idea jnz 4 jnz l the distance is AR IP DRw C performance = instructions per cycle clock frequency }{{}}{{} IPC /τ Standard technique in virtually all modern circuitry (not just CPUs, but also GPUs, video, networking, wireless,...) D. Kroening: AIS Embedded Systems Programming T 7 63 D. Kroening: AIS Embedded Systems Programming T 7 64 Pipelining time 3 4 I I I 3 I 4 I I 6 I I I 3 I 4 I I I I 3 I 4 E I I I 3 I I Best case: one instruction per cycle! Pipelining Performance Performance: IPC τ IPC τ D FF + D n where: IPC : instructions per cycle τ: cycle time n: # stages D: combinational delay without the flip flops D. Kroening: AIS Embedded Systems Programming T 7 6 D. Kroening: AIS Embedded Systems Programming T 7 66

12 Implementing the Pipeline: Roadmap Resource Conflicts Let s look at our sequential machine again:. Resolving resource conflicts. odifying the control 3. Dealing with data and control hazards IP AR DRw C Consider the C register of an instruction followed by another instruction! once the nd instruction is fetched? D. Kroening: AIS Embedded Systems Programming T 7 67 D. Kroening: AIS Embedded Systems Programming T 7 68 Register Lifetime Register Lifetime IP AR DRw C W R R R R W R IP R W AR W R DRw W R C W R R Flags R W W R eax... R W IP AR DRw C3 C4 3 4 We resolve by replication! Problem: and C need to be remembered for multiple stages! D. Kroening: AIS Embedded Systems Programming T 7 69 D. Kroening: AIS Embedded Systems Programming T 7 7 Resource Conflicts Example Pipeline Q: Which other resources are shared by stages? A: The (shared by and E)! Q: What do we do? A: ost CPUs have an L-cache that permits two (read-)accesses simultaneously. (Really two L caches: an I- and a D-cache) program (modified): mov [+esi], ecx IP AR DRw C3 C4 3 4 D. Kroening: AIS Embedded Systems Programming T 7 7 D. Kroening: AIS Embedded Systems Programming T 7 7

13 Example Pipeline () Example Pipeline () program (modified): mov [+esi], ecx IP AR DRw C3 3 program (modified): mov [+esi], ecx 9, 6 IP AR DRw C3 add 3 C4 4 C4 4, 3 D. Kroening: AIS Embedded Systems Programming T 7 73 D. Kroening: AIS Embedded Systems Programming T 7 74 Example Pipeline (3) Example Pipeline (4) program (modified): mov [+esi], ecx, IP 9, 6 3 AR DRw C3 Rmov add 3 3 program (modified): mov [+esi], ecx IP, AR DRw C3 3 Rmov 3 add C4 4 C4 4 6, D. Kroening: AIS Embedded Systems Programming T 7 7 D. Kroening: AIS Embedded Systems Programming T 7 76 Example Pipeline () Example Pipeline (6) 4 program (modified): mov [+esi], ecx AR DRw C3 IP 3 Rmov program (modified): mov [+esi], ecx IP AR DRw C3 3 C4 3 4 add C4 4 Rmov D. Kroening: AIS Embedded Systems Programming T 7 77 D. Kroening: AIS Embedded Systems Programming T 7 78

14 Data and Control Dependencies Example program with data dependency: add edx, ebx mov [+ esi ], edx Execution in the pipeline: Like that? time mov [+esi], edx E Data and Control Dependencies Example program with data dependency: add edx, ebx mov [+ esi ], edx Execution in the pipeline: time 3... mov [+esi], edx BUBBLE E D. Kroening: AIS Embedded Systems Programming T 7 79 D. Kroening: AIS Embedded Systems Programming T 7 8 emory RA in PCs RO: read-only memory RA: random-access memory (but usually means random-access read and write memory) 3 pin SI 7 pin SI icrodi 84 pin RABus RI SRA: static RA stores state as long as power is supplied pin DI 7 pin SODI 44 pin SDRA SODI pin DDR SODI pin DDR- SODI DRA: dynamic RA implemented using capacitors; the state is lost without periodic refresh 68 pin SDRA DI 84 pin DDR DI 4 pin DDR- DI D. Kroening: AIS Embedded Systems Programming T 7 8 D. Kroening: AIS Embedded Systems Programming T 7 8 Addresses Structure WE DATA RA address RA/RO-Chips store many (billions of) bits Distinguish using an address The address is given in binary Plus WE: read/write The data pins are used for reading as well as writing decoder 4 decoder address RA/RO chips are a D matrix The address is split into a row and column The binary encoding is turned into unary using a decoder D. Kroening: AIS Embedded Systems Programming T 7 83 D. Kroening: AIS Embedded Systems Programming T 7 84

15 SRA Cell with Two Inverters SRA Cell in COS Address Line Address Line VDD Data Data Reading and writing Address line selects the cell State is held using the inverters (latch) Read by comparing Data and Data GND Data Data D. Kroening: AIS Embedded Systems Programming T 7 8 D. Kroening: AIS Embedded Systems Programming T 7 86 DRA Reminder: Capacitors DRA uses capacitors more simplistic and easier to build than SRA high density, low cost But: slower! charging discharging charge % time fast but expensive SRA for caches (more on that later) slow but inexpensive DRA for the main memory Store an electric charge but only for limited time D. Kroening: AIS Embedded Systems Programming T 7 87 D. Kroening: AIS Embedded Systems Programming T 7 88 DRA Cell Data Buses Address Line Connecting multiple memory chips: memory module CPU memory module GND Data memory module A bit is stored as a capacity and has to be refreshed periodically No! I/O pins are expensive! D. Kroening: AIS Embedded Systems Programming T 7 89 D. Kroening: AIS Embedded Systems Programming T 7 9

16 Data Buses Interface RA Chips Goal: effective use of the pricey wires Idea: share wires for data and among RA modules Control signals: CS (Chip Select) activates a particular chip WE (Write Enable) OE (Output Enable) memory module memory module memory module Inactive chips have high-impedance outputs (Z) CPU data address control Write by setting WE, read by setting OE Interface constraint: OE and WE are never both active D. Kroening: AIS Embedded Systems Programming T 7 9 D. Kroening: AIS Embedded Systems Programming T 7 9 Write Cycle Read Cycle CS W E OE Address CS W E OE Address Data valid Data valid D. Kroening: AIS Embedded Systems Programming T 7 93 D. Kroening: AIS Embedded Systems Programming T 7 94 Row- und Column-Address-Strobes RAS/CAS Write Cycle Idea: save even more wires by sending the address in two (or more) steps Address Row Col RAS Typical: row and column are sent separately CAS W E RAS: Row Address Strobe, CAS: Column Address Strobe Data valid D. Kroening: AIS Embedded Systems Programming T 7 9 D. Kroening: AIS Embedded Systems Programming T 7 96

17 RAS/CAS Read Cycle Bus-Bursts Address Row Col RA has long latency RA is often accessed sequentially RAS CAS W E Caches therefore are arranged in lines: a sequence of consecutive (e.g. 6 bytes) Data valid Bus-bursts: efficient transmission of an entire cache line D. Kroening: AIS Embedded Systems Programming T 7 97 D. Kroening: AIS Embedded Systems Programming T 7 98 Bus-Bursts Double Data Rate (DDR) RA Address Row Col Address Row Col RAS RAS CAS CAS OE OE DATA D D D D3 DATA D D D D3 CLK CLK CAS Latency (CL) CAS Latency (CL) D. Kroening: AIS Embedded Systems Programming T 7 99 D. Kroening: AIS Embedded Systems Programming T 7 Timings Timings 4GB 8Hz DDR Non-ECC CL (---) DI (Kit of ) 4GB 8Hz DDR Non-ECC Low-Latency CL4 (4-4-4-) DI (Kit of ) 4GB 66Hz DDR Non-ECC CL (---) DI (Kit of ) 4GB 66Hz DDR Non-ECC CL (---) DI (Kit of ) Tall HS 4GB 66Hz DDR Non-ECC CL (---) DI (Kit of 4) 8GB 8Hz DDR Non-ECC Low-Latency CL4 (4-4-4-) DI (Kit of 4) HyperX DDR3 37Hz, 6HZ, 6Hz, 8Hz, 866Hz and Hz Description GB 37Hz DDR3 Non-ECC Low-Latency CL7 (7-7-7-) DI GB 6Hz DDR3 Non-ECC CL9 ( ) DI GB 6Hz DDR3 Non-ECC Low-Latency CL7 (7-7-7-) DI GB 6Hz DDR3 Non-ECC Low-Latency CL7 (7-7-7-) DI GB 8Hz DDR3 Non-ECC CL8 ( ) DI GB 8Hz DDR3 Non-ECC CL8 ( ) DI GB 37Hz DDR3 Non-ECC CL9 (9-9-9) DI (Kit of ) GB 37Hz DDR3 Non-ECC Low-Latency CL7 (7-7-7-) DI GB 37Hz DDR3 Non-ECC CL7 (7-7-7-) DI (Kit of ) GB 37Hz DDR3 Non-ECC CL7 (7-7-7-) DI (Kit of ) Intel XP GB 6Hz DDR3 Non-ECC CL9 ( ) DI GB 6Hz DDR3 Non-ECC CL9 ( ) DI (Kit of ) GB 6Hz DDR3 Non-ECC Low-Latency CL7 (7-7-7-) DI GB 6Hz DDR3 Non-ECC Low-Latency CL7 (7-7-7-) DI (Kit of ) GB 6Hz DDR3 Low Latency CL8 (8-7-7-) DI (Kit of ) NVIA SLI KHX64DK/4G KHX64DLLK/4G KHX8DK/4G KHX8DTK/4G KHX8DK4/4G KHX64DLLK4/8G Part Number KHXD3LL/G KHX8D3/G KHX3D3LL/G KHX3AD3LL/G KHX44D3/G KHX44AD3/G KHXD3K/G KHXD3LL/G KHXD3LLK/G KHXD3LLK/GX KHX8D3/G KHX8D3K/G KHX3D3LL/G KHX3D3LLK/G KHX3D3LLK/GN Example: --- Current standard:. CAS Latency. RAS-to-CAS Delay 3. RAS Precharge 4. Act-to-Precharge Delay D. Kroening: AIS Embedded Systems Programming T 7 D. Kroening: AIS Embedded Systems Programming T 7

18 Caches Caches: Overview Recall: DRA slow/cheap, SRA fast/pricey 3 46 Idea: use SRA as fast cache for lots of DRA Hides the latency of the slow DRA cache line index offset 3 tag Usually good hit rates >9 % cache... main memory D. Kroening: AIS Embedded Systems Programming T 7 3 D. Kroening: AIS Embedded Systems Programming T 7 4 Caches: Hashing Collisions Q: How to map the? Easiest answer: use least-significant bits address = tag index offset tag: distinguishes lines with same index index: address in cache offset: distinguishes words in cache line cache line 3 index tag tag D. Kroening: AIS Embedded Systems Programming T 7 D. Kroening: AIS Embedded Systems Programming T 7 6 Overview of Design Options for Caches Cache Size size line size number of bytes stored together allocation policy when is a new entry created? associativity length of list in hash table replacement policy which entries to purge (sectoring) write policy write through or write back split I/D cache or unified I/D cache Bigger cache better hit rate Bigger caches are also more expensive and have longer paths Partially addressed by hierarchy (more on that later) We will have more options once hierarchy is added. D. Kroening: AIS Embedded Systems Programming T 7 7 D. Kroening: AIS Embedded Systems Programming T 7 8

19 Line Size Associativity Observation: memory accesses are clustered I.e., the subsequent accesses are often next to each other Cache entries have overhead: address bits plus flag bits Also remember the latency of memory! Also called ways An n-way cache can store n entries with the same address hash Reduce overhead by making cache entry bigger Think of the length of the list in a hash table Typical size: 64 bytes ( bits) This reduces the number of collisions D. Kroening: AIS Embedded Systems Programming T 7 9 D. Kroening: AIS Embedded Systems Programming T 7 Associativity Cache Hierarchies tag cache line 3 3 index -way cache tag Recall that fast SRA is expensive, and bigger caches have long paths Thus: build a cache for the cache L: closest to CPU L, L3, L4: cache the next level Caches get bigger the closer they get to the memory D. Kroening: AIS Embedded Systems Programming T 7 D. Kroening: AIS Embedded Systems Programming T 7 Statistics odel Year L Cache L Cache L3 Cache L4 Cache 8486DX KB joint Pentium KB+8 KB Pentium Pro 99 8 KB+8 KB. B Pentium X KB+6 KB Pentium II KB+6 KB. B Xeon KB+8 KB. B Pentium III KB+6 KB. B Pentium 4 6 KB+6 KB.. B Itanium 6 KB+6 KB. 9 B or 4 B Pentium 3 3 KB+3 KB. B Core Duo 6 3 KB+3 KB B Core i7 8 3 KB+3 KB. B 8 B Core i 9 3 KB+3 KB. B 8 B Core i3 3 KB+3 KB. B 4 B Atom SoC 3 KB+4 KB. B Core 4. B 3 B 8 B Numbers are per core unless shared. D. Kroening: AIS Embedded Systems Programming T 7 3