9/25/ Software & Hardware Architecture

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1 8086 Software & Hardware Architecture 1

2 INTRODUCTION It is a multipurpose programmable clock drive register based integrated electronic device, that reads binary instructions from a storage device called memory as input & process the data according to those instructions and provides results as output. It has decision making capability & it do operations in micro seconds. 2 2

3 Topics to be covered 1. Software Architecture of the INTEL Hardware Architecture of INTEL Programming and program development. 3 3

4 Software architecture of the INTEL 8086 Memory segmentation and addressing Block diagram of 8086 Address space & Data organization Data Types Registers Stack I/O space 4 4

5 Hardware Architecture of INTEL 8086 Pin Diagram and Pin Details min/max mode Coprocessor and Multiprocessor configuration Hardware organization of address space Control signals I/O interfaces 5 5

6 8086 programmingand program development. Assembly Language Programming. Instruction Set. Assembler Directives. Programming Exercises. 6 6

7 Software Architecture of INTEL 8086 Microprocessor & Microcontroller 7 7

8 It is a 16-bit μp. Features 8086 has a 20 bit address bus can access up to 2 20 memory locations (1 MB). It can support up to 64K I/O ports. It provides 14, 16 -bit registers. Word size is 16 bits. It has multiplexed address and data bus AD0- AD15 and A16 A19. It requires single phase clock with 33% duty cycle to provide internal timing. 8 8

9 8086 is designed to operate in two modes, Minimum and Maximum. It can prefetchesup to 6instruction bytes from memory and queues them in order to speed up instruction execution. It requires +5V power supply. A 40 pin dual in line package. 9 9

10 Intel 8086 Internal Architecture 10 10

11 Internal architecture of has two blocks BIUand EU. The BIU handles all transactions of data and addresses on the buses for EU. The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction system byte queue

12 Both units operate asynchronouslyto give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register

13 EXECUTION UNIT Decodes instructions fetched by the BIU Generate control signals, Executes instructions. The main parts are: Control Circuitry Instruction decoder ALU 13 13

14 Register EXECUTION UNIT General Purpose Registers Purpose AX Word multiply, word divide, word I /O AL Byte multiply, byte divide, byte I/O, decimal arithmetic AH Byte multiply, byte divide BX Store address information CX String operation, loops CL Variable shift and rotate DX Word multiply, word divide, indirect I/O (Used to hold I/O address during I/O instructions. If the result is more than 16-bits, the lower order 16-bits are stored in accumulator and higher order 16-bits are stored in DX register) 14 14

15 Pointer And Index Registers used to keep offset addresses. Used in various forms of memory addressing. In the case of SP and BP the default reference to form a physical address is the Stack Segment (SS-will be discussed under the BIU) The index registers (SI& DI) and the BX generally default to the Data segment register (DS). SP: Stack pointer Used with SS to access the stack segment BP: Base Pointer Primarily used to access data on the stack Can be used to access data in other segments 15 15

16 SI: Source Index register is required for some string operations When string operations are performed, the SI register points to memory locations in the data segment which is addressed by the DS register. Thus, SI is associated with the DS in string operations. DI: Destination Index register is also required for some string operations. When string operations are performed, the DI register points to memory locations in the data segment which is addressed by the ES register. 16 Thus, DI is associated with the ES in string 16

17 EXECUTION UNIT Flag Register Flag Carry (CF) Parity (PF) Purpose Holds the carry after addition or the borrow after subtraction. Also indicates some error conditions, as dictated by some programs and procedures. PF=0;odd parity, PF=1;even parity. Auxiliary (AF) Zero (ZF) Sign (SF) Holds the carry (half carry) after addition or borrow after subtraction between bit positions 3 and 4 of the result (for example, in BCD addition or subtraction.) Shows the result of the arithmetic or logic operation. Z=1; result is zero. Z=0; The result is 0 Holds the sign of the result after an arithmetic/logic instruction execution. S=1; negative, S=

18 Flag Trap (TF) Interrupt (IF) Direction (DF) Overflow (OF) Purpose A control flag. Enables the trapping through an on-chip debugging feature. A control flag. Controls the operation of the INTR (interrupt request) I=0; INTR pin disabled. I=1; INTR pin enabled. A control flag. It selects either the increment or decrement mode for DI and /or SI registers during the string instructions. Overflow occurs when signed numbers are added or subtracted. An overflow indicates the result has exceeded the capacity of the Machine 18 18

19 Execution unit Flag Register Sixof the flags are status indicators reflecting properties of the last arithmetic or logical instruction. For example, if register AL = 7Fh and the instruction ADD AL,1 is executed then the following happen AL = 80h CF = 0; there is no carry out of bit 7 PF = 0; 80h has an odd number of ones AF = 1; there is a carry out of bit 3 into bit 4 ZF = 0; the result is not zero SF = 1; bit seven is one OF = 1; the sign bit has changed 19 19

20 BUS INTERFACE UNIT (BIU) Contains 6-byte Instruction Queue (Q) The Segment Registers (CS, DS, ES, SS). The Instruction Pointer (IP). The Address Summing block (Σ) 20 20

21 Segmented Memory The memory in an 8086/88 based system is organized as segmented memory Physical Memory Code segment (64KB) The CPU 8086 is able to address 1Mbyte of memory. The Complete physically available memory may be divided into a number of logical segments. FFFFF Data segment (64KB) Extra segment (64KB) Stack segment (64KB) 1 MB 21 21

22 The 4 segments are Code, Data, Extra and Stack segments. A Segment is a 64kbyte block of memory. The 16 bit contents of the segment registers in the BIU actually point to the starting locationcular segment. Segments may be overlapped or non-overlapped Advantages of Segmented memory Scheme Allows the memory capacity to be 1Mb although the actual addresses to be handled are of 16 bit size. Allows the placing of code, data and stack portions of the same program in different parts (segments) of the m/y, for data and code protection. Permits a program and/or its data to be put into different areas of memory each time program is executed, i.e. provision for relocation may be done. 22 The segment registers are used to allow the instruction, data or stack portion of 22

23 Segment registers In 8086/88 the processors have 4 segments registers Code Segment register (CS), Data Segment register (DS), Extra Segment register (ES) and Stack Segment (SS) register. All are 16 bit registers. Each of the Segment registers store the upper 16 bit address of the starting address of the corresponding segments

24 24 24

25 MEMORY BIU Segment Registers CSR 34BA DSR 44EB ESR 54EB 695E SSR 34BA0 44B9F 44EB0 54EAF 54EB0 64EAF 695E0 795DF CODE (64k) DATA (64K) EXTRA (64K) STACK (64K) 1 MB Each segment register store the upper 16 bit of the starting address of the segments 25 25

26 26 26

27 Segment and Address register combination CS:IP SS:SP SS:BP DS:BX DS:SI DS:DI (for other than string operations) ES:DI (for string operations) 27 27

28 Block diagram of 8086 RCET Microprocessor & Microcontroller 28 28

29 Block diagram of 8086 RCET Microprocessor & Microcontroller 29 29

30 General Purpose Registers AX - the Accumulator BX -the Base Register CX -the Count Register DX -the Data Register Normally used for storing temporary results Each of the registers is 16 bits wide (AX, BX, CX, DX) Can be accessed as either 16 or 8 bits AX, AH, AL 30 30

31 General Purpose Registers AX Accumulator Register Preferred register to use in arithmetic, logic and data transfer instructions because it generates the shortest Machine Language Code Must be used in multiplication and division operations Must also be used in I/O operations BX Base Register Also serves as an address register 31 31

32 General Purpose Registers CX Count register Used as a loop counter Used in shift and rotate operations DX Data register Used in multiplication and division Also used in I/O operations 32 32

33 Pointer and Index Registers All 16 bits wide, L/H bytes are not accessible Used as memory pointers Example: MOV AH, [SI] Move the byte stored in memory location whose address is contained in register SI to register AH IP is not under direct control of the programmer 33 33

34 Flag Register Overflow Direction Parity Carry Interrupt enable Trap Sign Zero Auxiliary Carry 6 are status flags 3 are control flag 34 34

35 8086 Programmer s Model BIU registers (20 bit adder) ES CS SS DS IP Extra Segment Code Segment Stack Segment Data Segment Instruction Pointer EU registers AX BX CX DX AH BH CH DH SP BP SI DI FLAGS AL BL CL DL Accumulator Base Register Count Register Data Register Stack Pointer Base Pointer Source Index Register Destination Index Register 35 35

36 The Stack The stack is used for temporary storage of information such as data or addresses. When a CALL is executed, the 8086 automatically PUSHes thecurrentvalueofcsandipontothe stack. Other registers can also be pushed Before return from the subroutine, POP instructions can be used to pop values back from the stack into the corresponding registers

37 The Stack 37 37

38 Hardware Architecture of INTEL

39 Hardware Architecture of INTEL 8086 Pin Diagram and Pin Details min/max mode Hardware organization of address space Control signals Coprocessor and Multiprocessor configuration I/O interfaces 39 39

40 INTEL Pin Diagram Microprocessor & Microcontroller 40 40

41 INTEL Pin Details Ground Clock Duty cycle: 33% Power Supply 5V ±10% Reset Registers, seg regs, flags CS: FFFFH, IP: 0000H If high for minimum 4 clks Microprocessor & Microcontroller 41 41

42 INTEL Pin Details Address/Data Bus: Contains address bits A 15 -A 0 when ALE is 1 & data bits D 15 D 0 when ALE is 0. Address Latch Enable: When high, multiplexed address/data bus contains address information. Microprocessor & Microcontroller 42 42

43 INTEL Pin Details INTERRUPT Non -maskable interrupt Interrupt acknowledge Interrupt request Microprocessor & Microcontroller 43 43

44 INTEL Pin Details Direct Memory Access Hold Hold acknowledge Microprocessor & Microcontroller 44 44

INTEL 8086 -Pin Details Address/Status Bus Address bits A 19 A

45 INTEL Pin Details Address/Status Bus Address bits A 19 A 16 & Status bits S 6 S 3 Microprocessor & Microcontroller 45 45

46 INTEL Pin Details BHE#, A 0 : 0,0: Whole word (16-bits) 0,1: High byte to/from odd address 1,0: Low byte to/from even address Bus High Enable/S7 Enables most significant data bits D 15 D 8 during read or write operation. S 7 : Always 1. 1,1: No selection Microprocessor & Microcontroller 46 46

47 INTEL Pin Details Min/Max mode Minimum Mode: +5V Maximum Mode: 0V Minimum Mode Pins Maximum Mode Pins Microprocessor & Microcontroller 47 47

48 Minimum Mode- Pin Details Read Signal Write Signal Memory or I/0 Data Transmit/Receive Microprocessor & Microcontroller Data Bus Enable 48 48

49 Maximum Mode - Pin Details S2 S1 S0 000: INTA 001: read I/O port 010: write I/O port 011: halt 100: code access 101: read memory 110: write memory 111: none -passive Status Signal Inputs to 8288 to generate eliminated signals due to max mode. Microprocessor & Microcontroller 49 49

50 Maximum Mode - Pin Details Lock Output Used to lock peripherals off the system Activated by using the LOCK: prefix on any instruction DMA Request/Grant Lock Output Microprocessor & Microcontroller 50 50

51 Maximum Mode - Pin Details QS1 QS0 00: Queue is idle 01: First byte of opcode 10: Queue is empty 11: Subsequent byte of opcode Queue Status Used by numeric coprocessor (8087) Microprocessor & Microcontroller 51 51

52 Minimum Mode 8086 System Microprocessor & Microcontroller 52 52

53 Maximum Mode 8086 System Microprocessor & Microcontroller 53 53

54 Flow Control Instructions - Cont. Single-flag jumps JS jump if sign negative JNS jump if nonnegative sign JP/JPE jump if parity even JNP/JPO jump if parity odd Jump based on CX JCXZ Loop Instructions Loop Loopnz/Loopne Loopz/Loope All jump instructions have no effect on the flags. 54

55 Branching Structures: IF-Then Example: If AX < 0 Then Replace AX by AX ENDIF ; if AX < 0 ;then END_IF: CMP AX, 0 JNL END_IF NEG AX 55

56 Example: If AL <= BL Then Display character in AL Else Display character in BL ENDIF IF-Then-Else ; if AL<=BL ;then ELSE_: DISPLAY: END_IF: MOV AH, 2 CMP AL, BL JNBE ELSE_ MOV DL, AL JMP DISPLAY MOV DL, BL INT 21H 56

57 CASE Example: CASE AX <0: put 1 in BX =0: put 0 in BX >0: put 1 in BX END_CASE ; case AX CMP AX, 0 JL NEGATIVE JE ZERO JG POSITIVE NEGATIVE: MOV BX, -1 JMP END_CASE ZERO: MOV BX, 0 JMP END_CASE POSITIVE: MOV BX, 1 END_CASE: 57

58 CASE Cont. Example: CASE AL 1,3: display o 2,4: display e END_CASE ; case AL CMP AL, 1 ; 1, 3: JE ODD CMP AL, 3 JE ODD CMP AL, 2 ; 2, 4: JE EVEN CMP AL, 4 JE EVEN JMP END_CASE ODD: MOV DL, o JMP DISPLAY EVEN: MOV DL, e DISPLAY: MOV AH, 2 INT 21H END_CASE: 58

59 Loop Next Dec Cx If CX<>0 JMP Next Loopz/loope Next Loop Instructions Dec Cx If (CX<>0) AND (ZF=1) JMP Next Loopnz/loopne Next Dec Cx If (CX<>0) AND (ZF=0) JMP Next 59

60 FOR LOOP Example: For 80 times DO Display * END_IF Next: MOV CX, 80 MOV AH, 2 MOV DL, * INT 21H Loop Next 60

Intel 8086 MICROPROCESSOR. By Y V S Murthy

Intel 8086 MICROPROCESSOR. By Y V S Murthy Intel 8086 MICROPROCESSOR By Y V S Murthy 1 Features It is a 16-bit μp. 8086 has a 20 bit address bus can access up to 2 20 memory locations (1 MB). It can support up to 64K I/O ports. It provides 14,