Binghamton University. CS-120 Summer LC3 Memory. Text: Introduction to Computer Systems : Sections 5.1.1, 5.3

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1 LC3 Memory Text: Introduction to Computer Systems : Sections 5.1.1, 5.3

John Von Neumann (1903-1957) Princeton /

2 John Von Neumann ( ) Princeton / Institute for Advanced Studies Need to compute particle interactions during a nuclear reaction (Manhattan Project) EDVAC (First US Digital Computer)

3 Von Neumann Architecture Memory MAR MDR Input Processing Unit ALU R1 R2 R3 R4 R5 R6 R7 Output Control Unit PC CC IR

4 LC3 Memory RAM Hardware Data width = 16 bits (1 word) Address with = 16 bit (1 word) 2 16 = 65,536 rows with addresses 0x0000 0xFFFF Each word may contain either data or instruction VonNeumann instructions and data use same memory 0xffff 0x01c7 0xfffe 0xdaf3 0xfffd 0xed00 0xffffc 0xbe1c 0xfffb 0xef16 0x0c09 0x0000 0x0c08 0x0000 0x0c07 0x013f 0x0c06 0x184a 0x0c05 0x x0003 0x0000 0x0002 0x0000 0x0001 0x0000 0x0000 0x03ff

5 LC3 Memory Read MAR Memory Address Register Contains address of memory to read from MDR Memory Data Register Read copies value in memory at MAR address into MDR MAR 0x0c07 MDR 0x013F 0xffff 0xfffe 0xfffd 0xffffc 0xfffb 0x0c09 0x0c08 0x0c07 0x0c06 0x0c05. 0x0003 0x0002 0x0001 0x0000 0xdaf3 0xed00 0xbe1c 0xef16 0x0000 0x0000 0x013f 0x184a 0x0001 0x0000 0x0000 0x0000 0x03ff

6 LC3 Memory Write MAR Memory Address Register Contains address of memory to write to MDR Memory Data Register Write copies value in MDR to memory at MAR address MAR 0x0c07 MDR 0x3333 0xffff 0xfffe 0xfffd 0xffffc 0xfffb 0x0c09 0x0c08 0x0c07 0x0c06 0x0c05. 0x0003 0x0002 0x0001 0x0000 0xdaf3 0xed00 0xbe1c 0xef16 0x0000 0x0000 0x3333 0x184a 0x0001 0x0000 0x0000 0x0000 0x03ff

7 Instruction Register 16 bit register in the Control Unit Contains the instruction currently being executed IR 0x1283 0x1283 = or ADD r1,r2,r3

8 Program Counter (PC) 16 bit register in Control Unit Contains Address of the next instruction to be executed Initialized to address of first instruction when program is loaded Incremented (+1) when instruction is read Some instructions read or write to the PC register (more to come) PC 0x301C

9 LC3 Instruction Cycle (1 st Draft) Start at x3000 Read Instruction Move to Next Instruction Process Instruction HALT

10 LC3 Instruction Cycle Fetch Instruction Store Results Decode Execute Evaluate Address Fetch Operands

11 Fetch Instruction Internal Details Fetch Instruction Copy PC to MAR Read Memory at MAR into MDR (Read PC) Copy MDR to IR Make PC ALU Operand A Make 1 ALU Operand B Tell ALU to ADD Store Result in PC (PC PC+1) Note: After Fetch Instruction, PC points at NEXT instruction! Store Results Execute Fetch Operands Decode Evaluate Address

12 Decode Internal Details Fetch Instruction Use OPCODE in IR (first 4 bits) to determine How the rest of the instruction register should be read Which phases of instruction cycle are needed * What control signals are sent to memory, processing unit, I/O in each relevant phase Use remaining (last 12) bits to determine Source Register(s) Destination Register Immediate Values (padded to 16 bits) Store Results Execute Fetch Operands Decode Evaluate Address * Different instructions use different subsets of the last 4 phases

13 Load Instruction Assembly Mnemonic: LD Destination Register (Rz) Offset e.g. ld R1,#12 Object Opcode: 0010 (0x2) DR (3 bit subfield) PCoffset9 (9 bit subfield) e.g. 0b =0x220C Adds value in PC to offset, writes to MAR, reads memory, copies MDR to Destination Register (Rz)

14 PC/Offset Address Mode 16 bit instruction too small for both op-code and 16 bit address Most data is close to current instruction in memory Calculate effective address by adding PC offset to PC PC offset may be positive or negative Effective address may be above or below current instruction In Assembly, label reference is the same as a PC offset! Label reference is converted to a PC offset by Assembler One instruction must refer to a single memory location REMEMBER: PC points to instruction AFTER current instruction!

15 Load Register Instruction Assembly Mnemonic: LDR Destination Register (Rz) Base Register (Rb) Offset e.g. ldr R1,R3,#3 Object Opcode: 0110 (0x6) DR (3 bit subfield) BaseR (3 bit subfield) Offset6 (6 bit subfield) e.g. 0b =0x62C3 Adds value in Base Register (Rb) to offset, writes to MAR, reads memory, copies MDR to Destination Register (Rz)

16 Base/Offset Address Mode 16 bit instruction too small for both op-code and 16 bit address Calculate effective address by adding offset to base register Offset may be positive or negative or zero Effective address may be above or below or at where base register points One instruction may point to different memory locations! Execute the same instruction with different base register values Q: How do you get an address in a register?

17 Load Effective Address Assembly Mnemonic: LEA Destination Register (Rz) Offset e.g. lea R1,#12 Object Opcode: 1110 (0xE) DR (3 bit subfield) PCoffset9 (9 bit subfield) e.g. 0b =0xE20C Adds value in PC to offset, writes to Destination Register (Rz)

18 Evaluate Address Internal Details Fetch Instruction No action for ADD, AND, NOT Store Results Decode For PC/Offset instructions (LD, LEA, etc.) Copy PC to ALU operand A Copy Pcoffset9, sign extended, to ALU operand B For Base/Offset instructions (LDR, etc.) Copy Rb to ALU operand A Copy Offset6, sign extended, to ALU operand B Tell ALU to Add Copy result to MAR Execute Fetch Operands Evaluate Address

19 Fetch Operands Internal Details Fetch Instruction For ADD, AND, NOT, copy SR1 to ALU operand A For ADD, AND, copy either SR2 or IMM5 to ALU operand B For LD and LDR, read memory at MAR Store Results Execute Fetch Operands Decode Evaluate Address

20 Execute Internal Details Fetch Instruction No action for LD, LDR, LEA For ADD, Tell ALU to Add For AND, Tell ALU to And For NOT, Tell ALU to invert Store Results Execute Fetch Operands Decode Evaluate Address

21 Store Results Internal Details Fetch Instruction For ADD, AND, NOT, store ALU result to DR For LD, LDR, copy MDR to DR For LEA, copy MAR to DR Store Results Execute Fetch Operands Decode Evaluate Address

22 Store Instruction Assembly Mnemonic: ST Source Register (Rs) Offset e.g. st R1,#12 Object Opcode: 0011 (0x3) SR (3 bit subfield) PCoffset9 (9 bit subfield) e.g. 0b =0x320C Adds value in PC to offset, writes to MAR, copies Source Register (Rs) value to MDR, writes memory NOTE: BACKWARDS INSTRUCTION (Rs Memory)

23 Store Register Instruction Assembly Mnemonic: STR Source Register (Rs) Base Register (Rb) Offset e.g. str R1,R3,#6 Object Opcode: 0111 (0x7) SR (3 bit subfield) BaseR (3 bit subfield) Offset6 (6 bit subfield) e.g. 0b =0x72C6 Adds value in Base Register (Rb) to offset, writes to MAR, copies Source Register (Rs) value to MDR, writes memory NOTE: BACKWARDS INSTRUCTION (Rs Memory)

24 LD/ST vs LDR/STR LD R3,COUNT ST R6,ANSWER Cannot read or write unlabeled addresses e.g. LD R4,DATA+3 Every time this instruction is executed, it references the SAME memory Cannot read or write vectors or arrays LD/ST Used for single fixed variables LDR/STR Used for arrays/vectors/offsets Almost always preceded by LEA Especially useful in looping code 3 rd argument is fixed (usually #0) LD R1,OFFSET LEA R2,DATA ADD R1,R1,R2 LDR R3,R1,#0 ADD R3,R3,#10 STR R3,R1,#0

25 LC3 Program Layout (No Branches).orig always first Next is your code End with HALT Followed by data.end always last

26 LC3 Example Program: Specifications Read the first memory location after the program. Write that value+1 in the second memory location after the program, and that value+2 in the third memory location after the program.

27 Example LC3 Program.orig x3000 LD R1,#??? ADD R1,R1,#1 ST R1,#??? ADD R1,R1,#1 ST R1,#??? HALT.fill #15.fill #0.fill #0.end

28 Example LC3 Program.orig x3000 x3000 LD R1,#??? Current Instruction x3001 ADD R1,R1,#1 PC = x3001 x3002 ST R1,#??? PC+1 x3003 ADD R1,R1,#1 PC+2 x3004 ST R1,#??? PC+3 x3005 HALT PC+4 x3006.fill #15 PC+5 x3007.fill #0 x3008.fill #0.end

29 Example LC3 Program.orig x3000 x3000 LD R1,#5 x3001 ADD R1,R1,#1 x3002 ST R1,#??? Current Instruction x3003 ADD R1,R1,#1 PC x3004 ST R1,#??? PC+1 x3005 HALT PC+2 x3006.fill #15 PC+3 x3007.fill #0 PC+4 x3008.fill #0.end

30 Example LC3 Program.orig x3000 x3000 LD R1,#5 x3001 ADD R1,R1,#1 x3002 ST R1,#4 x3003 ADD R1,R1,#1 x3004 x3005 ST R1,#??? HALT Current Instruction PC x3006.fill #15 PC+1 x3007.fill #0 PC+2 x3008.fill #0 PC+3.end

31 Example LC3 Program.orig x3000 LD R1,#5 ADD R1,R1,#1 ST R1,#4 ADD R1,R1,#1 ST R1,#3 HALT.fill #15.fill #0.fill #0.end

Instruction Set Architecture

Chapter 5 The LC-3 Instruction Set Architecture ISA = All of the programmer-visible components and operations of the computer memory organization address space -- how may locations can be addressed? addressibility