SystemVerilog Assertions for Clock-Domain-Crossing Data Paths. Don Mills Microchip Technology Inc.
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1 SystemVerilog Assertions for Clock-Domain-Crossing Data Paths Don Mills Microchip Technology Inc.
2 Outline Brief Review of CDC Concepts and Issues Basics of SystemVerilog Assertions Modeling Techniques and Issues using SVA for CDC SVA Model for both RTL and GLS 2
3 What is Clock Domain Crossing? Clk_A B_in What is a Clock Domain? flip-flops with same clock (clock tree) Clock Domain Crossing Data from one clock domain is captured (sampled) in another clock domain 3
4 Clock Domain Crossing Issue - Metastability Clk_A B_in B_in Setup time window B_in Hold time window Violating setup or hold time of flipflop can cause metastability A signal settling from metastability settles to the old state or the new state Screen shot from Philip Freidin 4
5 Asynchronous Clocks & Metastability Scenario 1?? "1" Clk_A B_in???? "0" sampled by A_clk???? A_clk B_in sampled by B_clk B_in B_clk Original Slide from Cliff Cummings Boston SNUG 2008 (Used by permission) Modifications made to match this presentation. All outputs are known in this cycle Clocked B_in signal is initially metastable settles to either 0 or 1 5
6 Asynchronous Clocks & Metastability Scenario 2 "1" "0" sampled by A_clk Clk_ A A_clk _in B2_in B2 B2 filters the metastable state of from propagating assumes settles within one clock cycle "1" "1" "1" "0" "0" _in sampled by B_clk B_in B_clk B2_in Original Slide from Cliff Cummings Boston SNUG 2008 (Used by permission) Modifications made to match this presentation. 6
7 An Assertion Property for CDC Clk_A _in B2_in B2 property CDC_prop1; logic Clk_A) ($changed(), v_temp = ) => ($changed(_in) && (_in === v_temp)) ##1 Transition ) ($changed(_in) && (_in === v_temp)) ##[2:3] ($changed() && ( === v_temp)); endproperty:cdc_prop1 7
8 Map Assertion to Wave view 1 Clk_A) ($changed(), v_temp = ) => (($changed(_in) && (_in === v_temp)) ##1 //switch clk ) ($changed(_in) && (_in === v_temp)) ##[2:3] ($changed(_out) && (_out === v_temp)); Test _in at output of in A_clk domain 8
9 Map Assertion to Wave view 2 Clk_A) ($changed(), v_temp = ) => (($changed(_in) && (_in === v_temp)) ##1 //switch clk ) ($changed(_in) && (_in === v_temp)) ##[2:3] ($changed(_out) && (_out === v_temp)); Test _in at output of in A_clk domain Testing $changed of input to in B_clk domain is a cycle late 9
10 Why does this Property fail for CDC? Clk_A _in B2_in B2 Cannot remain testing in Clk_A domain while actual data has moved onto the next clock domain property CDC_prop1; logic Clk_A) ($changed(), v_temp = ) => ($changed(_in) && (_in === v_temp)) ) ($changed(_in) && (_in === v_temp)) ##[2:3] ($changed() && ( === v_temp)); endproperty:cdc_prop1 10
11 A correct (RTL) Assertion Property for CDC Clk_A _in B2_in B2 Changes to Property 1. overlapping implication operator 2. no test after implication operator 3. use -> for clock transition property CDC_prop1; logic Clk_A) ($changed(), v_temp = ) ) ($changed(_in) && (_in === v_temp)) ##[2:3] ($changed() && ( === v_temp)); endproperty:cdc_prop1 11
12 Correctly working CDC Clk_A) ($changed(), v_temp = ) ) ($changed(_in) && (_in === v_temp)) ##[2:3] ($changed(_out) && (_out === v_temp)); 12
13 Full RTL test results rising and falling, 2 and 3 clk delay NOTE: Final $changed is tested one cycle after last transition All conditions passed 13
14 Gate Level Sim (GLS) can fail with RTL assertion Assertion sampling does not account for GLS propagation Clk_A _in B2_in B2 This passes in RTL because _in changes immediately on Clk_A Exaggerated Clk to Q GLS ) ($changed(_in) && (_in === v_temp)) 14
15 A Property that works for both RTL and GLS Clk_A _in B2_in B2 property CDC_prop1; logic Clk_A) ($changed(), v_temp = ) ) ##[0:1] ($changed(_in) && (_in === v_temp)) ##[2:3] ($changed() && ( === v_temp)); endproperty:cdc_prop1 The ##[0:1] allows for immediate testing in domain for RTL or for a to occur during GLS propagation of flip-flop 15
16 Passing GLS Clk_A) ($changed(), v_temp = ) ) ##[0:1] ($changed(_in) && (_in === v_temp)) ##[2:3] ($changed(_out) && (_out === v_temp)); 16
17 Conclusions Lots of papers on CDC in Google land Not so many papers on SV Assertions This paper presents an SV Assertion that works for both RTL and GLS This SV Assertion can be extended to support loop back to original clock domain 17
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