L11: Major/Minor FSMs

Transcription

1 L11: Major/Minor FSMs Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Rex Min 1

2 Quiz Quiz will be Closed Book Tuesday, March 21, 2006, 7:30pm-9:30pm in Covers Problem Sets 1-3, Lectures 1-10 (through Analog), Labs 1-3 Some of the topics to be covered include Combinational Logic: Boolean Algebra, Karnaugh Maps, MSP, MPS, dealing with don t cares Latches and Edge Triggered Registers/Flip-flops Understand the difference between latches, registers and unclocked memory elements (e.g., SR-Flip Flop) Different memory types: SR, D, JK, T Understand setup/hold/propagation delay and how they are computed System Timing (minimum clock period and hold time constraint) Impact of Clock skew on timing Counters and simple FSMs (understand how the 163 and 393 work) FSM design (Mealy/Moore, dealing with glitches) Combinational and sequential Verilog coding Continuous assignments, blocking vs. non-blocking, etc. 2

3 Quiz (cont.) Tri-states basics Dealing with glitches When are glitches OK? How do you deal with glitches in digital system design? (registered outputs, appropriate techniques to gate a clock, etc.) Memory Basics Understand differences between DRAM vs. SRAM vs. EEPROM Understand timing and interfacing to the 6264 Arithmetic Number representation: sign magnitude, Ones complement, Twos complement Adder Structures: Ripple carry, Carry Bypass Adder, Carry Lookahead Adder False Paths and Delay Estimation Shift/add multiplier, Baugh-Wooley Multiplier (Twos complement multiplication) Analog Design Basics of ADC and DAC, interfaces 3

4 Toward FSM Modularity Consider the following abstract FSM: S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 a 1 d 1 a 2 d 2 a 3 d 3 b 1 c 1 b 2 c 2 b 3 c 3 Suppose that each set of states a x...d x is a sub-fsm that produces exactly the same outputs. Can we simplify the FSM by removing equivalent states? No! The outputs may be the same, but the next-state transitions are not. This situation closely resembles a procedure call or function call in software...how can we apply this concept to FSMs? 4

5 The Major/Minor FSM Abstraction A A Minor FSM A RESET CLK Major FSM B B Minor FSM B RESET CLK Subtasks are encapsulated in minor FSMs with common reset and clock Simple communication abstraction: : tells the minor FSM to begin operation (the call) : tells the major FSM whether the minor is done (the return) The major/minor abstraction is great for... Modular designs (always a good thing) Tasks that occur often but in different contexts Tasks that require a variable/unknown period of time Event-driven systems 5

6 Inside the Major FSM... S 1 S 2 S 3 S 4 1. Wait until the minor FSM is ready 2. Trigger the minor FSM (and make sure it s started) 3. Wait until the minor FSM is done Major FSM State S 1 S 2 S 2 S 3 S 3 S 3 S 4 CLK 6

7 Inside the Minor FSM 1. Wait for a trigger from the major FSM T 1 T 2 T 3 T 4 3. Signal to the major FSM that work is done 2. Do some useful work Major FSM State CLK Minor FSM State S 1 S 2 S 2 S 3 S 3 S 3 S 4 T 1 T 1 T 2 T 3 T 4 T 1 T 1 can we speed this up? 7

8 Optimizing the Minor FSM Good idea: de-assert one cycle early T 1 T 2 T 3 T 4 Bad idea #1: T 4 may not immediately return to T 1 Bad idea #2: never asserts! T 1 T 2 T 3 T 4 T 1 T 2 8

9 A Four-FSM FSM Example TICK Major FSM A A B B C C Minor FSM A Minor FSM B Minor FSM C Operating Scenario: Major FSM is triggered by TICK Minors A and B are started simultaneously Minor C is started once both A and B complete TICKs arriving before the completion of C are ignored TICK IDLE Assume that A and B both rise before either minor FSM completes. Otherwise, we loop forever! TICK A + B ST AB A B A B A + B WT AB A B C WT C C ST C C C C 9

10 Four-FSM FSM Sample Waveform TICK A A Minor FSM A Major FSM B B Minor FSM B C C Minor FSM C state tick IDLE IDLE ST AB ST AB WT AB WT AB WT AB ST C ST C WT C WT C WT C IDLE IDLE ST AB A A B B C C 10