Online Unsupervised Spike Sorting Accelerator
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1 Online Unsupervised Spike Sorting Accelerator Zhewei Jiang, Jamis Johnson CSEE4840 Embedded System esign
2 Motivation for Hardware Spike Sorting Motivated by Transmission Cost High energy consumption Throughput limitation Spike Sorting 32~64 * 8 bits/spike 3~4 bits/spike ozens/hundreds of Channels Challenges Computation complexity Feature extraction Clustering Memory Requirement Feature istribution Cluster Centroid Prosthesis
3 Algorithm Stage Algorithm Main Module(s) istribution 1 Kernel ensity Estimation ISTR (main FSM) Sample Criterion Laplacian ISTR (Laplace FSM) Training Sorting Bimodal prediction & replacement policy Closest Grid (grid granularity) CAM_CLUSTER GRIFIN CAM_CLUSTER GRIFIN WTA
4 Algorithm - Kernel ensity Estimation Approximate Bayesian Optimal Kernel ensity Estimation Marr wavelet as kernel Hardware cost assuming 8 bit resolution memory entry Updates per spike kernel smoothing parameter
5 Algorithm - Kernel ensity Estimation Histogram Trivial kernel Hardware cost memory entry One update per spike
6 Algorithm - Kernel ensity Estimation 64 2 memory entry One update per spike Histogram Trivial kernel Hardware cost memory entry One update per spike
7 Kernel ensity Estimation Trivial Case 2 Kernel ensity Estimation Laplacian of Gaussian (Marr Wavelet) 1 Kernel ensity Estimation Gaussian (or LoG, similar hardware cost if precomputed) Histogram Smoothing with bin width
![Laplacian Convolution of histogram of negative Laplace operator [-1, 2, -1] ownward trend of 2 nd derivative is used to](/docs-images/73/68803479/images/8-3.jpg "segment distribution space into informative and uninformative regions Only data in the shaded area are used for")
8 Laplacian Convolution of histogram of negative Laplace operator [-1, 2, -1] ownward trend of 2 nd derivative is used to segment distribution space into informative and uninformative regions Only data in the shaded area are used for training
9 Informative Sample Vector Mask Informative sample vector mask reduces outliners sensitivity during training phase Certain features can share distribution space if no overlap can occur (e.g. peak & hyperpolarization)
10 Bayesian Classification At this point, classification can be done through istance metric (e.g. Probabilistic Neural Network, MCK, ) Boundary metric (Bayesian Boundary) Yaroslav Bulatov
11 Top-Level Hardware Architecture MEM2: INFO SAMPLE boundary[41:0] MEM3: GRI Spk_f[11:0] Informative[63:0] Valid_grid[6:0] Comb: GRIFIN infm Grid_idx[5:0] ker clear laplace MEM1: ISTRIBUTION MEM4: Grid_index/ Comb: grid match V[7:0][1:0]x8 Comb: WTA(min distance) Valid fin IX[2] IX[1] IX[0]
12 S/H Interface Clk, reset, read, write Spk_f[11:0] Writedata AVALON BUS ker clear laplace Update HARWARE Address Leak Valid fin IX[2] IX[1] IX[0] Clk, reset, read, write, readdata, writedata SOFTEWARE Scheduling, commands Readdata
13 Modules [istribution] Boundary_thr convolve wke Laplacian Boundary FEATURE is_f CAR Ctrl +1 w
14 Modules [istribution] Boundary_thr KE[i] <<1 SUB SUB Comparator A Register 1 informative 4 Comparator ENB Register A Register 1 A 1 4 Boundary 4 convolve ENB ENB
15 Modules [Training & Sorting] FEATURES FIS (Informative Features) SEGS (Grid Boundary Peak) GRIFIN CAM_CLUSTER (Content Associative Memory Grid indexes as cluster identifier) SEGS (Grid Boundary Hyperpolarization) GRIFIN ATTR WTA Output
16 Modules [GRIFIN] Fp Fh Idx_p Boundary Boundary_fp Idx_h Register Register Register Regis ter Boundary_fh A 1 A 1 A 1 A 1 Load_b H ENB 8 H ENB 8 H ENB 8 H ENB 8 Load_bh Load_bp SE T SE T SE T SE T C LR C LR C LR C LR Feature Comparator Comparator Comparator Comparator Index
17 Modules [CAM_CLUSTER] Idx_p Idx_h Register Register Load_C 3b A 1 4 SUB 3b A 1 4 SUB Strong Cluster F_h F_p ENB ENB istance Weak Cluster Outlier A Match Free Update & (miss leak) Each cluster is associated with a bimodal updater, every matching spike strengthens the usefulness of the cluster, and periodic leakage is applied to weaken the cluster. False cluster caused by outliers is cleared this way.
18 Modules [WTA] IST0 IST1 Candidate [0] Candidate [2] W W IST2 IST3 Candidate [2] W Cluster_idx[1] Cluster_idx[0] Candidate [3] IST4 IST5 Candidate [4] W Candidate [5] IST6 W VALI IST7 Candidate [6] Candidate [7] W W A B > sel vb v va
19 esign Timing Sequential Components: FSM (for histogram generation in ISTR) FSM (for Laplacian in ISTR) Usefulness Updater (Bimodal SM for outliner handling in CAM_CLUSTER) Negedge triggers nstate Transition: nstate <= f(state) Posedge triggers State Transition: State <= nstate & FSM Outputs (registered output) based on nstate Combinational circuit (in FSM) propagation for half cycle, guarantee no set-up/hold violation from clock jitter or skew
20 esign Timing (Legacy) Level sensitive Latch (non-clk enable) Negedge triggered FF WRITE CLK Retention Latch is used in a power-gating version of the SET SET design, with no retention flip-flop available. A non-retention FF trails L CLR CLR a Latch to allow the design of a Comb(bimodal) FSM that does not require extra cycle to read back state from L after power gating
21 esign Timing (Legacy) Level sensitive Latch (non-clk enable) Negedge triggered FF WRITE CLK WRITE SET SET CLK SET L CLR CLR CLR Comb(bimodal) Comb(bimodal)
22 esign Timing of Module ISTR Internal FSM timing as previous slides Ack (signal Fin) based interface, communication locked until software read out Fin. Command Ker: [read Max & incr][write][read Min & incr][write][fin] special case when memory overflow: [read & >> 1][write] (64 entries) Command Laplace: [read][read][read] (64 entries) [Fin] Secondary FSM find informative sample regions based on (entry[i]<<1) > (entry[i-1]+entry[i+1])
23 esign Timing of Module GC FEATURES FIS (Informative Features) SEGS CAM_CLUSTER S S ET R C LR GRIFIN ATTR S R S ET C LR WTA Output
24 RTL Sim (esign Compiler)
25 Issues & Lessons Learned Testability Individual Modules Overall Functionality ebugging
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