Digital Integrated Circuits

Transcription

1 Digital Integrated Circuits Lecture 5 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University

2 MULTIPLE initial/always In C (single-threaded), a single statement is being executed at a given time initial begin... always begin... always begin... always begin... Each initial/always block is executed concurrently. Multiple statements are being executed at a given time. (Similar to multi-threading and more roughly, multi-tasking) Why does it need? Hardware runs concurrently Each gate operates indepently Chung EPC6055 2

3 HOW MANY always BLOCKS? For sequential gates, we need at least one always block More precisely, we need one to model the output of flip-flops or latches comb. logic always or assign Seq. logic clock) Chung EPC6055 3

4 HOW MANY always BLOCKS? For a combinational network, we use many always blocks (But if possible, use as small as possible) comb. logic always or assign comb. logic always or assign Seq. logic always@(posedge clock) Chung EPC6055 4

5 HOW MANY always BLOCKS? Another good option Chung EPC6055 5

6 HOW MANY always BLOCKS? Note that we don t do below Chung EPC6055 6

7 The mix of structural and behavioral D Q D Q D D Q Q Instance 1 D D Q Q D Q Instance 2 D Q Chung EPC6055 7

8 BCD TO EXCESS-3 CODE CONVERTER //State Encoding `define S0 3'b000 `define S1 3'b100 `define S2 3'b101 `define S3 3'b111 `define S4 3'b110 `define S5 3'b011 `define S6 3'b010 module bcd_to_excess3(rst, clk, x, z); input rst, clk; input x; output z; reg z; reg [3:0] next_state; // State register reg [3:0] state; // Combinational logic or x) begin case(state) `S0: if(x) begin z = 0; next_state = `S2; else begin z = 1; next_state = `S1; Chung EPC6055 8

9 BCD TO EXCESS-3 CODE CONVERTER `S1: if(x) begin z = 0; next_state = `S4; else begin z = 1; next_state = `S3; `S2: begin if(x) z = 1; else z = 0; next_state = `S4; // Complete yourself! default: ; case // Sequential logic always@(posedge clk or negedge rst) begin if(~rst) state <= `S0; else state <= next_state; module Chung EPC6055 9

10 OPERATORS Operator Type Operator Meaning Example + add assign ADD=A + B - subtract assign SUB=A - B Arithmetic Operator * multiply assign MUL=A * B / divide assign DIV=A / B % modulo assign REM=A % B == equal return value = 0, 1, x === equal including x/z return value = 0, 1!= not equal return value = 0, 1, x Relational Operator!== Not equal including x/z return value = 0, 1 < Less than return value = 0, 1, x <= Less than or equal return value = 0, 1, x > Great than return value = 0, 1, x >= Greater than or equal return value = 0, 1, x Chung EPC

11 OPERATORS Operator Type Operator Meaning Example && Logical AND if (A && B) Logical Operator Logical OR if (A B)! Logical NOT if (!A) ~ Bitwise NOT ~(1011) = (0100) & Bitwise AND (1011) & (0011)=(0011) Bitwise Operator Bitwise OR (1011) (0011)=(1011) ^ Bitwise XOR (1011) ^ (0011)=(1000) ^~, ~^ Bitwise XNOR (1011) ~^ (0011)=(0111) & Reduction AND &(0101) = 0 Reduction OR (0101) = 1 Reduction Operator ~& Reduction NAND ~&(0101) = 1 ~ Reduction NOR ~ (0101) = 0 ^ Reduction XOR ^(0101) = 0 ~^, ^~ Reduction XNOR ~^(0101) = 1 Chung EPC

12 OPERATORS Operator Type Operator Meaning Example >> Right Shift 0101_1001=1011_0011>>1 Shift Operator << Left Shift 0110_0110=1011_0011<<1 { } concatenation {0011,{{01},{10}}=0011_0110 Others {{ }} replication A=1 b1; Y={4{A}} = 4 b1111? : Conditional Y=(A==B)? A:B (A==B, Y=A else Y=B) Chung EPC

13 DEBOUNCING AND SYNCHRONIZING Synchronizing External Signal Need to Synchronize External Signal with Internal Clock Avoid Setup Time Violation and Metastability Debouncing Mechanical Switch Contact May Bounce Several Milliseconds Before Settling in Final Value Must Wait for Bounce to Settle Before Reading Chung EPC

14 DEBOUNCING AND SYNCHRONIZING CIRCUIT Chung EPC

15 SINGLE PULSER Human Pressing Button Signal Would Be High for Many Cycles Single Pulser Circuit Convert Human Action to Single Clock Cycle Pulse Chung EPC

16 QUESTION Chung EPC

17 TRAFFIC LIGHT CONTROLLER Street A (Main Street) Has Green Until Car Arrives on Street B Sensors for Streets A and B When Car on B, A changes to Yellow and Red After 50 sec, If Car on A or No Car on B, then B changes to Yellow and then Red When A Turns Green, It Stays Green for at Least 60 sec Chung EPC

18 STATE GRAPH Clock Period = 10sec Chung EPC

19 VERILOG CODE // State Encoding `define S0 4'd0 `define S1 4'd1 `define S2 4'd2 `define S3 4'd3 `define S4 4'd4 `define S5 4'd5 `define S6 4'd6 `define S7 4'd7 `define S8 4'd8 `define S9 4'd9 `define S10 4'd10 `define S11 4'd11 `define S12 4'd12 module traffic(sa,sb,ga,ya,ra,gb,yb,rb,clk,rst); input sa,sb; input clk,rst; output Ga,Ya,Ra,Gb,Yb,Rb; reg Ga,Ya,Ra,Gb,Yb,Rb; reg [3:0] next_state; // State Register reg [3:0] state; // Output Logic (Combinational) begin Ra=0; Ya=0; Ga=0; Rb=0; Yb=0; Gb=0; case (state) `S0,`S1,`S2,`S3,`S4,`S5:begin Ga=1; Rb=1; `S6:begin Ya=1; Rb=1; `S7,`S8,`S9,`S10,`S11:begin Ra=1; Gb=1; `S12:begin Ra=1; Yb=1; default: ;// Do nothing case // Transition Logic (Combinational) or sb or state) begin case (state) `S0: next_state = `S1; `S1: next_state = `S2; `S2: next_state = `S3; Chung EPC

20 VERILOG CODE `S4: next_state = `S5; `S5: if(~sb) next_state = `S5; else next_state = `S6; `S6: next_state = `S7; `S7: next_state = `S8; `S8: next_state = `S9; `S9: next_state = `S10; `S10: next_state = `S11; `S11: if(sa ~sb) next_state = `S12; else next_state = `S11; `S12: next_state = `S0; default: ; // Do nothing case // Sequential Logic always@(posedge clk or negedge rst) begin if(~rst) state <= `S0; else state <= next_state; module Chung EPC

21 SHIFT-AND-ADD MULTIPLIER Need 4-Bit Adder, 4-Bit Multiplicand, 4-Bit Multiplier, and 8-Bit Product Register Chung EPC

22 SHIFT-AND-ADD MULTIPLIER Chung EPC

23 SHIFT-AND-ADD MULTIPLIER Chung EPC

24 SHIFT-AND-ADD MULTIPLIER Chung EPC

25 SHIFT-AND-ADD MULTIPLIER module multiple4 (a,b, clk, z, done ); input clk; input [3:0] a,b; output [8:0] z; output done; reg [8:0] acc; reg [3:0] state; reg done; assign z = acc; (posedge clk) begin if(state==0) begin acc[8:4] <= 5'b0; acc[3:0] <= b[3:0]; done <= 0; state <= state+1; else if(state == 1 state== 3 state==5 state== 7) begin if (acc[0]==1) begin acc[8:4] <= acc[7:4] + a[3:0]; state <= state+1; else begin acc <= {1'b0,acc[8:1]}; state <= state+2; else if(state==2 state==4 state==6 state== 8) begin acc <= {1'b0,acc[8:1]}; state <= state+1; else if(state==9) begin state <= 0; done <= 1; else state <= 0; module Not Good Example Chung EPC

26 SHIFT-AND-ADD MULTIPLIER module multiple4_2 (a,b, clk, rst,st, z, done ); input clk, rst, st; input [3:0] a,b; output [8:0] z; output done; reg [8:0] acc; reg [3:0] state; reg [3:0] next_state; reg sh, ad, load, done; wire m; ////// Datapath assign z = acc; assign m = acc[0]; // To contoller always@(posedge clk) begin if(sh) // From contoller acc <= {1'b0,acc[8:1]}; else if(ad) // From contoller acc[8:4] <= acc[7:4] + a[3:0]; else if(load) begin // From contoller acc[8:4] <= 5'b0; acc[3:0] <= b[3:0]; /////// Controller // Combinational Logic of the Controller (Transition and Output Logic) (state or m or st) begin load = 0; done = 0; ad = 0; sh = 0; next_state = 0; if(state==0) begin if(st) begin load = 1; next_state = state+1; else next_state = 0; else if(state == 1 state== 3 state==5 state== 7) begin if (m==1) begin ad = 1; next_state = state+1; else begin sh = 1; next_state = state+2; else if(state==2 state==4 state==6 state== 8) begin sh = 1; next_state = state+1; else if(state==9) begin next_state = 0; done = 1; Chung EPC

27 SHIFT-AND-ADD MULTIPLIER clk or negedge rst) begin if(!rst) state <= 0; else state <= next_state; module Chung EPC

28 SHIFT-AND-ADD MULTIPLIER Chung EPC

29 (RT-Level) Timing Module A and B communicates Module A ss a request to Module B Module B processes the request and s a response back request A response B It takes P ns to process the request including the communication time Chung EPC

30 (RT-Level) Timing If P is very small (P << T), where T is the clock period, A B reg reg request response Comb. logic CLK Req Res REQ OK CLK Req Res Chung EPC

31 (RT-Level) Timing If P > T, A B reg request response Comb. logic reg reg CLK Req Res REQ CLK Req Res Chung EPC

32 (RT-Level) Timing If P > 2T, A B request reg response reg Comb. logic reg reg CLK Req REQ Res Chung EPC

33 ARRAYS Arrays Variables of the reg, integer, time, and vector register data types can be represented as an array. <Data-Type> [Vector Range] <Variable Name> [Array Range] Multi-dimensional arrays are not supported. A vector is a single object with n-bit range whereas an array consists of m objects with n-bit range. reg xxx [15:0]; reg [3:0] mux [0:7]; // an array of 16 registers // an array of 8 4-bit registers Chung EPC

34 MODELING ROM Style 1 (Using Case) module rom_case(z, a); output [3:0] z; // 4 wide input [2:0] a; // address- 8 deep memory reg [3:0] z; begin case (a) 3'b000: z = 4'b1011; 3'b001: z = 4'b0001; 3'b100: z = 4'b0011; 3'b110: z = 4'b0010; 3'b111: z = 4'b1110; default: z = 4'b0000; case module // rom_case Chung EPC

35 MODELING ROM Style 2 (Using Array, Initialized with initial block) module rom_2dimarray_inital (z, a); output [3:0] z; input [2:0] a; // address- 8 deep memory // declare a memory rom of 8 4-bit registers. The indices are 0 to 7 reg [3:0] rom[0:7]; initial begin rom[0] = 4'b1011; rom[1] = 4'b0001; rom[2] = 4'b0011; rom[3] = 4'b0010; rom[4] = 4'b1110; rom[5] = 4'b0111; rom[6] = 4'b0101; rom[7] = 4'b0100; assign z = rom[a]; module Chung EPC

36 MODELING ROM Style 3 (Using Array, Initialized with $readmemb) module rom_2dimarray_initial_readmem (z, a); output [3:0] z; input [2:0] a; // declares a memory rom of 8 4-bit registers. //The indices are 0 to 7 reg [3:0] rom[0:7]; // NOTE: To infer combinational logic instead of a ROM, use // (* synthesis, logic_block *) initial $readmemb("rom.data", rom); assign z = rom[a]; module Chung EPC

37 MODELING RAM Asynchronous Read, Synchronous Write 0 cycle to read 1 cycle to write Chung EPC

38 MODELING RAM Synchronous Read/Write 1 cycle to read/write module or1200_spram_128x32( // Generic synchronous single-port RAM interface clk, rst, ce, we, oe, addr, di, doq ); // // Default address and data buses width // parameter aw = 7; parameter dw = 32; // // Generic synchronous single-port RAM interface // input clk, rst; input ce; // Chip enable input input we; // Write enable input oe; // Output enable input [aw-1:0] addr; // address bus input [dw-1:0] di; // input data bus output [dw-1:0] doq; // output data bus // // Generic single-port synchronous RAM model // // // Generic RAM's registers and wires // reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content reg [aw-1:0] addr_reg; // RAM address register // // Data output drivers // assign doq = (oe)? mem[addr_reg] : {dw{1'b0}}; // // RAM address register // clk or posedge rst) if (rst) addr_reg <= #1 {aw{1'b0}}; else if (ce) addr_reg <= #1 addr; // // RAM write // clk) if (ce && we) mem[addr] <= #1 di; module Chung EPC

39 MODELING RAM Dual-Port RAM module or1200_dpram_256x32(clk_a, rst_a, ce_a, oe_a, addr_a, do_a, clk_b, rst_b, ce_b, we_b, addr_b, di_b ); parameter aw = 8; parameter dw = 32; // // Generic synchronous double-port RAM interface // input clk_a, rst_a; input ce_a, oe_a; input [aw-1:0] addr_a; output [dw-1:0] do_a; input clk_b, rst_b; input ce_b; input we_b; input [aw-1:0] addr_b; input [dw-1:0] di_b; reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content reg [aw-1:0] addr_a_reg; // RAM address registered assign do_a = (oe_a)? mem[addr_a_reg] : {dw{1'b0}}; // RAM read clk_a or posedge rst_a) if (rst_a) addr_a_reg <= #1 {aw{1'b0}}; else if (ce_a) addr_a_reg <= #1 addr_a; // // RAM write // clk_b) if (ce_b && we_b) mem[addr_b] <= #1 di_b; module Chung EPC