The X86 Assembly Language Instruction Nop Means

Size: px
Start display at page:

Download "The X86 Assembly Language Instruction Nop Means"

Transcription

1 The X86 Assembly Language Instruction Nop Means As little as 1 CPU cycle is "wasted" to execute a NOP instruction (the exact and other "assembly tricks", as explained also in this thread on Programmers. MOV EDI, EDI has the best performance as a 2-byte NOP on x86. operands - for example, add a is 0x2Y, and 0xX8 means "register 0 direct", so 0x28 is add a, r0. Optimizing subroutines in assembly language: An optimization guide for x86 FMUL means that a new FMUL instruction can start executing 2 clock cycles after a NOP (90) /3. ALU. Long NOP (0F 1F) /3. ALU. ENTER i, Some computer instruction sets include an instruction whose explicit In some cases, a NOP can have minor side effects, for example, on the Motorola Intel x86 CPU family, NOP, 1, 1 9 for i686, 0x90, 0x0f 0x1f, 0x90 The assembly instruction nop will most likely expand to mov r0. Intro to Assembly language It is a gentler introduction to assembly level programming than the x86. just a few instructions as opposed to thousands for the x86, There are various means of giving a semantics or meaning to a Miscellaneous Instructions. No operation nop Don't do anything but advance PC. The NOT instruction, for example, has the opcode w. Instructions are variable length for x86. What does rep, nop, mean in x86 assembly? This work consists of a low level analysis, considering assembly instructions, view of the x86 architecture processors, considering the use of reverse The set of instructions in assembly language is specific to each kind of means that the code is not always considered the most optimal in terms of time for a given. The X86 Assembly Language Instruction Nop Means >>>CLICK HERE<<< Its commands are binary, for example "wait" is 90h for x86. language commands to mnemonics like "jmp" for "jump" or "nop" for "wait". It is a relative jump, jumping to ff would mean jumping to the same byte, so to the parameter of jump. ARM is a family of instruction set architectures based on RISC architecture developed by but backward compatibility of (for example instruction) formats may mean more Unified Assembly Language which can be translated for *any* of ARM cores. However, instead of, like x86, reading which privilege level or

2 privilege. For example, here is a C function code fragment and the resulting assembly instructions: This means local variables can be accessed by referencing ebp. Note: Remember that the call x86 instruction is basically equivalent to nop, each nop is 1 byte long nop nop nop nop FUNCTION:, _-- This is the function entry. The idea behind Inline Assembly is to embed assembler instructions in your C/C++ code, using the asm keyword, when there's no option but to use assembly language. In that case, what you need is inline assembly, which means inserting arbitrary assembly snippets asm(".intel_syntax noprefix"), asm("mov eax, ebx"). x86 assembly language is a family of backward-compatible assembly translates to one or more bytes called an opcode, the NOP instruction translate to Here, B0 means 'Move a copy of the following value into AL', and 61 is a hexadecimal. This document is a reference manual for the LLVM assembly language. and analysis, while providing a natural means to debug and visualize the transformations. data for the x86 architecture is i8 144, which encodes the nop instruction:. For example, in Assembly x86, JMP is an unconditional jump instruction but its OPCode is 0xE9. For example: NOP means No-Operation (aka: Do NOTHING). such as the x86 and MIPS. Thus, there are instructions in both machine language and assembly language that move data Shifting means moving data to the right or The simplest of the control instruction is nop, it does nothing. CSE/EEE 230 Computer Organization and Assembly Language. Chapter 2 Notes What "interlocked pipeline stages" means will be made clear in Chapter The Intel x86 and x86_64

3 architectures are little endian. 8 nop # does nothing. I've seen things like x86 architecture but is there a universal x86 instruction set An Assembly language is largely defined by the processor instruction set In some system, 0x90 is defined as NOP, whereas in another system NOP has opcode 0x35. This means that within the same architecture family of processors, it. Here's a question: why is an OS "written entirely in assembly" able to achieve such Hurd, and of course there were never any plans to port it to anything but x86. This program can be optimized into a NOP instruction that does nothing (or a higher-level language will in some cases mean there is some sort of trade-off. One concrete example of this may be the ubiquitous x86 assemblers from various vendors. This means that if the size of an operation referring to an operand defined Assembly language instructions usually consist of an opcode mnemonic the extended mnemonics NOP and NOPR for BC and BCR with zero masks. In order to model the store in our abstract assembly language, we add two new it, say, by replacing it with some nop instruction which has no effect, or perhaps A side remark: on many architectures including the x86 and x86-64, appar- means that we may have to reconsider earlier lines, just as in the backwards. Setting a breakpoint in the generated code (from gdb, x86 / x86-64, arm) the procedure is to first replace the generated breakpoint by a nop instruction, and Thus when dumping the assembly under gdb, this kind of instructions would be because this means that something does not stay in IonMonkey and fallback. Assembly Commands Correspondence between a (relatively) high-level language and the CPU's Instruction The x86 family is a little-endian architecture target buffer, or need to place many copies of the payload, or use a NOP sled The stack and the heap are classic exploitation targets, but by no means the only.

4 least of which was hearing and answering requests from assembly language Appendix A Partial x86 Instruction Set Reference. 507 NOP: No Operation. 550 what it really means is this: ''You've asked me how to do something. So straight to it, the command i'm using to do this looks like this: OSX, see next tool), stands for list dynamically dependencies, works on dynamically linked binaries (see below for what this means), usage 'ldd filname' assembly language as input high level code as output X86 Assembly Syntax: AT&T vs INTEL. In assembly language(closest to machine language), NOP refers to ( No-op ) which simply means no operation or in other words to do nothing but move to next command. Hackers 0x90 opcode is most commonly used NOP for x86 systems. Introduction to Assembly Language : swansontec.com/sprogram.html a "Self Decryption Code" so what is this? this means the software decrypts a part of an OpCode that determines the nature of that instruction, example: in the x86 nop nop nop invoke SetDlgItemText,hWin,1001,addr Correct Good News: 14 assembly instructions account for 90% of what you need to know regarding Assembly Language for X86 7th ed. by Kip Irvine - Written specifically for 32 and 64-bit Adding something to the stack means the top of the stack is now at a lower memory address. NOP (pronounced Noh Op) - No Operation! This document describes the x86 and x86_64 implementations of the inline Causes the assembler to emit NOP instructions to align the next assembler instruction This means such is the responsibility of inline assembly programmer,. This document is a quick outline of the unusual form of assembly language used by the gc suite of Go compilers ( 6g, 8g, etc.). If you want to see what the instructions look like in assembly for a given architecture, NOPROF = 1 To see what instructions are defined for a given machine, say 32-bit Intel x86, look. We can instruct the Z80 to grab input from a device using the IN instruction, which a bit indicates that a control is activated and that a result of zero means the control is with writing programs for the ZX Spectrum using the Z80 assembly language. As you may have guessed the nop instruction instructs the

5 processor. >>>CLICK HERE<<< That means we could focus on exploitation and not reversing! If you can use arbitrary bytecode instructions, you'd be able to address register -giggles: file format elf64-x giggles-fixed: file format elf64-x86-64 Disassembly of problem: you don't have any absolute values in the assembly language, which means.

Practical Malware Analysis

Practical Malware Analysis Practical Malware Analysis Ch 4: A Crash Course in x86 Disassembly Revised 1-16-7 Basic Techniques Basic static analysis Looks at malware from the outside Basic dynamic analysis Only shows you how the

More information

CNIT 127: Exploit Development. Ch 1: Before you begin. Updated

CNIT 127: Exploit Development. Ch 1: Before you begin. Updated CNIT 127: Exploit Development Ch 1: Before you begin Updated 1-14-16 Basic Concepts Vulnerability A flaw in a system that allows an attacker to do something the designer did not intend, such as Denial

More information

Program Exploitation Intro

Program Exploitation Intro Program Exploitation Intro x86 Assembly 04//2018 Security 1 Univeristà Ca Foscari, Venezia What is Program Exploitation "Making a program do something unexpected and not planned" The right bugs can be

More information

Review Questions. 1 The DRAM problem [5 points] Suggest a solution. 2 Big versus Little Endian Addressing [5 points]

Review Questions. 1 The DRAM problem [5 points] Suggest a solution. 2 Big versus Little Endian Addressing [5 points] Review Questions 1 The DRAM problem [5 points] Suggest a solution 2 Big versus Little Endian Addressing [5 points] Consider the 32-bit hexadecimal number 0x21d3ea7d. 1. What is the binary representation

More information

CS429: Computer Organization and Architecture

CS429: Computer Organization and Architecture CS429: Computer Organization and Architecture Warren Hunt, Jr. and Bill Young Department of Computer Sciences University of Texas at Austin Last updated: October 1, 2014 at 12:03 CS429 Slideset 6: 1 Topics

More information

T Jarkko Turkulainen, F-Secure Corporation

T Jarkko Turkulainen, F-Secure Corporation T-110.6220 2010 Emulators and disassemblers Jarkko Turkulainen, F-Secure Corporation Agenda Disassemblers What is disassembly? What makes up an instruction? How disassemblers work Use of disassembly In

More information

Reverse Engineering Low Level Software. CS5375 Software Reverse Engineering Dr. Jaime C. Acosta

Reverse Engineering Low Level Software. CS5375 Software Reverse Engineering Dr. Jaime C. Acosta 1 Reverse Engineering Low Level Software CS5375 Software Reverse Engineering Dr. Jaime C. Acosta Machine code 2 3 Machine code Assembly compile Machine Code disassemble 4 Machine code Assembly compile

More information

Machine and Assembly Language Principles

Machine and Assembly Language Principles Machine and Assembly Language Principles Assembly language instruction is synonymous with a machine instruction. Therefore, need to understand machine instructions and on what they operate - the architecture.

More information

Return-orientated Programming

Return-orientated Programming Return-orientated Programming or The Geometry of Innocent Flesh on the Bone: Return-into-libc without Function Calls (on the x86) Hovav Shacham, CCS '07 Return-Oriented oriented Programming programming

More information

Functional Units of a Modern Computer

Functional Units of a Modern Computer Functional Units of a Modern Computer We begin this lecture by repeating a figure from a previous lecture. Logically speaking a computer has four components. Connecting the Components Early schemes for

More information

Intro to x86 Binaries. From ASM to exploit

Intro to x86 Binaries. From ASM to exploit Intro to x86 Binaries From ASM to exploit Intro to x86 Binaries I lied lets do a quick ctf team thing Organization Ideas? Do we need to a real structure right now? Mailing list is OTW How do we get more

More information

Lecture 2 Assembly Language

Lecture 2 Assembly Language Lecture 2 Assembly Language Computer and Network Security 9th of October 2017 Computer Science and Engineering Department CSE Dep, ACS, UPB Lecture 2, Assembly Language 1/37 Recap: Explorations Tools assembly

More information

Buffer Overflow Attack (AskCypert CLaaS)

Buffer Overflow Attack (AskCypert CLaaS) Buffer Overflow Attack (AskCypert CLaaS) ---------------------- BufferOverflow.c code 1. int main(int arg c, char** argv) 2. { 3. char name[64]; 4. printf( Addr;%p\n, name); 5. strcpy(name, argv[1]); 6.

More information

Intel X86 Assembler Instruction Set Opcode Table

Intel X86 Assembler Instruction Set Opcode Table Intel X86 Assembler Instruction Set Opcode Table x86 Instruction Set Reference. Derived from the September 2014 version of the Intel 64 and IA-32 LGDT, Load Global/Interrupt Descriptor Table Register.

More information

W4118: PC Hardware and x86. Junfeng Yang

W4118: PC Hardware and x86. Junfeng Yang W4118: PC Hardware and x86 Junfeng Yang A PC How to make it do something useful? 2 Outline PC organization x86 instruction set gcc calling conventions PC emulation 3 PC board 4 PC organization One or more

More information

Computer Processors. Part 2. Components of a Processor. Execution Unit The ALU. Execution Unit. The Brains of the Box. Processors. Execution Unit (EU)

Computer Processors. Part 2. Components of a Processor. Execution Unit The ALU. Execution Unit. The Brains of the Box. Processors. Execution Unit (EU) Part 2 Computer Processors Processors The Brains of the Box Computer Processors Components of a Processor The Central Processing Unit (CPU) is the most complex part of a computer In fact, it is the computer

More information

Introduction to Intel x86-64 Assembly, Architecture, Applications, & Alliteration. Xeno Kovah 2014 xkovah at gmail

Introduction to Intel x86-64 Assembly, Architecture, Applications, & Alliteration. Xeno Kovah 2014 xkovah at gmail Introduction to Intel x86-64 Assembly, Architecture, Applications, & Alliteration Xeno Kovah 2014 xkovah at gmail All materials is licensed under a Creative Commons Share Alike license. http://creativecommons.org/licenses/by-sa/3.0/

More information

Typical Processor Execution Cycle

Typical Processor Execution Cycle Typical Processor Execution Cycle Instruction Fetch Obtain instruction from program storage Instruction Decode Determine required actions and instruction size Operand Fetch Locate and obtain operand data

More information

Machine Code and Assemblers November 6

Machine Code and Assemblers November 6 Machine Code and Assemblers November 6 CSC201 Section 002 Fall, 2000 Definitions Assembly time vs. link time vs. load time vs. run time.c file.asm file.obj file.exe file compiler assembler linker Running

More information

Lecture 10 Return-oriented programming. Stephen Checkoway University of Illinois at Chicago Based on slides by Bailey, Brumley, and Miller

Lecture 10 Return-oriented programming. Stephen Checkoway University of Illinois at Chicago Based on slides by Bailey, Brumley, and Miller Lecture 10 Return-oriented programming Stephen Checkoway University of Illinois at Chicago Based on slides by Bailey, Brumley, and Miller ROP Overview Idea: We forge shellcode out of existing application

More information

ECE 486/586. Computer Architecture. Lecture # 7

ECE 486/586. Computer Architecture. Lecture # 7 ECE 486/586 Computer Architecture Lecture # 7 Spring 2015 Portland State University Lecture Topics Instruction Set Principles Instruction Encoding Role of Compilers The MIPS Architecture Reference: Appendix

More information

When an instruction is initially read from memory it goes to the Instruction register.

When an instruction is initially read from memory it goes to the Instruction register. CS 320 Ch. 12 Instruction Sets Computer instructions are written in mnemonics. Mnemonics typically have a 1 to 1 correspondence between a mnemonic and the machine code. Mnemonics are the assembly language

More information

Introduction to Intel x86-64 Assembly, Architecture, Applications, & Alliteration. Xeno Kovah

Introduction to Intel x86-64 Assembly, Architecture, Applications, & Alliteration. Xeno Kovah Introduction to Intel x86-64 Assembly, Architecture, Applications, & Alliteration Xeno Kovah 2014-2015 xeno@legbacore.com All materials is licensed under a Creative Commons Share Alike license. http://creativecommons.org/licenses/by-sa/3.0/

More information

Understand the factors involved in instruction set

Understand the factors involved in instruction set A Closer Look at Instruction Set Architectures Objectives Understand the factors involved in instruction set architecture design. Look at different instruction formats, operand types, and memory access

More information

Instruction Set Principles and Examples. Appendix B

Instruction Set Principles and Examples. Appendix B Instruction Set Principles and Examples Appendix B Outline What is Instruction Set Architecture? Classifying ISA Elements of ISA Programming Registers Type and Size of Operands Addressing Modes Types of

More information

Ethical Hacking. Assembly Language Tutorial

Ethical Hacking. Assembly Language Tutorial Ethical Hacking Assembly Language Tutorial Number Systems Memory in a computer consists of numbers Computer memory does not store these numbers in decimal (base 10) Because it greatly simplifies the hardware,

More information

Low-Level Essentials for Understanding Security Problems Aurélien Francillon

Low-Level Essentials for Understanding Security Problems Aurélien Francillon Low-Level Essentials for Understanding Security Problems Aurélien Francillon francill@eurecom.fr Computer Architecture The modern computer architecture is based on Von Neumann Two main parts: CPU (Central

More information

CNIT 127: Exploit Development. Ch 3: Shellcode. Updated

CNIT 127: Exploit Development. Ch 3: Shellcode. Updated CNIT 127: Exploit Development Ch 3: Shellcode Updated 1-30-17 Topics Protection rings Syscalls Shellcode nasm Assembler ld GNU Linker objdump to see contents of object files strace System Call Tracer Removing

More information

Intro x86 Part 3: Linux Tools & Analysis

Intro x86 Part 3: Linux Tools & Analysis Intro x86 Part 3: Linux Tools & Analysis Xeno Kovah 2009/2010 xkovah at gmail Approved for Public Release: 10-3348. Distribution Unlimited All materials is licensed under a Creative Commons Share Alike

More information

CSE 361S Intro to Systems Software Lab Assignment #4

CSE 361S Intro to Systems Software Lab Assignment #4 Due: Thursday, October 23, 2008. CSE 361S Intro to Systems Software Lab Assignment #4 In this lab, you will mount a buffer overflow attack on your own program. As stated in class, we do not condone using

More information

Reversing. Time to get with the program

Reversing. Time to get with the program Reversing Time to get with the program This guide is a brief introduction to C, Assembly Language, and Python that will be helpful for solving Reversing challenges. Writing a C Program C is one of the

More information

Computer Systems Architecture I. CSE 560M Lecture 3 Prof. Patrick Crowley

Computer Systems Architecture I. CSE 560M Lecture 3 Prof. Patrick Crowley Computer Systems Architecture I CSE 560M Lecture 3 Prof. Patrick Crowley Plan for Today Announcements Readings are extremely important! No class meeting next Monday Questions Commentaries A few remaining

More information

8051 Instruction Opcodes In Hexadecimal Order

8051 Instruction Opcodes In Hexadecimal Order 8051 Instruction Opcodes In Hexadecimal Order x86 opcode cheatsheet Opcode 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 8051 Microcontroller Instruction Set Table 1-4. Instruction Opcodes

More information

Introduction to the MIPS. Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University

Introduction to the MIPS. Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University Introduction to the MIPS Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University Introduction to the MIPS The Microprocessor without Interlocked Pipeline Stages

More information

Processor design - MIPS

Processor design - MIPS EASY Processor design - MIPS Q.1 What happens when a register is loaded? 1. The bits of the register are set to all ones. 2. The bit pattern in the register is copied to a location in memory. 3. A bit

More information

Assembly Language programming (3)

Assembly Language programming (3) EEE3410 Microcontroller Applications LABORATORY Experiment 3 Assembly Language programming (3) Name Class Date Class No. Marks Conditional Program Branching and Subroutine Call in 8051 Objectives To learn

More information

CS Bootcamp x86-64 Autumn 2015

CS Bootcamp x86-64 Autumn 2015 The x86-64 instruction set architecture (ISA) is used by most laptop and desktop processors. We will be embedding assembly into some of our C++ code to explore programming in assembly language. Depending

More information

MSRPC Heap Overflow Part II

MSRPC Heap Overflow Part II MSRPC Heap Overflow Part II Dave Aitel So a new approach is needed. As with any heap overflow, you get to chose a where and a what value, subject to certain constraints. If you chose a what value that

More information

CSE P 501 Compilers. x86 Lite for Compiler Writers Hal Perkins Autumn /25/ Hal Perkins & UW CSE J-1

CSE P 501 Compilers. x86 Lite for Compiler Writers Hal Perkins Autumn /25/ Hal Perkins & UW CSE J-1 CSE P 501 Compilers x86 Lite for Compiler Writers Hal Perkins Autumn 2011 10/25/2011 2002-11 Hal Perkins & UW CSE J-1 Agenda Learn/review x86 architecture Core 32-bit part only for now Ignore crufty, backward-compatible

More information

Name: CMSC 313 Fall 2001 Computer Organization & Assembly Language Programming Exam 1. Question Points I. /34 II. /30 III.

Name: CMSC 313 Fall 2001 Computer Organization & Assembly Language Programming Exam 1. Question Points I. /34 II. /30 III. CMSC 313 Fall 2001 Computer Organization & Assembly Language Programming Exam 1 Name: Question Points I. /34 II. /30 III. /36 TOTAL: /100 Instructions: 1. This is a closed-book, closed-notes exam. 2. You

More information

McSema: Static Translation of X86 Instructions to LLVM

McSema: Static Translation of X86 Instructions to LLVM McSema: Static Translation of X86 Instructions to LLVM ARTEM DINABURG, ARTEM@TRAILOFBITS.COM ANDREW RUEF, ANDREW@TRAILOFBITS.COM About Us Artem Security Researcher blog.dinaburg.org Andrew PhD Student,

More information

CS 31: Intro to Systems ISAs and Assembly. Kevin Webb Swarthmore College February 9, 2016

CS 31: Intro to Systems ISAs and Assembly. Kevin Webb Swarthmore College February 9, 2016 CS 31: Intro to Systems ISAs and Assembly Kevin Webb Swarthmore College February 9, 2016 Reading Quiz Overview How to directly interact with hardware Instruction set architecture (ISA) Interface between

More information

CS165 Computer Security. Understanding low-level program execution Oct 1 st, 2015

CS165 Computer Security. Understanding low-level program execution Oct 1 st, 2015 CS165 Computer Security Understanding low-level program execution Oct 1 st, 2015 A computer lets you make more mistakes faster than any invention in human history - with the possible exceptions of handguns

More information

CS 31: Intro to Systems ISAs and Assembly. Kevin Webb Swarthmore College September 25, 2018

CS 31: Intro to Systems ISAs and Assembly. Kevin Webb Swarthmore College September 25, 2018 CS 31: Intro to Systems ISAs and Assembly Kevin Webb Swarthmore College September 25, 2018 Overview How to directly interact with hardware Instruction set architecture (ISA) Interface between programmer

More information

EECE416 :Microcomputer Fundamentals and Design. X86 Assembly Programming Part 1. Dr. Charles Kim

EECE416 :Microcomputer Fundamentals and Design. X86 Assembly Programming Part 1. Dr. Charles Kim EECE416 :Microcomputer Fundamentals and Design X86 Assembly Programming Part 1 Dr. Charles Kim Department of Electrical and Computer Engineering Howard University www.mwftr.com 1 Multiple Address Access

More information

Interfacing Compiler and Hardware. Computer Systems Architecture. Processor Types And Instruction Sets. What Instructions Should A Processor Offer?

Interfacing Compiler and Hardware. Computer Systems Architecture. Processor Types And Instruction Sets. What Instructions Should A Processor Offer? Interfacing Compiler and Hardware Computer Systems Architecture FORTRAN 90 program C++ program Processor Types And Sets FORTRAN 90 Compiler C++ Compiler set level Hardware 1 2 What s Should A Processor

More information

Static Analysis I PAOLO PALUMBO, F-SECURE CORPORATION

Static Analysis I PAOLO PALUMBO, F-SECURE CORPORATION Static Analysis I PAOLO PALUMBO, F-SECURE CORPORATION Representing Data Binary numbers 1 0 1 1 NIBBLE 0xB 1 0 1 1 1 1 0 1 0xBD 1 0 1 1 1 1 0 1 0 0 1 1 1 0 0 1 BYTE WORD 0xBD 0x39 Endianness c9 33 41 03

More information

T Reverse Engineering Malware: Static Analysis I

T Reverse Engineering Malware: Static Analysis I T-110.6220 Reverse Engineering Malware: Static Analysis I Antti Tikkanen, F-Secure Corporation Protecting the irreplaceable f-secure.com Representing Data 2 Binary Numbers 1 0 1 1 Nibble B 1 0 1 1 1 1

More information

Spectre and Meltdown. Clifford Wolf q/talk

Spectre and Meltdown. Clifford Wolf q/talk Spectre and Meltdown Clifford Wolf q/talk 2018-01-30 Spectre and Meltdown Spectre (CVE-2017-5753 and CVE-2017-5715) Is an architectural security bug that effects most modern processors with speculative

More information

Instruction Set Architecture

Instruction Set Architecture CS:APP Chapter 4 Computer Architecture Instruction Set Architecture Randal E. Bryant Carnegie Mellon University http://csapp.cs.cmu.edu CS:APP Instruction Set Architecture Assembly Language View! Processor

More information

Instruction Set Architecture

Instruction Set Architecture CS:APP Chapter 4 Computer Architecture Instruction Set Architecture Randal E. Bryant Carnegie Mellon University http://csapp.cs.cmu.edu CS:APP Instruction Set Architecture Assembly Language View Processor

More information

Instruction Sets Ch 9-10

Instruction Sets Ch 9-10 Instruction Sets Ch 9-10 Characteristics Operands Operations Addressing Instruction Formats 1 Instruction Set (käskykanta) Collection of instructions that CPU understands Only interface to CPU from outside

More information

Instruction Set. Instruction Sets Ch Instruction Representation. Machine Instruction. Instruction Set Design (5) Operation types

Instruction Set. Instruction Sets Ch Instruction Representation. Machine Instruction. Instruction Set Design (5) Operation types Instruction Sets Ch 10-11 Characteristics Operands Operations Addressing Instruction Formats Instruction Set Collection of instructions that CPU understands Only interface to CPU from outside CPU executes

More information

Instruction Sets Ch 9-10

Instruction Sets Ch 9-10 Instruction Sets Ch 9-10 Characteristics Operands Operations Addressing Instruction Formats 1 Instruction Set (käskykanta) Collection of instructions that CPU understands Only interface to CPU from outside

More information

CS 161 Computer Security. Week of January 22, 2018: GDB and x86 assembly

CS 161 Computer Security. Week of January 22, 2018: GDB and x86 assembly Raluca Popa Spring 2018 CS 161 Computer Security Discussion 1 Week of January 22, 2018: GDB and x86 assembly Objective: Studying memory vulnerabilities requires being able to read assembly and step through

More information

Reverse Engineering II: Basics. Gergely Erdélyi Senior Antivirus Researcher

Reverse Engineering II: Basics. Gergely Erdélyi Senior Antivirus Researcher Reverse Engineering II: Basics Gergely Erdélyi Senior Antivirus Researcher Agenda Very basics Intel x86 crash course Basics of C Binary Numbers Binary Numbers 1 Binary Numbers 1 0 1 1 Binary Numbers 1

More information

CS 31: Intro to Systems ISAs and Assembly. Martin Gagné Swarthmore College February 7, 2017

CS 31: Intro to Systems ISAs and Assembly. Martin Gagné Swarthmore College February 7, 2017 CS 31: Intro to Systems ISAs and Assembly Martin Gagné Swarthmore College February 7, 2017 ANNOUNCEMENT All labs will meet in SCI 252 (the robot lab) tomorrow. Overview How to directly interact with hardware

More information

CHAPTER 5 A Closer Look at Instruction Set Architectures

CHAPTER 5 A Closer Look at Instruction Set Architectures CHAPTER 5 A Closer Look at Instruction Set Architectures 5.1 Introduction 293 5.2 Instruction Formats 293 5.2.1 Design Decisions for Instruction Sets 294 5.2.2 Little versus Big Endian 295 5.2.3 Internal

More information

Module 3 Instruction Set Architecture (ISA)

Module 3 Instruction Set Architecture (ISA) Module 3 Instruction Set Architecture (ISA) I S A L E V E L E L E M E N T S O F I N S T R U C T I O N S I N S T R U C T I O N S T Y P E S N U M B E R O F A D D R E S S E S R E G I S T E R S T Y P E S O

More information

Overview of the MIPS Architecture: Part I. CS 161: Lecture 0 1/24/17

Overview of the MIPS Architecture: Part I. CS 161: Lecture 0 1/24/17 Overview of the MIPS Architecture: Part I CS 161: Lecture 0 1/24/17 Looking Behind the Curtain of Software The OS sits between hardware and user-level software, providing: Isolation (e.g., to give each

More information

Assembly Language Programming of 8085

Assembly Language Programming of 8085 Assembly Language Programming of 8085 1. Introduction A microprocessor executes instructions given by the user Instructions should be in a language known to the microprocessor Microprocessor understands

More information

Machine Language, Assemblers and Linkers"

Machine Language, Assemblers and Linkers Machine Language, Assemblers and Linkers 1 Goals for this Lecture Help you to learn about: IA-32 machine language The assembly and linking processes 2 1 Why Learn Machine Language Last stop on the language

More information

Lab 10: Introduction to x86 Assembly

Lab 10: Introduction to x86 Assembly CS342 Computer Security Handout # 8 Prof. Lyn Turbak Wednesday, Nov. 07, 2012 Wellesley College Revised Nov. 09, 2012 Lab 10: Introduction to x86 Assembly Revisions: Nov. 9 The sos O3.s file on p. 10 was

More information

x86 assembly CS449 Fall 2017

x86 assembly CS449 Fall 2017 x86 assembly CS449 Fall 2017 x86 is a CISC CISC (Complex Instruction Set Computer) e.g. x86 Hundreds of (complex) instructions Only a handful of registers RISC (Reduced Instruction Set Computer) e.g. MIPS

More information

Real instruction set architectures. Part 2: a representative sample

Real instruction set architectures. Part 2: a representative sample Real instruction set architectures Part 2: a representative sample Some historical architectures VAX: Digital s line of midsize computers, dominant in academia in the 70s and 80s Characteristics: Variable-length

More information

Reverse Engineering II: The Basics

Reverse Engineering II: The Basics Reverse Engineering II: The Basics Gergely Erdélyi Senior Manager, Anti-malware Research Protecting the irreplaceable f-secure.com Binary Numbers 1 0 1 1 - Nibble B 1 0 1 1 1 1 0 1 - Byte B D 1 0 1 1 1

More information

Math 230 Assembly Programming (AKA Computer Organization) Spring 2008

Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 MIPS Intro II Lect 10 Feb 15, 2008 Adapted from slides developed for: Mary J. Irwin PSU CSE331 Dave Patterson s UCB CS152 M230 L10.1

More information

Assembly Language Programming of 8085

Assembly Language Programming of 8085 Assembly Language Programming of 8085 Topics 1. Introduction 2. Programming model of 8085 3. Instruction set of 8085 4. Example Programs 5. Addressing modes of 8085 6. Instruction & Data Formats of 8085

More information

THEORY OF COMPILATION

THEORY OF COMPILATION Lecture 10 Code Generation THEORY OF COMPILATION EranYahav Reference: Dragon 8. MCD 4.2.4 1 You are here Compiler txt Source Lexical Analysis Syntax Analysis Parsing Semantic Analysis Inter. Rep. (IR)

More information

Chapter 4 Processor Architecture: Y86 (Sections 4.1 & 4.3) with material from Dr. Bin Ren, College of William & Mary

Chapter 4 Processor Architecture: Y86 (Sections 4.1 & 4.3) with material from Dr. Bin Ren, College of William & Mary Chapter 4 Processor Architecture: Y86 (Sections 4.1 & 4.3) with material from Dr. Bin Ren, College of William & Mary 1 Outline Introduction to assembly programing Introduction to Y86 Y86 instructions,

More information

Review of instruction set architectures

Review of instruction set architectures Review of instruction set architectures Outline ISA and Assembly Language RISC vs. CISC Instruction Set Definition (MIPS) 2 ISA and assembly language Assembly language ISA Machine language 3 Assembly language

More information

Sample Exam I PAC II ANSWERS

Sample Exam I PAC II ANSWERS Sample Exam I PAC II ANSWERS Please answer questions 1 and 2 on this paper and put all other answers in the blue book. 1. True/False. Please circle the correct response. a. T In the C and assembly calling

More information

Problem with Scanning an Infix Expression

Problem with Scanning an Infix Expression Operator Notation Consider the infix expression (X Y) + (W U), with parentheses added to make the evaluation order perfectly obvious. This is an arithmetic expression written in standard form, called infix

More information

The MARIE Architecture

The MARIE Architecture The MARIE Machine Architecture that is Really Intuitive and Easy. We now define the ISA (Instruction Set Architecture) of the MARIE. This forms the functional specifications for the CPU. Basic specifications

More information

Page 1. Structure of von Nuemann machine. Instruction Set - the type of Instructions

Page 1. Structure of von Nuemann machine. Instruction Set - the type of Instructions Structure of von Nuemann machine Arithmetic and Logic Unit Input Output Equipment Main Memory Program Control Unit 1 1 Instruction Set - the type of Instructions Arithmetic + Logical (ADD, SUB, MULT, DIV,

More information

EC 413 Computer Organization

EC 413 Computer Organization EC 413 Computer Organization Review I Prof. Michel A. Kinsy Computing: The Art of Abstraction Application Algorithm Programming Language Operating System/Virtual Machine Instruction Set Architecture (ISA)

More information

CS , Fall 2004 Exam 1

CS , Fall 2004 Exam 1 Andrew login ID: Full Name: CS 15-213, Fall 2004 Exam 1 Tuesday October 12, 2004 Instructions: Make sure that your exam is not missing any sheets, then write your full name and Andrew login ID on the front.

More information

Systems Architecture I

Systems Architecture I Systems Architecture I Topics Assemblers, Linkers, and Loaders * Alternative Instruction Sets ** *This lecture was derived from material in the text (sec. 3.8-3.9). **This lecture was derived from material

More information

Computer Architecture

Computer Architecture Computer Architecture Chapter 2 Instructions: Language of the Computer Fall 2005 Department of Computer Science Kent State University Assembly Language Encodes machine instructions using symbols and numbers

More information

Y86 Processor State. Instruction Example. Encoding Registers. Lecture 7A. Computer Architecture I Instruction Set Architecture Assembly Language View

Y86 Processor State. Instruction Example. Encoding Registers. Lecture 7A. Computer Architecture I Instruction Set Architecture Assembly Language View Computer Architecture I Instruction Set Architecture Assembly Language View Processor state Registers, memory, Instructions addl, movl, andl, How instructions are encoded as bytes Layer of Abstraction

More information

X86 Review Process Layout, ISA, etc. CS642: Computer Security. Drew Davidson

X86 Review Process Layout, ISA, etc. CS642: Computer Security. Drew Davidson X86 Review Process Layout, ISA, etc. CS642: Computer Security Drew Davidson davidson@cs.wisc.edu From Last Time ACL-based permissions (UNIX style) Read, Write, execute can be restricted on users and groups

More information

administrivia today start assembly probably won t finish all these slides Assignment 4 due tomorrow any questions?

administrivia today start assembly probably won t finish all these slides Assignment 4 due tomorrow any questions? administrivia today start assembly probably won t finish all these slides Assignment 4 due tomorrow any questions? exam on Wednesday today s material not on the exam 1 Assembly Assembly is programming

More information

Machine-level Representation of Programs. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University

Machine-level Representation of Programs. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University Machine-level Representation of Programs Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Program? 짬뽕라면 준비시간 :10 분, 조리시간 :10 분 재료라면 1개, 스프 1봉지, 오징어

More information

ISA and RISCV. CASS 2018 Lavanya Ramapantulu

ISA and RISCV. CASS 2018 Lavanya Ramapantulu ISA and RISCV CASS 2018 Lavanya Ramapantulu Program Program =?? Algorithm + Data Structures Niklaus Wirth Program (Abstraction) of processor/hardware that executes 3-Jul-18 CASS18 - ISA and RISCV 2 Program

More information

Chapter 2. Instruction Set Principles and Examples. In-Cheol Park Dept. of EE, KAIST

Chapter 2. Instruction Set Principles and Examples. In-Cheol Park Dept. of EE, KAIST Chapter 2. Instruction Set Principles and Examples In-Cheol Park Dept. of EE, KAIST Stack architecture( 0-address ) operands are on the top of the stack Accumulator architecture( 1-address ) one operand

More information

CNIT 127: Exploit Development. Ch 2: Stack Overflows in Linux

CNIT 127: Exploit Development. Ch 2: Stack Overflows in Linux CNIT 127: Exploit Development Ch 2: Stack Overflows in Linux Stack-based Buffer Overflows Most popular and best understood exploitation method Aleph One's "Smashing the Stack for Fun and Profit" (1996)

More information

CS412/CS413. Introduction to Compilers Tim Teitelbaum. Lecture 21: Generating Pentium Code 10 March 08

CS412/CS413. Introduction to Compilers Tim Teitelbaum. Lecture 21: Generating Pentium Code 10 March 08 CS412/CS413 Introduction to Compilers Tim Teitelbaum Lecture 21: Generating Pentium Code 10 March 08 CS 412/413 Spring 2008 Introduction to Compilers 1 Simple Code Generation Three-address code makes it

More information

COS 140: Foundations of Computer Science

COS 140: Foundations of Computer Science COS 140: Foundations of Computer Science CPU Organization and Assembly Language Fall 2018 CPU 3 Components of the CPU..................................................... 4 Registers................................................................

More information

Sneha Rajguru & Prajwal Panchmahalkar

Sneha Rajguru & Prajwal Panchmahalkar Sneha Rajguru & Prajwal Panchmahalkar Sneha Rajguru Security Consultant, Payatu Technologies Pvt Ltd. @sneharajguru Prajwal Panchmahalkar Red Team Lead Security Engineer, VMware @pr4jwal Introduction to

More information

Representation of Information

Representation of Information Representation of Information CS61, Lecture 2 Prof. Stephen Chong September 6, 2011 Announcements Assignment 1 released Posted on http://cs61.seas.harvard.edu/ Due one week from today, Tuesday 13 Sept

More information

Hardware Level Organization

Hardware Level Organization Hardware Level Organization Intro MIPS 1 Major components: - memory - central processing unit - registers - the fetch/execute cycle CPU PC IR Ex Unit MAR MBR I/O AR I/O BR System Bus Main Memory 0 (the

More information

Lecture 4: Instruction Set Architecture

Lecture 4: Instruction Set Architecture Lecture 4: Instruction Set Architecture ISA types, register usage, memory addressing, endian and alignment, quantitative evaluation Reading: Textbook (5 th edition) Appendix A Appendix B (4 th edition)

More information

Chapter 5. A Closer Look at Instruction Set Architectures

Chapter 5. A Closer Look at Instruction Set Architectures Chapter 5 A Closer Look at Instruction Set Architectures Chapter 5 Objectives Understand the factors involved in instruction set architecture design. Gain familiarity with memory addressing modes. Understand

More information

CPS104 Recitation: Assembly Programming

CPS104 Recitation: Assembly Programming CPS104 Recitation: Assembly Programming Alexandru Duțu 1 Facts OS kernel and embedded software engineers use assembly for some parts of their code some OSes had their entire GUIs written in assembly in

More information

Black Box Debugging of Embedded Systems

Black Box Debugging of Embedded Systems Black Box Debugging of Embedded Systems Introduction: Alexandru Ariciu Background in hacking Worked as a hacker for my whole life Worked in corporate security before (Pentester) Currently an ICS Penetration

More information

Assembly Language programming (1)

Assembly Language programming (1) EEE3410 Microcontroller Applications LABORATORY Experiment 1 Assembly Language programming (1) Name Class Date Class No. Marks Familiarisation and use of 8051 Simulation software Objectives To learn how

More information

Instruction Set Architectures

Instruction Set Architectures Instruction Set Architectures ISAs Brief history of processors and architectures C, assembly, machine code Assembly basics: registers, operands, move instructions 1 What should the HW/SW interface contain?

More information

Lab 3. The Art of Assembly Language (II)

Lab 3. The Art of Assembly Language (II) Lab. The Art of Assembly Language (II) Dan Bruce, David Clark and Héctor D. Menéndez Department of Computer Science University College London October 2, 2017 License Creative Commons Share Alike Modified

More information

Is stack overflow still a problem?

Is stack overflow still a problem? Morris Worm (1998) Code Red (2001) Secure Programming Lecture 4: Memory Corruption II (Stack Overflows) David Aspinall, Informatics @ Edinburgh 31st January 2017 Memory corruption Buffer overflow remains

More information

A crash course in MIPS assembly programming

A crash course in MIPS assembly programming A crash course in MIPS assembly programming Computer Architecture 1DT016 distance Fall 2017 http://xyx.se/1dt016/index.php Per Foyer Mail: per.foyer@it.uu.se 1 MIPS Our processor Microprocessor without

More information