Lecture 4: Instruction Set Architecture

Transcription

1 Lecture 4: Instruction Set Architecture ISA types, register usage, memory addressing, endian and alignment, quantitative evaluation Reading: Textbook (5 th edition) Appendix A Appendix B (4 th edition) 1 What Is ISA? Instruction set architecture is the structure of a computer that a machine language programmer (or a compiler) must understand to write a correct (timing independent) program for that machine. For IBM System/360, 1964 ISA types: Stack, Accumulator, and General-purpose register ISA is mature and stable Why do we study it? 2 1

2 MIPS: A "Typical" RISC ISA 32-bit fixed format instruction (3 formats) bit GPR (R0 contains zero, DP takes pair) 3-address, reg-reg arithmetic instruction Single address mode for load/store: base + displacement no indirection Simple branch conditions Delayed branch 3 Example: MIPS Assembly Code ; C code: ; c = (a <= b)? (a - b) : (b - a); ; a -- MEM(4), b -- MEM(8), c -- MEM(12) ; R8 -- a, R9 -- b, R10 -- tmp, R11 -- c lw $8, 4($0) ; load a to reg 8 lw $9, 8($0) ; load b to reg 9 slt $10, $9, $8 ; set reg 10 if b < a beq $10, $0, +2 ; no, skip next two sub $11, $9, $8 ; c=b-a beq $0, $0, +1 ; skip next sub $11, $8, $9 ; c=a-b sw $9, 12($0) ; store c 4 2

3 MIPS Instruction Format (32-bit) Register-Register Op Op Op Rs1 Register-Immediate Branch Op Rs2 Rd Rs1 Rd immediate target Opx Jump / Call Rs1 Rs2 immediate 5 Example: MIPS Binary Code _00000_01000_ // lw $8, 4($0) _00000_01001_ // lw $9, 8($0) _01001_01000_01010_00000_ // slt $10, $9, $ _01010_00000_ // beq $10, $0, _01001_01000_01011_00000_ // sub $11, $9, $ _00000_00000_ // beq $0, $0, _01000_01001_01011_00000_ // sub $11, $8, $ _00000_01011_ // sw $9, 12($0) 6 3

4 Stack ISA Implicit operands on stack Ex. C = A + B Push A Push B Add Pop C Good code density; used in 60 s-70 s; now in Java VM 7 Accumulator ISA The accumulator provides an implicit input, and is the implicit place to store the result. Ex. C = A + B Load A Add B Store C Used before

5 General-purpose Registers General-purpose registers are preferred by compilers Reduce memory traffic Improve program speed Improve code density Usage of general-purpose registers Holding temporal variables in expression evaluation Passing parameters Holding variables GPR and RISC and CISC RISC ISA is extensively used for desktop, server, and embedded: MIPS, PowerPC, UltraSPARC, ARM, MIPS16, Thumb CISC: IBM 360/370, VAX, and Intel 80x86 9 Variants of GPR Architecture Number of operands in ALU instructions: two or three Add R1, R2, R3 Add R1, R2 Maximal number of memory operands in ALU instructions: zero, one, two, or three Load R1, A Load R1, A Load R2, B Add R3, R1, B Add R3, R1, R2 Three popular combinations register-register (load-store): 0 memory, 3 operands register-memory: 1 memory, 2 operands memory-memory: 2 memories, 2 operands; or 3 memories, 3 operands 10 5

6 Register-Memory Architecture There is no implicit operand One input operand is register, and one in memory Ex. C = A + B Load R1, A Add R3, R1, B Store R3, C Processors include VAX, 80x86 11 Register-Register (Load-Store) Both operands are registers Values in memory must be loaded into a register and stored back Ex. C = A + B Load R1, A Load R2, B Add R3, R1, R2 Store R3, C Processors: MIPS, SPARC 12 6

7 How Many Registers? If the number of registers increases: Allocate more variables in registers (fast accesses) Reducing spill code Reducing memory traffic Longer register specifiers (difficult encoding) Increasing register access time (physical registers) More registers to save in context switch MIPS64: 32 general-purpose registers 13 ISA and Performance CPU time = #inst CPI cycle time RISC with Register-Register instructions Simple, fixed-length instruction encoding Simple code generation Regularity in CPI Higher instruction counts Lower instruction density CISC with Register-memory instructions No extra load to accessing memory operands Easy encoding (?) Operands not equivalent Restricted #registers due to memory address encoding Irregularity in CPI 14 7

8 Memory Addressing Instructions see registers, constant values, and memory Addressing mode decides how to specify an object to access Object can be memory location, register, or a constant Memory addressing is complicated Memory addressing involves many factors Memory addressing mode Object size byte ordering alignment For a memory location, its effective address is calculated in a certain form of register content, immediate address, and PC, as specified by the addressing mode 15 Little or Big: Where to Start? Byte ordering: Where is the first byte? Big-endian:IBM, SPARC, Mororola Little-endian: Intel, DEC Supporting both: MIPS, PowerPC Number 0x5678 Little-endian Big-endian

9 Alignment Align n-byte objects on n-byte boundaries (n = 1, 2, 4, 8) One aligned position, n-1 misaligned positions Misaligned access is undesirable Expensive logic, slow references Aligning in registers may be necessary for bytes and half words 17 MIPS Data Addressing Modes Register ADD $16, $7, $8 Immediate ADDI $17, $7, 100 Displacement LW $18, 100($9) Only these three are supported for data addressing 18 9

10 Storage Used by Compilers Register storage Holding temporary variables in expression evaluation Passing parameters Holding variables Memory storages consists of Stack: to hold local variables Global data area: to hold statically declared objects Heap: to hold dynamic objects 19 Memory Addressing Seen in CISC Direct (absolute) Register indirect Indexed Scaled Autoincrement Autodecrement Memory indirect And more ADD R1, (1001) SUB R2, (R1) ADD R1, (R2 + R3) SUB R2, 100(R2)[R3] ADD R1, (R2)+ SUB R2, -(R1) ADD (see textbook p-a9) 20 10

11 Choosing Memory Addressing Modes Choosing complex addressing modes Close to addressing in high-level language May reduce instruction count (thus fast) Increase implementation complexity (may increase cycle time) Increase CPI RISC ISA comes with simple memory addressing, and CISC ISA with complex ones 21 Frequency of Addressing Modes? Usage of address modes, VAX machine, SPEC

12 Usage of Immediate Operands In RISC Alpha, SPEC CINT2000 & CFP Immediate Size in RISC Alpha, SPEC CINT2000 & CFP2000; <6% are ve; 50-70% 24 fit in 8 bits; 75-80% in 16 bits 12

13 Displacement Size in RISC Displacement bit size: Alpha ISA, SPEC CPU2000 Integer and FP; most +ve; majority of large 14+ bits are ve; about 1% of 25 displacements need more than 16 bits. Operands size, type and format In MIPS Opcode encodes operand size Ex. ADD for signed integer, ADDU for unsigned integer, ADD.D for double-precision FP Most common types include Integer: complement binary numbers Character: ASCII Floating point: IEEE standard 754, single-precision or double-precision Decimal format 4-bits for one decimal digit (0-9), one byte for two decimal digits Necessary for business applications Fixed Point format in DSP processors: Representing fractions in (-1, +1) fixed point =

14 Dynamic Instruction Mix (MIPS) SPEC2K Int SPEC2K FP Load 26% 15% Store 10% 2% Add 19% 23% Compare 5% 2% Cond br 12% 4% Cond mv 2% 0% Jump 1% 0% LOGIC 18% 4% FP load 15% FP store 7% FP others 19% 27 Compiler Effects Architectures change for the needs of compilers How do compilers use registers? How many? How do compilers use addressing modes? Anything that compilers do not like? 28 14