Allevia'ng memory bandwidth pressure with wavefront temporal blocking and diamond 'ling Tareq Malas* Georg Hager Gerhard Wellein David Keyes*

Transcription

1 Allevia'ng memory bandwidth pressure with wavefront temporal blocking and diamond 'ling Tareq Malas* Georg Hager Gerhard Wellein David Keyes* Erlangen Regional Compu0ng Center, Germany *King Abdullah Univ. of Sci. & Tech. (KAUST), Saudi Arabia

2 Memory bandwidth starved stencil computadons, with spadal blocking Example system Double precision Domain size: cores Intel Ivy Bridge 7- pt 3D stencil with spadal blocking Constant symmetric coefficients Performance limit = attainable memory BW Memory Bytes / LUP = 40 GB / s 24 B / LUP =1.67 GLUP / s

3 Stencil computadons challenges in future architectures Each node may have up to a thousand shared- memory cores with: small cache size per core small memory bandwidth per core complex cache sharing among cores expensive synchronizadon among all the cores interacdon between heterogeneous processors Expensive synchronizadon aner each iteradon

4 Diamond Dling Improves the performance on shared and distributed memory systems High data reuse, reducing memory accesses Provides independent space- Dme blocks to reduce synchronizadon between threads and nodes overlap computadon with communicadon TessellaDon reduces the overhead of handling the boundaries of subdomains, sockets, and heterogeneous processors Time Space

5 Diamond Dling Improves the performance on shared and distributed memory systems High temporal reuse, reducing memory accesses Provides independent space- Dme blocks to reduce synchronizadon between threads and nodes overlap computadon with communicadon TessellaDon reduces the overhead of handling the boundaries of subdomains, sockets, and heterogeneous processors Time Space

6 Diamond Dling Improves the performance on shared and distributed memory systems high temporal reuse, reducing memory accesses provides independent space- Dme blocks to reduce synchronizadon between threads and nodes overlap computadon with communicadon TessellaDon reduces the overhead of handling the boundaries of subdomains, sockets, and heterogeneous processors Time Space Y

7 Diamond Dling Improves the performance on shared and distributed memory systems high temporal reuse, reducing memory accesses provides independent space- Dme blocks to reduce synchronizadon between threads and nodes overlap computadon with communicadon tesselladon reduces the overhead of handling the boundaries of subdomains, sockets, and heterogeneous processors TessellaDon reduces the overhead of handling the boundaries of subdomains, sockets, and heterogeneous processors

8 Wavy assignments for larger diamonds

9 Related work Diamond Dling technique has drawn the atendon of the research community in recent years Orozco, D., & Gao, G. (2009). Diamond 0ling: A 0ling framework for 0me- iterated scien0fic applica0ons. Strzodka, R., Shaheen, M., Pajak, D., & Seidel, H.- P. (2011). Cache Accurate Time Skewing in Itera0ve Stencil Computa0ons. InternaDonal Conference on Parallel Processing (pp ). BandishD, V., Pananilath, I., & Bondhugula, U. (2012). Tiling stencil computa0ons to maximize parallelism. In Proceedings of the InternaDonal Conference on High Performance CompuDng, Networking, Storage and Analysis (pp. 40:1 40:11). Zhou, X. (2013). Tiling op0miza0ons for stencil computa0ons. PhD thesis, University of Illinois at Urbana- Champaign. Grosser, T., Verdoolaege, S., Cohen, A., & Sadayappan, P. (2013). The Promises of Hybrid Hexagonal/Classical Tiling for GPU. Grosser, T., Verdoolaege, S., Cohen, A., & Sadayappan, P. (2014). The rela0on between diamond 0ling and hexagonal 0ling. Proceedings of the 1 st InternaDonal Workshop on High- Performance Stencil ComputaDons (pp ). Vienna, Austria.

10 1- Core- Wavefront temporal blocking + Diamond Dling (1CWD) Extruded diamonds Diamond Dling and domain decomposidon across the Y- axis Wavefront temporal blocking along the Z- axis No decomposidon across the X- axis t Y Z "# "$ "% "& "' "( Strzodka, R., Shaheen, M., Pajak, D., & Seidel, H.- P. (2011), Cache Accurate Time Skewing in Itera0ve Stencil Computa0ons. " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " #

11 MulD- Core- Wavefront temporal blocking + Diamond Dling (MCWD) Advantages: Can run at small domain sizes on many- core architectures, as it does not require concurrent Dle for each thread Large reducdon in cache size requirements compared to having 1 cache block per core UDlizes the shared cache between cores and hardware threads of modern processors " t Y Z "#$%&'( "#$%&') "#$%&'* "#$%&'+ " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " #

12 Diamond Dling temporal blocking Setup Double precision Domain size: cores Intel Ivy Bridge MCWD achieves 1.11x speedup over 1CWD 2.14x speedup over spadally blocked code

13 Coming enhancement Assign threads to muldple groups instead of one large threads group Use hierarchical cache blocking to improve the data reuse at different cache levels " t Y Z "#$%&'( "#$%&') "#$%&'* "#$%&'+ " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " #