ARM Cortex-M4 Architecture and Instruction Set 2: General Data Processing Instructions

Transcription

1 ARM Cortex-M4 Architecture and Instruction Set 2: General Data Processing Instructions M J Brockway January 31, 2016

2 Cortex-M4 Machine Instructions - simple example... main FUNCTION ; initialize registers MOV r0, #10 ; Starting loop counter value MOV r1, #0 ; starting result ; Calculating loop ADD r1, r0 ; R1 = R1 + R0 SUBS r0, #1 ; Decrement R0, update flag ( S suffix) BNE loop ; If result not zero jump to loop ; Result is now in R1 deadloop B deadloop ; Infinite loop ENDFUNC END ; End of file

3 MOV, MVN Syntax MOV{S}{cond} Rd, operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, operand2 The MOV instructons copy the value of the second operand to Rd; MVN copies the complement of this value to Rd. where: S is an optional suffix. If included, the condition code flags are updated on the result of the operation. cond is an optional condition code (see below). Rd is the destination - always a register. operand2 is a flexible second operand: one of a constant: #const where 32-bit const is either a left-shifted byte or a constant of one of the forms 00XY00XY, XY00XY00, XYXYXYXY. a register with optional shift (see below). imm16 is any value in the range

4 MOV, MVN - Examples MOV R3, #0x1F0000 value in R3 set to 0x1F0000 MVN R3, #0x1F0000 value in R3 set to 0xFFE0FFFFF MOV R3, #0x2C0000 ORR R3, #0x5F value in R3 set to 0x2C0000 then bitwise OR d with 0x5F Effect is to set R3 to 0x2C005F. Why can t this be done in a single operation? MOV R3, R0 value in R0 copied to R3 MOVS R3, R0 value in R0 copied to R3 and condition flags set according to result Eg Z is set if result is 0; N is set if result is negative MVNS R3, R0 complement of value in R0 copied to R3 and condition flags set according to result

5 Condition Code Suffixes (Refer to the condition flags in the last lecture; not a comprehensive list!) EQ equal: Z==1 NE not equal: Z==0 HS higher or same, unsigned: C==1 HI higher, unsigned: C==1 and Z==0 LO lower, unsigned: C==0 LS lower or same, unsigned: C==0 or Z==1 MI negative: N==1, PL positive or zero: N==0, VS overflow: V==1 VC no overflow: V==0 GE greater than or equal, signed: N==V GT greater than, signed: N==V and Z==0 LE less than or equal, signed: N!=V or Z==1 LT less than, signed: N!=V

6 Conditional execution examples MOVEQ R3, #0x1F0000 If Z flag is set, set value in R3 to 0x1F0000 MVNNE R3, #0x1F0000 if Z flag is clear, set value in R3 to 0x1F0000 MOVLE R3, R0 If signed less-or-equal, copy value in R0 to R3 MOVSGT R3, R0 If signed greater-than, copy value in R0 to R3 and set condition flags according to result MVNSLE R3, R0 If signed less-or-equal, copy complement of value in R0 to R3 and set condition flags according to result MOVS R3, #0 MOVEQ R4, R0 Will the second instruction be executed? (Yes - but why?)

7 MOV, MVN - the Flexible second operand The second operand can be a register with optional shift. The syntax is MOV{S}{cond} Rd, Rs{, shift} MVN{S}{cond} Rd, Rs{, shift} The optional shift, when present, denotes one of ASR #n Arithmetic shift right n bits, 1 n 32. LSL #n Logical shift left n bits, 1 n 31. LSR #n Logical shift right n bits, 1 n 32. ROR #n Rotate right n bits, 1 n 31. RRX Rotate right one bit, with extend. If present, the shift is applied to the value in register Rs then copied (complemented in case of MVN) into Rd. If absent, we have just a plain register-to-register copy.

8 More examples MOVEQ R3, R2, ASR #1 If Z flag is set, set value in R3 to contents of R2 arithmetically shifted right 1 bit MVNNE R3, R0, LSL #3 if Z flag is clear, set value in R3 to complement of contents of R0 logically shifted left 3 bits MOVS R3, R0, ROR #4 Copy value in R0 right-rotated 4 bits to R3 and set condition flags according to result MVNS R3, R0, RRX Copy complement of value in R0 rotated one bit to the right with extend, to R3 and set condition flags according to result We do not need an arithmetic left shift - why not? We do not need a left-rotate - why not?

9 The Flexible second operand - hardware setup barrel shifter ALU The arithmetic-logic unit (ALU) performs arithmetic operations (add, subtract, negate, add-with-carry,...) or logical operations (bitwise AND, OR, XOR, complement,...) on one or two 32-bit inputs. One input is via a barrel shifter which performs arithmetical or logical shifts or rotates on the 32-bit input in one clock cycle, passing the result on to the ALU. The ARM thus does MOV (or whatever) with a shifted/rotated operand in a single operation. MOV, MVN take only a single operand: the upper input to the ALU is not used. However, we next meet some two-input operations...

10 Arithmetic Syntax op{s}{cond} {Rd,} Rn, operand2 where: op is one of ADD - add: Rd Rn + operand2 ADC - add with carry: Rd Rn + operand2 + C SUB - subtract: Rd Rn - operand2 SBC - subtract: Rd Rn - operand2 -!C RSB - reverse subtract: Rd operand2 - Rn Optional S suffix and cond condition are as we defined above. Rd, Rn are registers: Rd is the destination. Its specification is optional: if absent, Rd=Rn. operand2 is a flexible second operand, a byte-sized immediate value or a register with optional shift, as seen above. ADD, SUB also allow operand2 to be any value in the range (12 bits). N,Z,C,V flags updated (with S option) according to result.

11 Arithmetic Examples ADD R0, R1, R1, LSL #2 R0 R1 + (R1 << 2) ADDEQ R0, R1, #1 If Z flag is set, R0 R1 + 1 ADDS R0, #1 R0 R0 + 1 ADC R3, R4, R5 R3 R4 + R5 + C SUBS R0, R0, #1 R0 R0-1; set condition flags SBCNES R0, R1, R2 If Z flag is clear, R0 R0 - R2 -!C; set condition flags RSBS R0, R1 R0 R1 - R0; set flags

12 Logic Syntax op{s}{cond} {Rd,} Rn, operand2 where: op is one of AND - bitwise AND: Rd Rn & operand2 ORR - bitwise OR: Rd Rn operand2 EOR - bitwise exclusive OR: Rd Rn ôperand2 BIC - bitwise AND NOT: Rd Rn &!(operand2); clears bits in Rb marked by operand2 ORN - bitwise OR NOT: Rd Rn!(operand2) Optional S suffix and cond condition are as we defined above. Rd, Rn are registers: Rd is the destination. Its specification is optional: if absent, Rd is Rn. operand2 is a flexible second operand, a byte-sized immediate value or a register with optional shift, as seen above. With S option, N,Z updated according to result (possibly also C during evaluation of operand2)

13 Logic Examples AND R0, R1, R2, LSL #2 R0 R1 & (R1 << 2) ORREQ R0, R1, #0x1F If Z flag is set, R0 R1 0x1F EORS R0, R1 R0 R0 ˆR1; set flags BIC R3, R4 R3 R3 &!R4: bits set in R4 are cleared in R3

14 Shifts We have seen these pure barrel-shifter operations combined with other operations via the flexible operand2. They can also be stand-alone operations... Syntax op{s}{cond} Rd, Rn, Rs op{s}{cond} Rd, Rn, #n RRX{S}{cond} Rd, Rn where: op is one of ASR - arithmetic shift right LSL - logical shift left LSR - logical shist right ROR - rotate right Optional S suffix and cond condition are as we defined above.

15 Shifts Rd is the destination register Rn is register holding the value to be shifted Register Rs holds valaue of shift length - only the lowest order byte applies #n is a shift length: ASR 1 n 32; LSL 0 n 31; LSR 1 n 32; ROR 1 n 31 RXX sets Rd to bits in Rn rotated right 1 bit. With S option, N,Z updated according to result; if shift length > 0, C updated to last bit shifeted out.

16 Comparisons These always update the condition flags, without needing an S suffix. There is no destination register: the only purpose is to update the flags. Syntax: CMP{cond} Rn, operand2 CMN{cond} Rn, operand2 TST{cond} Rn, operand2 TEQ{cond} Rn, operand2 where: Rn register holds the first operand; operand2 is a flexible second operand, as seen above. CMP subtracts the operands and CMN adds the operands, setting the condition flags but discarding the result. Cf SUBS, ADDS. CMP R0, R1 sets Z and C if R0==R1, sets N if R1 > R0, sets C if R0 > R1 TST bitwise ANDs the operands and TEQ bitwise EORs the operands, setting the condition flags but discarding the result. Cf ANDS, EORS.

17 Comparisons - Examples int c= 10; while ( c!= 0 ) { c--; } MOV r0, #10 Loop CMP r0, #0 BEQ exitloop SUB r0, r0, #1 B loop exitloop

18 Comparisons - Examples if ( r1 == 22 ) r0++; else r0--; CMP r1, #22 BNE else ADD r0,#1 B endif else SUB r0,#1 endif

19 Comparisons - Examples switch (r4) { case 1: r0= 56; break; case 2: r0= 123; break; } CMP r4,#1 BNE try2 MOV r0,#56 B endcase try2 CMP r4,#2 BNE endcase MOV r0,#123 endcase

20 References UM10562.pdf: The LPC408x/407x User Manual DUI0553A cortex m4 dgug.pdf: The Cortex M4 Generic User Guide Both these documents are linked to the home page of the module, in the group Resources for the LPC4088. The Generic User Guide is well worth reading in conjunction with these lecture slides and in general provides a fairly readable technical but not-too-technical introduction. In connection with this lecture see especially the GUG sections 3.3 and 3.5.