Chapter 2 Instructions Sets. Hsung-Pin Chang Department of Computer Science National ChungHsing University

Transcription

1 Chapter 2 Instructions Sets Hsung-Pin Chang Department of Computer Science National ChungHsing University

2 Outline Instruction Preliminaries ARM Processor SHARC Processor

3 2.1 Instructions Instructions sets The programmer s interface to the hardware Two CPUs as example ARM processor: ARM version 7 SHARK Digital signal processor (DSP)

4 2.2 Preliminaries Computer architecture taxonomy Assembly language.

5 2.2.2 Computer Architecture Taxonomy Von Neumann architecture Harvard architectures RISC vs. CISC

6 Von Neumann architecture A computer whose memory holds both data and instructions The CPU has several internal registers Program counter, general-purpose register CPU fetches instructions by program counter from memory The separation of the instruction memory from the CPU Distinguish a stored-program computer from a general finite-state machine

7 A von Neumann Architecture Computer address 200 memory ADD r5,r1,r3 data 200 PC CPU IR ADD r5,r1,r3

8 Harvard Architecture Separate memories for data and program The program counter points to the program memory Hard to write self-modifying programs Used for one very simple reason Provide higher performance for digital signal processing Most of DSPs are Harvard architectures Most of the phone calls go through at least 2 DSPs, one at each end of the phone call

9 Harvard Architecture address data memory program memory data address data PC CPU

10 von Neumann vs. Harvard Harvard cannot use self-modifying code. Harvard allows two simultaneous memory fetches. Most DSPs use Harvard architecture for streaming data: greater memory bandwidth more predictable bandwidth Streaming data Data set the arrive continuously and periodically

11 RISC vs. CISC Another axis relates to instructions and how they are executed Complex instruction set computer (CISC) A variety of instructions Reduced instruction set computer (RISC) Fewer and simpler instructions Load/store Pipelined processors

12 Instruction Set Characteristics Fixed vs. variable length. Addressing modes. Number of operands. Types of operands.

13 Programming Model Programming model: the set of registers available for use by programs Some registers are unavailable to programmer (IR).

14 2.2.2 Assembly language The textual description of instructions Basic features: One instruction per line Labels Provide names for memory location Start in the first column Instructions often start in later columns To distinguish them from labels Comments run from some designated comment character to the end of the line

15 An Example of ARM Assembly Language label1 ADR r4,c LDR r0,[r4] ; a comment ADR r4,d LDR r1,[r4] SUB r0,r0,r1 ; comment

16 Pseudo-ops Some assembler directives don t correspond directly to instructions Help programmer create complete language programs For example Define current address Reserve storage Constants

17 Pseudo-ops (Cont.) Examples In ARM: BIGBLOCK %10 ; allocate a block of 10-byete ; memory and initialize to 0

18 2.3 ARM Processor ARM is a family of RISC architecture and has been extended over several versions ARM 610, ARM7, ARM9, ARM10, ARM11 ARM 7 Von Neumann architecture machine ARM9 Harvard architecture machine We will concentrate on ARM7

19 ARM Assembly Language Fairly standard assembly language label LDR r0,[r8] ; a comment ADD r4,r0,r1

20 ARM Data Type The standard ARM word is 32 bits long Word may be divided into four 8-bit bytes ARM allow addresses to be 32 bits long An address refer to a byte, not a word Word 0 is at location 0 Word 1 is at location 4 PC is incremented by 4 in sequential access Can be configured at power-up to address the bytes in a word in either little-endian or bit-endian mode

21 Byte Organization Within an ARM Word Little-endian mode The lowest-order byte residing in the low-order bits of the word Big-endian mode The lowest-order byte stored in the highest bits of the word bit 31 bit 0 bit 0 bit 31 byte 3 byte 2 byte 1 byte 0 byte 0 byte 1 byte 2 byte 3 little-endian big-endian

22 ARM Data Operation ARM is a load-store architecture Arithmetic and logical operations cannot be performed directly on memory locations Data operands must first be loaded into the CPU and then stored back to main memory

23 ARM Programming Model ARM has 16 general-purpose registers r0~r15 r15: also used as the program counter Allow the program counter value to be used as an operand in computations

24 ARM Programming Model r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 (PC) 31 N Z C V CPSR 0

25 ARM Programming Model (Cont.) CPSR: Current Program Status Register Set automatically during every arithmetic, logical, or shifting operation Top four bits of the CPSR N: set when the result is negative in two s-complement arithmetic Z: set when every bit of the result is zero C: set when there is a carry out of the operation V: set when an arithmetic operation results in an overflow

26 ARM Status Bits Examples: = 0: NZCV = xffffffff + 0x1 = 0x0 0-1 = -1: NZCV = x0-0x1=0xffffffff

27 ARM Data Instructions Basic format: ADD r0,r1,r2 Computes r1+r2, stores in r0. Immediate operand: ADD r0,r1,#2 Computes r1+2, stores in r0 Data instructions Arithmetic Logical Shift/store

28 ARM Arithmetic Instructions ADD : add ADC : add with carry ADC r0, r1, r2; r0 = r1 + r2 + C SUB : subtract SBC : subtract with carry SUB r0, r1, r2; r0 = r1 - r2 + C -1 RSB : reverse subtract RSB r0, r1, r2; r0 = r2 r1 RSC : reverse subtract w. carry RSB r0, r1, r2; r0 = r2 r1 + C -1 MUL : multiply MLA : multiply and accumulate MLA r0, r1, r2, r3; r0 = r1 x r2 + r3

29 ARM Logical Instructions AND : Bit-wise and ORR : Bit-wise or EOR : Bit-wise exclusive-or BIC : bit clear BIC r0, r1, r2; r0 = r1 & Not(r2)

30 ARM Shift/Rotate Instructions LSL : logical shift left Fills with zeroes LSR : logical shift right ASL : arithmetic shift left = LSL ASR : arithmetic shift left Copy the sign bit to the most significant bit ROR : rotate right RRX : rotate right extended with C Performs 33-bit rotate, with the CPSR s C bit being inserted above sign bit of the word

31 ARM Comparison Instructions Do not modify registers but only set the values of the NZCV bits of the CPSR register CMP : compare CMP r0, r1; compute (r0 - r1)and set NZCV CMN : negated compare CMP r0, r1; compute (r0 + r1)and set NZCV TST : bit-wise AND test TST r0, r1; compute (r0 AND r1)and set NZCV TEQ : bit-wise exclusive-or test TEQ r0, r1; compute (r0 EOR r1)and set NZCV

32 ARM Move Instructions MOV : move MOV r0, r1; r0 = r1 MVN : move (negated) MOV r0, r1; r0 = NOT(r1)

33 ARM Load/Store instructions LDR : load word LDRH : load half-word LDRB : load byte STR : store word STRH : store half-word STRB : store byte

34 Addressing Modes Register Immediate Indirect or Register Indirect Base-Plus-Offset Base register r0 r15 Offset, and or subtract an unsigned number Immediate Register (not PC) Scaled register: only available for word and unsigned byte instructions

35 Register Indirect Addressing LDR r0,[r1] If r1 = 0x100 Set r0 = mem32[0x100] STR r0,[r1] If r1 = 0x100 Set mem32[0x100] = r0

36 Base-Plus-Offset Addressing Pre-indexing LDR r0,[r1,#4] ; r0:=mem32[r1+4] Offset up to 4K, added or subtracted, (# -4) Post-indexing LDR r0,[r1],#4 ; r0:=mem32[r1], then r1:=r1+4 Auto-indexing LDR r0, [r1,#4]! ; r0:=mem32[r1+4], then r1:=r1+4

37 ARM ADR pseudo-op Cannot refer to an address directly in an instruction. Generate value by performing arithmetic on PC. ADR provide a pseudo-operation (or pseudoinstruction) to simply the steps ADR r1, F00 ; give location 0x100 the name FOO

38 Example: C assignments C: x = (a + b) - c; Assembler: ADR r4,a LDR r0,[r4] ADR r4,b LDR r1,[r4] ADD r3,r0,r1 ADR r4,c LDR r2[r4] SUB r3,r3,r2 ADR r4,x STR r3[r4] ; get address for a ; get value of a ; get address for b, reusing r4 ; get value of b ; compute a+b ; get address for c ; get value of c ; complete computation of x ; get address for x ; store value of x

39 Example: C assignment C: y = a*(b+c); Assembler: ADR r4, b LDR r0, [r4] ADR r4, c LDR r1, [r4] ADD r2, r0,r1 ADR r4, a LDR r0, [r4] MUL r2, r2, r0 ADR r4, y STR r2, [r4] ; get address for b ; get value of b ; get address for c ; get value of c ; compute partial result ; get address for a ; get value of a ; compute final value for y ; get address for y ; store y

40 Example: C assignment C: z = (a << 2) (b & 15); Assembler: ADR r4,a ; get address for a LDR r0,[r4] ; get value of a MOV r0,r0,lsl 2 ; perform shift ADR r4,b ; get address for b LDR r1,[r4] ; get value of b AND r1,r1,#15 ; perform AND ORR r1,r0,r1 ; perform OR ADR r4,z ; get address for z STR r1,[r4] ; store value for z

41 ARM Flow of Control Branch instruction: PC-relative B #100 ; add 400 to the current PC value B LABEL ; branch a LABEL Conditional branch by testing CPSR value EQ : equal (Z = 1) NE : not equal (Z = 0) CS : carry set ( C = 1) CC : carry clear (C = 0)

42 ARM Flow of Control (Cont.) MI : minus ( N = 1) PL : nonnegative ( N = 0) VS : overflow ( V = 1) VC : no overflow ( V = 0) HI : unsigned higher ( C = 1 and Z = 0) LS : unsigned lower or same ( C = 0 or Z = 1) GE : greater than or equal ( N = V) LT : signed less than ( N!= V) GT : signed greater than ( Z = 0 and N = V) LE : signed less than or equal ( Z = 1 and N!= V)

43 Example: if statement C: if (a > b) { x = 5; y = c + d; } else x = c - d; Assembler: ; compute and test condition ADR r4,a ; get address for a LDR r0,[r4] ; get value of a ADR r4,b ; get address for b LDR r1,[r4] ; get value for b CMP r0,r1 ; compare a < b BGE fblock ; if a >= b, branch to false block

44 If statement, cont d. ; true block MOV r0,#5 ADR r4,x STR r0,[r4] ADR r4,c LDR r0,[r4] ADR r4,d LDR r1,[r4] ADD r0,r0,r1 ADR r4,y STR r0,[r4] B after ; generate value for x ; get address for x ; store x ; get address for c ; get value of c ; get address for d ; get value of d ; compute y ; get address for y ; store y ; branch around false block

45 If statement, cont d. ; false block fblock ADR r4,c LDR r0,[r4] ADR r4,d LDR r1,[r4] SUB r0,r0,r1 ADR r4,x STR r0,[r4] after... ; get address for c ; get value of c ; get address for d ; get value for d ; compute a-b ; get address for x ; store value of x

46 Example: Conditional instruction implementation ; true block MOVLT r0,#5 ADRLT r4,x STRLT r0,[r4] ADRLT r4,c LDRLT r0,[r4] ADRLT r4,d LDRLT r1,[r4] ADDLT r0,r0,r1 ADRLT r4,y STRLT r0,[r4] ; generate value for x ; get address for x ; store x ; get address for c ; get value of c ; get address for d ; get value of d ; compute y ; get address for y ; store y

47 Conditional instruction implementation, cont d. ; false block ADRGE r4,c LDRGE r0,[r4] ADRGE r4,d LDRGE r1,[r4] SUBGE r0,r0,r1 ADRGE r4,x STRGE r0,[r4] ; get address for c ; get value of c ; get address for d ; get value for d ; compute a-b ; get address for x ; store value of x

48 Example: switch statement C: switch (test) { case 0: break; case 1: } Assembler: ADR r2,test LDR r0,[r2] ADR r1,switchtab LDR r1,[r1,r0,lsl #2] switchtab DCD case0 DCD case1... ; get address for test ; load value for test ; load address for switch table ; index switch table

49 Example: FIR filter C: for (i=0, f=0; i<n; i++) f = f + c[i]*x[i]; Assembler ; loop initiation code MOV r0,#0 ; use r0 for I MOV r8,#0 ; use separate index for arrays ADR r2,n ; get address for N LDR r1,[r2] ; get value of N MOV r2,#0 ; use r2 for f

50 FIR filter, cont.d ADR r3,c ; load r3 with base of c ADR r5,x ; load r5 with base of x ; loop body loop LDR r4,[r3,r8] ; get c[i] LDR r6,[r5,r8] ; get x[i] MUL r4,r4,r6 ; compute c[i]*x[i] ADD r2,r2,r4 ; add into running sum ADD r8,r8,#4 ; add one word offset to array index ADD r0,r0,#1 ; add 1 to i CMP r0,r1 ; exit? BLT loop ; if i < N, continue

51 ARM Subroutine Linkage Branch and link instruction: BL foo Save the current PC value to r14 And then jump to foo To return from subroutine: MOV r15,r14

52 Summary Load/store architecture Most instructions are RISCy, operate in single cycle. Some multi-register operations take longer. All instructions can be executed conditionally.