ARM Cortex-M4 Programming Model Logical and Shift Instructions

Transcription

1 ARM Cortex-M4 Programming Model Logical and Shift Instructions References: Textbook Chapter 4, Sections 4.1, 4.2, 4.3, 4.5, 4.6, 4.9 ARM Cortex-M Users Manual, Chapter 3 1

2 CPU instruction types Data movement operations memory-to-register and register-to-memory includes different memory addressing options memory includes peripheral function registers register-to-register constant-to-register (or to memory in some CPUs) Arithmetic operations add/subtract/multiply/divide multi-precision operations (more than 32 bits) Logical operations and/or/exclusive-or/complement (between operand bits) shift/rotate bit test/set/reset compare Flow control operations branch to a location (conditionally or unconditionally) branch to a subroutine/function return from a subroutine/function 2

3 Bitwise Logic AND {Rd,} Rn, Op2 Bitwise logic AND. Rd Rn & operand2 ORR {Rd,} Rn, Op2 Bitwise logic OR. Rd Rn operand2 EOR {Rd,} Rn, Op2 Bitwise logic exclusive OR. Rd Rn ^ operand2 ORN {Rd,} Rn, Op2 Bitwise logic NOT OR. Rd Rn (NOT operand2) BIC {Rd,} Rn, Op2 Bit clear. Rd Rn & NOT operand2 BFC Rd, #lsb, #width Bit field clear. Rd[(width+lsb 1):lsb] 0 Bit field insert. BFI Rd, Rn, #lsb, #width Rd[(width+lsb 1):lsb] Rn[(width-1):0] MVN Rd, Op2 Move NOT, logically negate all bits. Rd 0xFFFFFFFF EOR Op2 3 Yifeng Zhu Lecture Slides

4 ARM Logic Operations A Rn B Operand2 A&B AND A B ORR A^B EOR A&(~B) BIC A (~B) ORN ~A MVN Bit-Wise Logic Instructions AND{S} {Rd,} Rn, <op2> ; Rd=Rn & op2 ORR{S} {Rd,} Rn, <op2> ; Rd=Rn op2 EOR{S} {Rd,} Rn, <op2> ; Rd=Rn ^ op2 BIC{S} {Rd,} Rn, <op2> ; Rd=Rn & (~op2) (bit clear) ORN{S} {Rd,} Rn, <op2> ; Rd=Rn (~op2) MVN{S} Rd, <op2> ; Rd=(~op2) (complement all bits)

5 To set bits Use the or operation to set selected bits of a register to 1. (The other bits remain constant.) Friendly software modifies just the bits that need to be. GPIO_PORTD_DIR_R = 0x03; // Set PD1,PD0 outputs Assembly: LDR R0,=GPIO_PORTD_DIR_R LDR R1,[R0] ; read previous value ORR R1,R1,#0x03 ; set bits 0 and 1 STR R1,[R0] ; update c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 value of R x03 constant ( mask ) c 7 c 6 c 5 c 4 c 3 c result of the ORR

6 Set a Bit (in C) or a = (1 << k) a = a (1 << k) Example: k = 5 a 1 << k a (1 << k) a 7 a 6 a 5 a 4 a 3 a 2 a 1 a a 7 a 6 1 a 4 a 3 a 2 a 1 a 0 6

7 To clear bits Use the and operation to clear selected bits of a register. GPIO_PORTD_DIR_R &= 0xFC; // PD1,PD0 inputs Assembly: LDR R0,=GPIO_PORTD_DIR_R LDR R1,[R0] ; read previous value AND R1,R1,#0xFC ; clear bits 0 and 1 STR R1,[R0] ; update c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 value of R xFC constant ( mask ) c 7 c 6 c 5 c 4 c 3 c result of the AND

8 Clear a Bit (in C) Example: k = 5 a &= ~(1<<k) a = a & ~(1<<k) a (1 << k) ~(1 << k) a & ~(1<<k) a 7 a 6 a 5 a 4 a 3 a 2 a 1 a a 7 a 6 0 a 4 a 3 a 2 a 1 a 0 8

9 Using BIC to clear bits Use the bic operation to clear selected bits of a register. GPIO_PORTD_DIR_R &= ~0x03; // PD1,PD0 inputs Assembly: LDR R0,=GPIO_PORTD_DIR_R LDR R1,[R0] ; read previous value BIC R1,R1,#0x03 ; clear bits 0 and 1 STR R1,[R0] ; update c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 value of R x03 = ~0xFC = mask c 7 c 6 c 5 c 4 c 3 c result of the AND Similar to AND, but more straightforward - bits to be cleared are designated.

10 To toggle The exclusive or operation can also be used to toggle bits. GPIO_PORTD_DATA_R ^= 0x80; /* toggle PD7 */ Assembly: LDR R0,=GPIO_PORTD_DATA_R LDR R1,[R0] ; read port D EOR R1,R1,#0x80 ; toggle bit 7 STR R1,[R0] ; update b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 value of R x80 constant ~b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 result of the EOR

11 Toggle a Bit (in C) Without knowing the initial value, a bit can be toggled by XORing it with a 1 Example: k = 5 a ^= 1<<k a 1 << k a ^= 1<<k a 7 a 6 a 5 a 4 A 3 a 2 a 1 a a 7 a 6 NOT(a 5 ) a 4 a 3 a 2 a 1 a 0 a 5 1 a Truth table of Exclusive OR with one 11

12 Switch Interfacing Not pressed Open Pressed Closed 10kΩ +3.3V s LM3S or TM4C Input port Negative logic 10kΩ +3.3V t LM3S or TM4C Input port Positive logic The and operation to extract, or mask, individual bits: Pressed = GPIO_PORTA; //true if PA6 switch pressed Assembly: LDR R0,=GPIO_PORTA LDRB R1,[R0] ; read port A ANDS R1,#0x40 ; clear all bits except bit 6 BNE SwitchSet ; branch if Switch pulled high a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 value of R x40 constant 0 a result of the AND Note: If 8-bit result is zero, then we know a 6 = 0 If the 8-bit result is non-zero, then a 6 = 1

13 Switch Interfacing Not pressed Open Pressed Closed 10kΩ +3.3V s LM3S or TM4C Input port Negative logic 10kΩ +3.3V t LM3S or TM4C Input port Positive logic The TST operation to extract, or mask, individual bits: Pressed = GPIO_PORTA; //true if PA6 switch pressed Assembly: LDR R0,=GPIO_PORTA LDRB R1,[R0] ; read port A TST R1,#0x40 ; clear all bits except bit 6 BNE SwitchSet ; branch if Switch pulled high TST performs the ANDS operation, except that the lefthand operand (R1 above) remains unchanged only the flags are set. Note: If 8-bit result is zero, then we know a 6 = 0 If the 8-bit result is non-zero, then a 6 = 1

14 Shift Operations Logical Shift Right LSR 0 Arithmetic Shift Right ASR C 1<n<32 1<n<32 Logical Shift Left LSL Rotate Shift Right ROR Rotate Right Extended RRX 0 0<n<31 1<n<32 n=1 Formats: LSL Rd, Rm, #imm ; imm = # bit positions to shift (n) LSL Rd, Rm, Rs ; Rs = # bit positions to shift (n) Use the ASR instruction when manipulating signed numbers, and use the LSR instruction when shifting unsigned numbers

15 Barrel Shifter Second ALU operand has a special hardware called Barrel shifter Shift a designated #bits left/right in one step Example: ADD r1, r0, r0, LSL #3 ; r1 = r0 + r0 << 3 = 9 r0 15

16 Shift Example High and Low are unsigned 4-bit components, which will be combined into a single unsigned 8-bit Result. Result = (High<<4) Low; Assembly: LDR R0,=High LDR R1,[R0] ; read value of High LSL R1,R1,#4 ; shift into position LDR R0,=Low LDR R2,[R0] ; read value of Low ORR R1,R1,R2 ; combine the two parts LDR R0,=Result STR R1,[R0] ; save the answer h 3 h 2 h 1 h 0 value of High in R1 h 3 h 2 h 1 h after last LSL l 3 l 2 l 1 l 0 value of Low in R2 h 3 h 2 h 1 h 0 l 3 l 2 l 1 l 0 result of the ORR instruction

17 Example: C statements C: z = (a << 2) (b & 15); Assembler: LDR r4,=a LDR r0,[r4] LSL r0,r0,#2 LDR r4,=b LDR r1,[r4] AND r1,r1,#15 ORR r1,r0,r1 LDR r4,=z STR r1,[r4] ; get address for a ; get value of a ; perform shift ; get address for b ; get value of b ; perform AND ; perform OR ; get address for z ; store value for z 17